Gebruiksaanwijzing /service van het product FS2010 van de fabrikant Agilent Technologies
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FuturePlus Systems Corporation FS2010 Users Manual For use with Agilent Logic Analyzers Revision – 1.1 Copyright 2005 FuturePlus® Systems Corporation FuturePlus is a trademark of FuturePlus Systems.
2 How to reach us ......................................................................................... 4 Product Warranty ....................................................................................... 5 Limitation of Warranty ...........
3 Use of EyeFinder/Eyescan ............................................................................. 27 Transaction Viewer .................................................................................. 28 General Information ..................
4 How to reach us For Technical Support: FuturePlus Systems Corporation 36 Olde English Road Bedford NH 03110 TEL: 603-471-2734 FAX: 603-471-2738 On the web http://www.futureplus.com For Sales and Marketing Support: FuturePlus Systems Corporation TEL: 719-278-3540 FAX: 719-278-9586 On the web http://www.
5 Product Warranty This FuturePlus Systems product has a warranty against defects in material and workmanship for a period of 1 year fr om the date of shipment. During the warranty period, FuturePlus Systems will, at its option, either replace or repair products proven to be defective.
6 Introduction The FS2010 is a 32/64 bit, 0 to 133Mhz PCI-X State and Timing adapter probe for use with Agilent logic analyzers. This card has a universal card edge connector and a 3.3v extender card c onnector. The FS2010 PCI-X State/Timing adapter probe and extender card performs three functions.
7 Analyzing the PCI-X Local Bus This chapter introduces you to the FS2010 and lists the minimum equipment required and accessories supplied for PCI-X Local Bus analysis. This chapter also contains information that is common to both state and timing analysis.
8 This operating manual uses the sa me signal notation as the PCI-X LOCAL BUS SPECIFICATION - REVISION 1.0 That is, a # symbol at the end of a signal name indicates that t he signal’s active state occurs when it is at a low voltage. The absence of a # symbol indicates that the signal is active at a high voltage.
9 *For 32 bit analysis load the timing or st ate configuration file into a single logic analyzer card. If you are using a 16910 card then only one card is required for 64 bit analysis.
10 The following explains how to connect the logic analyzer to the FS2010 for either state or timing analysis: 1. Connect the logic analyzer PODs 3 adapter cables, either the E5378A or E5385A depending on the logic analyzer cards used. 2. Plug the Adapter cables into the probe as shown in the table below.
11 To install the FS2010 software, insert the diskette labeled 16700/702 Installation disk for the FS2010 into the Agilent 16700 diskette drive. From the SYSTEM ADMINISTRATION TOOLS select INSTALL under SOFTWARE. From the SOFTW ARE INSTALL screen select the FLEXIBLE DISK and APPLY.
12 The 1680/90/900 Analyzer is a PC based application that requires a PC running Windows OS with the Agilent logic analyzer software installed or a 16900 frame. Before installing the protocol decoder for the PCI-X protocol on a PC you must install the Agilent logic analyzer software.
13 Data that is saved on a 167xx analyzer in fast binary format, or 16900 analyzer data saved as a *.ala file, can be imported into the 1680/90/900 environment for analysis. You can do offline analysis on a PC if you have the 1680/90/900 operati ng system installed on the PC, if you need this software please contact Agilent.
14 After clicking “next” you must browse for the fast binary data file you want to import. Once you have loca ted the file and clicked start import, the data should appear in the listing. After the data has been imported you must load the protocol decoder before you will see any decoding.
15 After the decoder has loaded, select Preferences if required, from the overview screen and set the preferences to their correct value in order to decode the trace properly. This is a general requirement, some decoders do not have preferences, and if this is the case then no preference setting is necessary.
16 The FS2010 diskette sets up the format menu as shown in the following table. This format is the same for both Timing and State Analysis. Label Clk Inputs Pod 6 Pod 5 Pod 4 Pod 3 Pod 2 Pod 1 ADDR 11.
17 Loading the configuration file w ill automatically load the PCI-X Transaction Decode software onto the workspace. If this does not happen then check to make sure that the PCI-X decode software was .
18 FS2010 Software and Timing mode The FS2010 Decoder should NOT be run when the logic analyzer is configured in timing mode. This will cause the system to hang. The ADDR and DATA variables in the FORMAT menu are assigned to the AD[31:0] signals on the PCI-X bus .
19 The CYCLE variable is made up of the following signals: TRDY#, FRAME#, IRDY#, C/BE(3:0), DEVSEL# , and STOP#. This variable has 27 symbols defined that can be used to help make triggering, timing analysis and pattern filtering easier. The following lists the bit pattern and the corresponding symbol.
20 The TERM CODE variable is made up of DEVSEL#, TRDY#, and STOP#. The following lists the bit pattern and the corresponding symbol. Symbol DEVSEL# TRDY# STOP# MASTER ABORT 1 1 1 SPLIT RESPONSE 1 0 1 .
21 State Analysis This chapter explains how to c onfigure the FS2010 to perform state analysis on the PCI-X Local Bus. T he configuration software sets up the format specification menu of the logic analyzer for compatibility with the PCI-X Local Bus. The next chapter explains how to configure the FS2010 to perform timing analysis.
22 For full analysis, the PCI-X wor kspace should appear as below. 167xx screenshot 169xx screenshot showing overview Configuring the Workspace for PCI-X Analysis.
23 Captured data is as shown in the following figure. The below figure displays the PCI-X transactor decode on a 167xx frame. The State Listing Display.
24 T The above figure shows the listing from the 169xx frame..
25 The FS2010 generates one output column that is sub-divided into the following sub-columns. Name Base Description CMD TEXT The command type displayed in HEX Wait The type of wait state ADDR_H TEXT The address as it appears during a 64 bit address transfer (as defined by a DAC) ADDR_L HEX The address as it appears on the lower AD lines (AD[31:0]).
26 Timing Analysis Since the FS2010 interface does not bu ffer the PCI-X bus, it introduces negligible skew to the PCI-X Local Bus signals. Load the logic analyzer configuration file. If the FS2010 software is installed, load the logic analyzer configuration file for timing from the logic/configs/FuturePlus/FS2010 directory on the 167xx analyzer.
27 Captured data is displayed as shown in the following figure. Use of Eye Finder can greatly enhanc e your timing analysis by helping find the data valid window of every signal on the bus with respect to the clock.
28 Transaction Viewer The FS2010 Protocol Decoder version 2.0 or higher is enabled to work with the FuturePlus Systems Tr ansaction Viewer. The Transaction Viewer is a powerful tool that allows the user to view PCI-X data captured with the FS2010 in a graphi cal environment that presents the information by Transaction as opposed to State.
29 General Information This chapter provides additional reference information including the characteristics and signal connections for the FS2010 module. The following operating characteristi cs are not specifications, but are typical operating characteri stics for the FS2010 module.
30 Due to the FS2010 being an interposer all signals are extended 1.2 in. in length, consisting of 57 ohm single-ended impedance etch. All PCI-X Local Bus operations ar e supported by the hardware and the inverse assembler.
31 J2 Signal Connector Signal Name/Logical Signal name Logic A nalyze r channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyze r channel number Signal name/Logical Signal Name Ground 1 2 Gr.
32 Signal Name/Logical Signal name Logic A nalyze r channel number SA MTEC Pin number SA MTEC Pin number Logic A nalyze r channel number Signal name/Logical Signal Name Ground 57 58 Ground NC Odd D13 .
33 J3 Signal Connections Signal Name/Logical Signal name Logic A nalyze r channel number SAMTEC Pin number SAMTEC Pin number Logic A nalyze r channel number Signal name/Logical Signal Name Ground 1 2 .
34 Signal Name/Logical Signal name Logic A nalyze r channel number SA MTEC Pin number SA MTEC Pin number Logic A nalyze r channel number Signal name/Logical Signal Name Ground 57 58 Ground SERR# Odd D.
35 J4 Signal Connections Signal Name/Logical Signal name Logic A nalyze r channel number SA MTEC Pin number SA MTEC Pin number Logic A nalyze r channel number Signal name/Logical Signal Name Ground 1 .
36 Signal Name/Logical Signal name Logic A nalyze r channel number SA MTEC Pin number SA MTEC Pin number Logic A nalyze r channel number Signal name/Logical Signal Name Ground 57 58 Ground AD59 Odd D1.
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