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FuturePlus ® Systems Corporation DDR SDRAM Analysis Probe FS2331 Users Manual For use with Agilent Technologies Logic Analyzers Revision 1.4 FuturePlus is a trademark of FuturePlus Systems C orporati.
2 How to reach us ....................................................................................................................... 4 Product Warranty ..............................................................................................
3 Unused Pods ................................................................................................................................... 23 Offline Analysis .....................................................................................
4 Ho w to reach us For Technical Support: FuturePlus Systems Corporation 15 Constitution Drive Bedford, NH 03110 TEL:603 - 471 - 2734 FAX:603 - 471 - 2738 On the Web: www.futureplus.com For Sales and Marketing Support: TEL:719 - 278 - 3540 FAX:719 - 278 - 9586 On the Web: www.
5 Product Warranty Due to the complex nature of the FS2331 and the wide variety of possible customer target implementations, the FS2331 has a 30 day acceptance period by the customer from the date of receipt.
6 Introduction Thank you for purchasing the FuturePlus Systems FS2331 DDR SDRAM Logic Analyzer Probe. We believe you wi ll find the FS2331, along with your Agilent Technologies Logic Analyzer, a valuable tool for helping to characterize and debug your DDR - based systems.
7 J1 E5385A adapter cables (FS1015) are used to connect to the following logic analyzer cards: 1671X, 16750/1/2/3 E5378A adapter cables (FS1014) are used to connect to the following logic analyzer car.
8 FS2331 Probe Description The FS 2331 DDR DIMM Probe allows you to perform state and timing analysis measurements on Double Data Rate DRAM DIMM busses using an Agilent logic analyzer. Probe Feature Summary • Quick and easy connection between the DDR 184 pin DIMM connector and Agilent Logic Analyzers.
9 Probe Design This probe uses discrete ECL logic in order to operate at the speed necessary to provide DDR333 signal decode. Because ECL logic operates in linear mode it dissipates more heat than other logic designs. BE ADVISED – THE PROBE IS HOT TO THE TOUCH.
10 Because strobe edges are centered on the data valid window for writes, and straddle it for reads, the analyzer cannot simply use the raw DQS0 to sample data. If it did, then even in the ideal case, only half of the data valid window would be us able.
11 Probe Pod Assignment The FS2331 DDR Probe uses 8 pods. Two are used to capture traffic on the DDR Command bus, and 6 are used for the Data bus, strobes, check bits, masks, and Serial Presence Detect signals.
12 Probe Switch Settings A switch bank of 6 independent SPST switches is provided on the FS2331 for user selection of a number of probe features. These are detailed below.
13 Logic Analyzer Signal Threshold Voltage Settings Threshold voltage settings are set at SSTL - 2 levels (1. 25 V) for all pods in the format specification of the analyzer. The user may have to adjust this setting for optimal performance for their specific target.
14 Card Requirements for PC2700 Systems In order to insure that the FS2331 and the logic analyzer work properly with PC2700 systems it is recommended that the 16753/4/5/6 cards be used when probing at DDR rates of 333Mhz or greater. This recommendation is based on several factors.
15 Logic Analyzer Card Requ irements DDR Bus Speed 16700 Analyzer Type Timing Analysis State Analysis 16717/8/9 2 cards configured as one module with one timing machine 3 cards: • 1 card module with.
16 Software Requirements System Software The FS2331 Probe requires version A.02.70.00 (or later) of the 16700 System Operating Software. You can check to see if you already have the correct version by opening the “System Administration” dialog and selecting the “Show Version” button.
17 Note: In the above picture under Logic analyzer pods, the first pod goes to the Odd pod and the second goes to the Even pod of the termination adapter (e.g. Pod B1 goes to odd termination adapter pod and B2 goes to the even termination adapter pod).
18 analyzer cards together to create multi - card modules. You may use modules that are already configured with more than two cards, but only two of the cards (8 pods) will be used for each DDR bus.
19 Load the system config file “DR230_2” for 3 card state. This file will cause all three cards to be configured for state analysis operation. The card in slot C will be setup to capture DDR Commands at the CK0 rate.
20 Connecting to your Target System – Chip Select Many DDR333 systems qualify Command activity using the Chip Select lines, S0:3. This is either because they utilize “2T Timing” in which t heir .
21 Chip Select Jumper locations 2) Dedicating a DIMM slot to the FS2331 This approach offers the highest signal integrity. It involves dedicating a DIMM slot to the FS2331, isolating the Chip Select s.
22 § Sleeve the Pin Slide a short length of insulation over the exposed con nector pin to fully protect it from contacting the barrel of the hole. Insulation from 30 AWG wire is a good fit.
23 § Wire from the adjacent DIMM slot to the isolated pin Using a short length of rework wire connect the adjacent slot’s identical pin, e.g. p in 157 for S0, to the isolated pin on the dedicated DIMM slot.
24 Offline Analysis Data that is saved on a 167xx analyzer in fast binary format, or 16900 analyzer data saved as a *.ala file, can be imported into the 1680/90/900 environme nt for analysis. You can do offline analysis on a PC if you have the 1680/90/900 operating system installed on the PC, if you need this software please contact Agilent.
25 After clicking “next” you must browse for the fast binary data file you want to import. Once you have located the file and clicked start import, the data should appear in the listing. After the data has b een imported you must load the protocol decoder before you will see any decoding.
26 Timing Analysis Operation Loading the Inverse Assembler and Decoding DDR Commands No Inverse Assembler is used for timing analysis. However, symbols are pre - defined for the DDR Command bus. These decode the RAS, CAS, and WE lines to display the DDR Command as “Read”, “Write”, “Precharge”, etc.
27 3. Trigger the analyzer on any burs t. 4. Open a new All Waves waveform window that displays measurement results from both the Command and Data analyzers. This can be done from the Workspace window by dragging a waveform display tool onto the Workspace and connecting the output of each Data an d Command analyzer to the tool.
28 Command and Data analyzers. It can take up to 100ns for the int ermodule arm signal to make it from the Command analyzer to the Data analyzer. For this reason it is not possible to guarantee a trigger on a burst at a given address which also has a given data pattern.
29 Using Eye Finder with the FS2331 DDR Probe The explanation of the procedure for calibrating the probe for optimal read and write state acquisition provides a description of some useful ways you can interpret Eye Finder results. Eye Finder can be very useful in helping characterize DDR busses.
30 Using EyeScan with the FS2331 Probe EyeScan is a feature available on Agilent 16760 and 16753/4/5/6 logic analyzer cards. It provides the ability to perform eye measurements on multiple channels simultaneously. For more detailed information on the use of the feature refer to the Help files for either logic analyzer.
31 Using the FS2331 DDR Probe with an Interposer (FS1024/25) An interposer with the FS2331 is recommended if the user w ants to see the activity in a specific DIMM slot or with a specific DIMM module.
32 FS2331 Calibration The FS2331 is calibrated for operation at DDR333 rates, this should be sufficient for it’s ope ration. In the event that Data eye closure is seen during Eyefinder or Eyescan of simultaneous Writes and Reads, then the FS2331 calibration may need adjustment.
33.
34 Notice in this display the data valid windows for DATA31 - 0 and DATA64 - 32 are reduced in size. This is because the measured windows represent the intersection of the read and write windows. Notice also that there is almost no data valid window for the strobes.
35 The blue lines show the default logic analyzer sample position. The dark gray areas show periods of time in which the indicated signals are not stable, and the remaining areas indicate where the signals are stable with respect to the clock.
36 • Not all of the Address l ines had activity. This is indicated by the “I” symbol. To see which lines had no activity, place the cursor on the Address label and click the right mouse button. Select the “Expand” pick to see the Eye Finder measurement for each Address line.
37 Notice that this m easurement was taken with one of the Chip Select lines hooked up. You can see that its data valid window is smaller than that of the other command bus signals. This is due largely to the use of soldered wires to connect the Chip Select signal.
38 Once Eye Finder is running at an accepta ble rate you will be able to evaluate the data valid window positions and sizes. Below is a typical display: Several things can be inferred from inspection of the Eye Finder results: • You will often see two complete data valid windows, one on each side o f the analyzer clock.
39 • Not all channels have a data valid window after the clock. This is because the cl ock for data bursts is active on both rising and falling edges of the strobe.
40 The correct logic analyzer sample position for the data valid windows is just to the left of (before) th e analyzer clock. This ensures that the data being sent by the controller prior to issuing the strobe is the data sampled by the analyzer.
41 After these adjustments you should see an Eye Finder display like the above: At this point you should make a note of the sampling position for the data lines. In the diagram above it is indicated as - 2.45ns average for all data lines. This number will be used later when choosing the proper adjustment for the read burst delay line.
42 indicating its nominal delay value in 100ps units. Thus a 1700ps delay line will be marked “1705” and a 1200ps d elay line will be marked “1205”. The delay lines are accurate to within +/ - 50ps) To measure the read burst data valid position, start the stimulus on the DDR bus .
43 • The read strobes straddle the data, as they should for read cycles. • The read data valid windows are about the same size as the write ones were. In many systems however you should not be surprised to find the read windows appreciably smaller than the write windows.
44 The average sample position for the data lines during these read bursts is – 2.25ns . This Eye Finder measurement was taken with a read delay line setting of 1.8ns. You now have enough information to calculate what an optimal read delay setting would be to capture both read and write bursts.
45 Step 4 – Adju st the delay line value to maximize R/W overlap You can use the following formula to calculate the proper value for the read delay line that will maximize overlap between read and write data valid windows: New U18 Delay Line Value = Current U18 Delay Line Value + (Avg.
46 Notice in this display the data valid windows are reduced in size. This is because the measured windows represent the intersection of the read and write windows.
47 General Information This chapter provides additional reference information includ ing the characteristics and signal connections for the FS2331 DDR Analysis Probe. The following operating characteristics are not specifications, but are typical operating characteristics for the HyperTransport Analysis Probe.
48 Signal Connections J1 Data Signal Name/Logical Signal name Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number S ignal name/Logical Signal Name Ground 1 .
49 Signal Name/Logical Signal name Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number S ignal name/Logical Signal Name Ground 57 58 Ground DQ18 Odd D13 59 .
50 J2 Data and Command Signal Name/Logical Signal name Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer chan nel number Signal name/Logical Signal Name Ground 1 2 Groun.
51 Signal Name/Logical Signal name Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer chan nel number Signal name/Logical Signal Name DQ25 Odd D13 59 60 Even D13 SPARE Gr.
52 J3 Command and Data Signal Name/Logical Signal name Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Sign al name/Logical Signal Name Ground 1 2 Groun.
53 Signal Name/Logical Signal name Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Sign al name/Logical Signal Name S1n Odd D13 59 60 Even D13 DQ38 Grou.
54 J4 Data Signal Name/Logical Signal name Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name Ground 1 2 Ground NC 3 4 NC G.
55 Signal Name/Logical Signal name Logic Analyzer channel number SAMTEC Pin number SAMTEC Pin number Logic Analyzer channel number Signal name/Logical Signal Name DQS7 Odd D13 59 60 Even D13 DM7/DQS16.
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