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18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture CY7C1370D CY7C1372D Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05555 Rev .
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 2 of 28 Selection Guide 250 MHz 200 MHz 167 MHz Unit Maximum Access T ime 2.6 3.0 3.4 ns Maximum Operating Curren t 350 300 275 mA Maximum CMOS S.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 3 of 28 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQa DQa V DDQ V SS DQa DQ.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 4 of 28 Pin Configurations (continued) 234 5 6 7 1 A B C D E F G H J K L M N P R T U DQ a V DDQ NC/576 M NC/1G DQ c DQ d DQ c DQ d AA A A AV DDQ .
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 5 of 28 Pin Configurations (continued) 234 5 67 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c .
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 6 of 28 Pin Definitions Pin Name I/O T ype Pin Description A0 A1 A Input- Synchronous Address Inputs used to select one of the addres s locations . Sa mpled at the rising e dge of the CLK. BW a BW b BW c BW d Input- Synchronous Byte Write Select Input s, active LOW .
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 7 of 28 Introduction Functional Overview The CY7C1370D and C Y7C1372D are synchronous-pipeli ned Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transi tions. All synchronous input s pass through input registers co ntrolled by the rising ed ge of the clock.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 8 of 28 Asserting the Write Enable input (WE ) with the selected Byte Write Select (BW ) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 9 of 28 Notes: 1. X = “Don't Care”, H = Lo gic HIGH, L = Logic L OW , CE stands fo r ALL Chip Ena bles active.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 10 of 28 Partial Write Cycle Description [1, 2, 3, 8] Function (CY7C1370D) WE BW d BW c BW b BW a Read H X X X X Write – No bytes written L H H.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 1 1 of 28 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1370D/CY7C1372D incorpora tes a serial boundary scan test access por t (T AP). This p art is fully compliant with 1 149.1. The T AP operates using JEDEC-standard 3.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 12 of 28 When the T AP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board -level serial test data path.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 13 of 28 in the T AP controller , i t will directly control the state of the output (Q-bus) pins, when t he EXTEST is entered as the current instruction. When HIGH, it will e nable the output buffers to drive the output bus.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 14 of 28 3.3V T AP AC T est Conditions Input pulse levels ... ............... .............. .............. .. V SS to 3.3V Input rise and fall times ......... ........ ........... ... ...........
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 15 of 28 Identification Register Definitions Instruction Field CY7C137 2D CY7C1370D Description Revision Number (31:29) 000 000 Reserved for version number . Cypress Device ID (28:12) [12] 0101 1001000100101 0101 1001000010101 Reserved for future use.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 16 of 28 1 19-Ball BGA Boundary Scan Order [13, 14] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 H4 23 F6 45 G4 67 L1 2T 4 2 4 E 7 4.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 17 of 28 165-Ball BGA Boundary Scan Order [13, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1N 6 3 1 D 1 0 6 1G 1 2N 7 3 2 C 1 1 6 2 D 2 3N 1 0 .
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 18 of 28 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T e mperature ............. .............. ...... –65 °C to +150°C Ambient T emperature with Power Applied .
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 19 of 28 Note: 18. T ested initially and af ter any design or proc ess chan ge that may affect these p arameters. Cap acit ance [18] Parameter Description T est Conditions 1 00 TQ FP Max. 1 19 BGA Max.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 20 of 28 Switching Characteristics Over the Operating Range [23, 24] Parameter Descriptio n –250 –200 –167 Unit Min. Max. Min. Max. Min. Max. t Power [19] V CC (typical) to the first access read or write 1 1 1 ms Clock t CYC Clock Cycle T ime 4.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 21 of 28 Switching W aveforms Read/Wri te/Timing [25, 26, 27] Notes: 25. For this waveform ZZ is tied LOW. 26. When C E is LOW, CE 1 is LOW , C E 2 is HIGH and CE 3 is LOW . When CE is HIGH,CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 22 of 28 Notes: 28. The Ignore Clock Edge or St all cycle (Clock 3) illustrated CEN being used to create a p ause. A write is not perfor m ed durin g this cycle. 29. Device must be deselected when entering ZZ mode.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 23 of 28 Ordering Information Not all of the spe ed, package and temperature ran ges are available. Please contact your local sales r epresentative or visit www .cypress.com for actual pro duct s offered.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 24 of 28 250 CY7C1370D-250AXC 51-8 5050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1372D-250AXC CY7C1370D-250BGC 51-851 15 1 1 9-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372D-250BGC CY7C1370D-250BGXC 51-851 15 1 1 9-ball Ball Grid Array (14 x 22 x 2.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 25 of 28 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 26 of 28 Package Diagrams (continued) 1.27 20.32 2 16 5 4 37 L E A B D C H G F K J U P N M T R 12.00 19.50 30° TYP. 2.40 MAX. A1 CORNER 0.70 REF. U T R P N M L K J H G F E D C A B 21 43 65 7 Ø1.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 27 of 28 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce.
CY7C1370D CY7C1372D Document #: 38-05555 Rev . *F Page 28 of 28 Document History Page Document Title: CY7C1372D/CY7C1370D 18-Mbit (512 K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05555 REV .
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