Gebruiksaanwijzing /service van het product CY7C1380F van de fabrikant Cypress
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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 18-Mbit (512K x 36/1M x 18) Pipelined SRAM Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-05543 Rev .
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 2 of 34 Logic Block Diagram – CY7C1380D/CY7C1380F [3] (512K x 36) Logic Block Diagram – CY7C1382D/CY7C1382F [3] (1M x 1.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 3 of 34 Pin Configurations 100-Pin TQFP Pinout (3-Chip Enable) Figure 1. CY7C1380D, CY7C1380F(51 2K X 36) F igure 2.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 4 of 34 1 19-Ball BGA Pinout Figure 3. CY7C1380F (512K X 36) Figure 4. CY7C1382F (1M X 18) 234 5 6 7 1 A B C D E F G H J K .
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 5 of 34 165-Ball FBGA Pinout (3-Chip Enable) Figure 5. CY7C1380D/CY7C1380F (512 K x 36) Figure 6.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 6 of 34 T able 1. Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address inputs used to select one o f the address locations . Samp led at the rising edge of the CLK if ADSP or ADSC is active L OW , and CE 1 , CE 2 , and CE 3 [2] are sampled active.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 7 of 34 MODE Input-S tatic Selects burst order . When tied to GND selects linear burst sequence. When tied to V DD or left floating selects interleaved burst sequence. This i s a strap pin a nd must remain static during device operation.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 8 of 34 Functional Overview All synchronous inputs pass through input registe rs controlled by the rising edge of the clock. All data outputs pass through output registers controlled by th e ri sing ed ge of the clock.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 9 of 34 Burst Sequence s The CY7C1380D/CY7C1382D/C Y7C1380F/CY7C138 2F provides a two-bit wraparound counter , fed by A1: A0, that imple- ments an interleaved or a linear burst sequence.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 10 of 34 T ruth T able The T ruth T able for this data sheet follows. [4, 5, 6, 7, 8] Operation Add.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 1 1 of 34 T ruth T able for Read/Write [4, 9] Function (CY7C1380D/CY7C13 80F) GW BWE BW D BW C BW B BW A R e a d H HXXXX R .
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 12 of 34 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1380D/CY7C1382D incorpora tes a serial boundary scan test access port (T AP).Thi s part is fully compliant wi th 1 149.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 13 of 34 When the T AP controller is in the Capture-IR state, the two least significant bits are loade d with a binary ‘ 01’ pattern to enable fau lt isolation of the board-level serial te st data path.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 14 of 34 when the EXTEST is entered as the current instruction. When HIGH, it enables the output b uffers to drive the output bus. When LOW , this bit pl aces the output bus into a High-Z conditi on.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 15 of 34 3.3V T AP AC T est Conditions Input pulse levels .............. .............. .............. ....... V SS t o 3.3V Input rise and fall tim es. ............. .......
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 16 of 34 Identification Regi ster Definitions Instruction Field CY7C1380D/CY7C1380F (512K x 36) CY7C1382D/CY7C1382F (1 Mbit x 18) Description Revision Number (31:29) 000 000 Describes the version number .
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 17 of 34 1 19-Ball BGA Bounda ry Scan Order [14, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 H4 23 F6 45 .
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 18 of 34 165-Ball BGA Bounda ry Scan Order [14, 16] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2N 7 3 2 C .
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 19 of 34 Maximum Ratin gs Exceeding the maximu m ratings may impair the usefu l life of the device. For user guidelines, n ot tested. S torage T emperature ................ .
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 20 of 34 Cap acitance [19] Parameter Description T est C onditions 100 TQFP Package 1 19 BGA Package 165 FBGA Package Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 21 of 34 Figure 9. AC T est Loads and Waveforms OUTPUT R = 317 Ω R = 351 Ω 5p F INCLUDING JIG AND SCOPE (a) (b) OUTPUT R L = 50 Ω Z 0 = 50 Ω V T = 1.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 22 of 34 Switching Characteristics Over the Operating Range [20, 21] Parameter Description 25 0 MHz 200 MHz 167 MHz Unit Min Max Min Max Min Max t POWER V DD (T ypical) to the first Access [22] 1 11 ms Clock t CYC Clock Cycle T ime 4.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 23 of 34 Switching W aveforms Figure 10. Read Cycle Timing [26] t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES GW, BWE, BWx Data Out (Q) High-Z t CLZ t DOH t CO ADV t OEHZ t CO Single READ BURST READ t OEV t OELZ t CHZ ADV suspends burst.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 24 of 34 Figure 1 1 . Write Cycle Timing [26, 27] Switching W aveforms (continued ) t CYC t CL CLK ADSP t ADH t ADS ADDRESS.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 25 of 34 Figure 12. Read/Write Cycle Timing [26, 28, 29] Switching W aveforms (continued ) t CYC t CL CLK ADSP t ADH t ADS .
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 26 of 34 Figure 13. ZZ Mode T iming [30, 31] Switching W aveforms (continued ) t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes 30.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 27 of 34 Ordering Information The follow ing t able list s all speed, pac kage and temp erature ra ng e options. Please note tha t some options listed belo w may not be available for order entry .
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 28 of 34 Speed (MHz) Ordering Code Package Diagram Part and Packa ge T ype Operating Range 200 CY7C1380D-200AXC 51-8 5050 100-pin Thin Quad Flat Pack (14 x 20 x 1.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 29 of 34 Speed (MHz) Ordering Code Package Diagram Part and Packa ge T ype Operating Range 167 CY7C1380D-167AXC 51-8 5050 100-pin Thin Quad Flat Pack (14 x 20 x 1.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 30 of 34 Package Diagrams Figure 14. 100-Pin Thin Plastic Quad Flat Pack (14 x 20 x 1.4 mm) (51-85050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 31 of 34 Figure 15. 1 19-Ba ll BGA ( 14 x 22 x 2.4 mm) (51-851 15) Package Diagrams (continued) 51-851 15-*B [+] Feedback.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 32 of 34 Figure 16. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180) Package Diagrams (continued) A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø 0 . 2 5MCAB Ø0.
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 33 of 34 Document History Page Document Title: CY7C1380D/CY7C13 82D/CY7C1380F/CY7C1 382F , 18-Mbit (512K x 36/1M x 18) Pipelined SRAM Document Number: 38-05543 REV . ECN NO. Submission Date Orig.
Document #: 38-05543 Rev . *F Revised January 12, 20 09 Page 34 of 34 All product s and comp any names me ntioned in this document may be the t rademarks of the ir respecti ve holders. CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F © Cypress Semicondu ctor Corporati on, 2006-2009.
Een belangrijk punt na aankoop van elk apparaat Cypress CY7C1380F (of zelfs voordat je het koopt) is om de handleiding te lezen. Dit moeten wij doen vanwege een paar simpele redenen:
Als u nog geen Cypress CY7C1380F heb gekocht dan nu is een goed moment om kennis te maken met de basisgegevens van het product. Eerst kijk dan naar de eerste pagina\'s van de handleiding, die je hierboven vindt. Je moet daar de belangrijkste technische gegevens Cypress CY7C1380F vinden. Op dit manier kan je controleren of het apparaat aan jouw behoeften voldoet. Op de volgende pagina's van de handleiding Cypress CY7C1380F leer je over alle kenmerken van het product en krijg je informatie over de werking. De informatie die je over Cypress CY7C1380F krijgt, zal je zeker helpen om een besluit over de aankoop te nemen.
In een situatie waarin je al een beziter van Cypress CY7C1380F bent, maar toch heb je de instructies niet gelezen, moet je het doen voor de hierboven beschreven redenen. Je zult dan weten of je goed de alle beschikbare functies heb gebruikt, en of je fouten heb gemaakt die het leven van de Cypress CY7C1380F kunnen verkorten.
Maar de belangrijkste taak van de handleiding is om de gebruiker bij het oplossen van problemen te helpen met Cypress CY7C1380F . Bijna altijd, zal je daar het vinden Troubleshooting met de meest voorkomende storingen en defecten #MANUAl# samen met de instructies over hun opplosinge. Zelfs als je zelf niet kan om het probleem op te lossen, zal de instructie je de weg wijzen naar verdere andere procedure, bijv. door contact met de klantenservice of het dichtstbijzijnde servicecentrum.
