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72-Mbit(2M x 36/4M x 18/1M x 72) Pi p elined SRAM with NoBL™ Architecture CY7C1470V25 CY7C1472V25 CY7C1474V25 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05290 Rev .
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 2 of 28 A0, A1, A C MODE BW a BW b WE CE1 CE2 CE3 OE READ LOGIC DQs DQP a DQP b D A T A S T E E R I N G O U T P U T B U F F E R S.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 3 of 28 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQa DQa V.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 4 of 28 Pin Configurations (continued) 23 4 567 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 5 of 28 Pin Configurations (continued) A B C D E F G H J K L M N P R T U V W 1 2 3 4 56 78 9 1 1 10 DQg DQg DQg DQg DQg DQg DQg D.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 6 of 28 ADV/LD Input- Synchronous Advance/Load Inp ut used to advance the on-chip ad dress counter or load a new add ress . When HIGH (and CEN is asserted L OW) the internal burst co unter is advanced.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 7 of 28 Functional Overview The CY7C1470V25/CY7C1472V25 /CY7C1474V25 are synchronous-pipel ined Burst NoBL SRAMs designed specifi- cally to eliminate wait states during Write/Read transitions.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 8 of 28 CY7C1474V25, BW a,b,c,d for CY7C1470V25 and BW a,b for CY7C1472V25) inputs must be dr iven in each cycle of the burst write in order to writ e the correc t bytes of data. Sleep Mode The ZZ input pin is an asynchronous input.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 9 of 28 Partial Write Cycle Description [1, 2, 3, 8] Function (CY7C1470 V2 5) WE BW d BW c BW b BW a Read H X X X X Write – No .
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 10 of 28 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1470V25/CY7C147 2V25/CY7C1474V25 incorpo- rates a serial boundary scan test access port (T AP) . This port operates in accordance with IEEE S tandard 1 149.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 1 1 of 28 Instruction Register Three-bit instructions can be serially loaded into the instruction register . This register is loa ded when it is placed betwe en the TDI and TDO ba lls as show n in the T ap Contro ller Block Diagram.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 12 of 28 possible to capture all other signals an d simply ignore the value of the CLK captured in the bounda ry scan reg ister . Once the data is captured, it is possible to shift out the data by putting the T AP into the Shift-DR state.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 13 of 28 2.5V T A P AC T est Conditions Input pulse levels ... ............... ........... .............. ..... V SS to 2.5V Input rise and fall time ........... .............. ...
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 14 of 28 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Bit S i ze (x72) I n s t r u c t i o n 333 B y p a s s 1.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 15 of 28 Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 1 65-Ball ID 1C 1 2 1 R 3.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 16 of 28 Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 2 09-Ball ID 1 A1 29 T1 5.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 17 of 28 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65 °C to +150°C Ambient T emp erature with Power Applied .
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 18 of 28 Cap acit ance [14] Parameter Description T est Condition s 100 TQFP Max. 165 FBGA Max. 209 FBGA Max. Unit C ADDRESS Address Input Capacit ance T A = 25 ° C, f = 1 MHz, V DD = 2.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 19 of 28 Switching Characteristics Over the Operating Range [15, 16] Parameter Description –250 –200 –167 Unit Min. Max. Min. Max. Min. Max. t Power [17] V CC (typic al) to the First Access Read or Write 1 1 1 ms Clock t CYC Clock Cycle T i me 4.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 20 of 28 Switching W aveforms Read/Write/T iming [21, 2 2, 23] Notes: 21. For this waveform ZZ is tied LOW. 22. When CE is LOW , CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW . When CE is H IGH,CE 1 is HIGH o r CE 2 is LOW or CE 3 is HIGH.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 21 of 28 NOP , ST ALL and DESELECT Cycles [21, 22, 24] ZZ Mode T iming [25, 26] Notes: 24. The IGNORE CLOCK EDGE or ST ALL cycle (Clock 3) illustrated CEN being used to create a pause.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 22 of 28 Ordering Information Not all of the speed, package and temperature ranges are available. Please co ntact your local sales representative or visit www .cypress.com for actual pro duct s offered.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 23 of 28 250 CY7C1470V25-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead -Free Commercial CY7C1472V25-250AXC CY7C1470V25-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Arra y (15 x 17 x 1.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 24 of 28 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 25 of 28 Package Diagrams (continued) A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.45±0.05(165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35 1.40 MAX. SEATING PLANE 0.53±0.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 26 of 28 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce.
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 27 of 28 Document History Page Document Title: CY7C1470 V25/CY7C1472V25/CY7C14 74V25 72-Mbit(2M x 36/4M x 18/1M x 72 ) Pipelined SRAM with NoB L™ Architecture Document Number: 38-05290 REV .
CY7C1470V25 CY7C1472V25 CY7C1474V25 Document #: 38-05290 Rev . *I Page 28 of 28 *I 472335 See ECN VKN Corrected the typo in the pi n configuration fo r 209-Ball FBGA pinout (Corrected the ball name for H9 to V SS from V SSQ ). Added the Maximum Rating for Supply Vo ltage on V DDQ Relative to GND.
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