Gebruiksaanwijzing /service van het product CY7C1472V33 van de fabrikant Cypress
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72-Mbit (2M x 36/4M x 18/1M x 72) Pi p elined SRAM with NoBL™ Architecture CY7C1470V33 CY7C1472V33 CY7C1474V33 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05289 Rev .
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 2 of 29 A0, A1, A C MODE CE1 CE2 CE3 OE READ LOGIC DQ s DQ P a DQ P b DQ P c DQ P d DQ P e DQ P f DQ P g DQ P h D A T A S T E E R.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 3 of 29 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQa DQa V.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 4 of 29 Pin Configurations (continued) 234 56 7 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 5 of 29 Pin Configurations (continued) A B C D E F G H J K L M N P R T U V W 12 34 5 6 7 89 1 1 10 DQg DQg DQg DQg DQg DQg DQg DQ.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 6 of 29 Pin Definitions Pin Name I/O T ype Pin Description A0 A1 A Input- Synchronous Address In p uts used to select one of the add re ss locations . Sampled at the rising edge of the CLK.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 7 of 29 Functional Overview The CY7C1470V33, CY7 C1472V33, and CY7C1474V33 are synchronous-pipel ined Burst NoBL SRAMs designed specifi- cally to eliminate wait states during Write/Read transitions.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 8 of 29 On the next clock rise the data presented to DQ and DQP (DQ a,b,c,d, e,f,g,h /D QP a,b,c,d,e,f,g,h for CY7C1474V33, DQ a,.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 9 of 29 Notes: 1. X = “Don't Care”, H = Lo gic HIGH, L = Logic L OW , CE stands fo r ALL Chip Ena bles active.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 10 of 29 Partial Write Cycle Description [1, 2, 3, 8] Function (CY7C1470 V3 3) WE BW d BW c BW b BW a Read H X X X X Write – No.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 1 1 of 29 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1470V33, CY7C1 472V33, and CY7C1474V33 incorporates a serial bounda ry scan test access port (T AP). This port operates in accordance with IEEE S tandard 1 149.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 12 of 29 Instruction Register Three-bit instructions can be serially loaded into the instruction register . This register is loa ded when it is placed betwe en the TDI and TDO ba lls as show n in the T ap Contro ller Block Diagram.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 13 of 29 possible to capture all other signals an d simply ignore the value of the CLK captured in the bounda ry scan reg ister . Once the data is captured, it is possible to shift out the data by putting the T AP into the Shift-DR state.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 14 of 29 3.3V T AP AC T est Conditions Input pulse levels ............... .............. .............. ..... V SS to 3.3V Input rise and fall times ......... ........ ... ... ....
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 15 of 29 Identification Register Definitions Instruction Field CY7C1470V33 (2M x 36) CY7C1472V33 (4M x 18) CY7C1474V33 (1M x 72) .
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 16 of 29 Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165 -Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1C 1 2 1 R 3.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 17 of 29 Boundary Scan Exit Order (1M x 72) Bit # 2 09-Ball ID Bit # 209-Ball ID Bit # 209 -Ball ID Bit # 209-Ball ID 1 A1 29 T1 .
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 18 of 29 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65 °C to +150°C Ambient T emp erature with Power Applied .
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 19 of 29 Cap acit ance [15] Parameter Description T est Co nd itions 100 TQFP Max. 165 FBGA Max. 209 FBGA Max. Unit C ADDRESS Address Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 20 of 29 Switching Characteristics Over the Operating Range [16, 17] Parameter Description –250 –200 –167 Unit Min. Max. Min. Max. Min. Max. t Power [18] V CC (typical) to the First Access Read or Write 1 1 1 ms Clock t CYC Clock Cycle T ime 4.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 21 of 29 Switching W aveforms Read/Write/T iming [22, 2 3, 24] Notes: 22. For this waveform ZZ is tied LOW. 23. When CE is LOW , CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW . When CE is H IGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 22 of 29 NOP , ST ALL and DESELECT Cycles [2 2, 23 , 25 ] ZZ Mode T iming [26, 27] Notes: 25. The IGNORE CLOCK EDGE or ST ALL cycle (Clock 3) illustrated CEN being used to create a pause.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 23 of 29 Ordering Information Not all of the speed, package and temperature ranges are av ailable. Please contact your local sales representative or visit www .cyp ress.com for actual products offered.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 24 of 29 250 CY7C1470V33-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1472V33-250AXC CY7C1470V33-250BZC 51-85165 165-ball Fine-Pitc h Ball Grid Array (15 x 17 x 1.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 25 of 29 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 26 of 29 Package Diagrams (continued) A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.45±0.05(165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35 1.40 MAX. SEATING PLANE 0.53±0.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 27 of 29 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce.
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 28 of 29 Document History Page Document Title: CY7C1470 V33/CY7C1472V33/CY 7C14 74V3 3 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05289 REV .
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document #: 38-05289 Rev . *I Page 29 of 29 *H 416221 See ECN RXU Converted from Prelimin ary to Final Changed address of Cypress Semico nductor Corporation on Page.
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