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72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-15013 Rev .
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 2 of 30 Logic Block Diagram – CY7C1471BV25 (2M x 36) Logic Block Diagram – CY7C1473BV25 (4M x 18) C MODE BW A BW B WE CE.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 3 of 30 Logic Block Diagram – CY7C1475BV25 (1M x 72) A0, A1, A C MODE CE1 CE2 CE3 OE READ LOGIC DQ s DQ Pa DQ Pb DQ Pc DQ .
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 4 of 30 Pin Configurations A A A A A1 A0 NC/288M NC/144M V SS V DD A A A A A A DQP B DQ B DQ B V DDQ V SS DQ B DQ B DQ B DQ .
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 5 of 30 Pin Configurations (continued) A A A A A1 A0 NC/288 M NC/144M V SS V DD A A A A A A A NC NC V DDQ V SS NC DQP A DQ A.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 6 of 30 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm ) Pinout CY7C1471BV25 (2M x 36) 234 56 7 1 A B C D E .
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 7 of 30 Pin Configurations (continued) A B C D E F G H J K L M N P R T U V W 12 3 45 6 7 8 9 1 1 10 DQg DQg DQg DQg DQg DQg .
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 8 of 30 T able 1. Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address Inpu t s Used to Select One of the Address Locations . Samp led at the rising edge of the CLK.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 9 of 30 Functional Overview The CY7C1471BV25, CY7C1473BV25 , and CY7C1475BV25 are synchronous flow through burst SRAMs designed specifi- cally to eliminate wait states during write read transitions.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 10 of 30 included to greatly simplify re ad/modify/write seque nces, which can be reduced to simple byte write operations. Because the CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25 are common IO devices, data must not be driven into the device while the outputs are active.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 1 1 of 30 T a ble 4. T ruth T able The truth table for CY7C1471BV25, CY7C1473BV25, and CY7C1475 BV25 follows.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 12 of 30 T able 5. T ru th T able for Re ad/Write The read-write truth table for CY7C1471BV25 follows.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 13 of 30 IEEE 1 149.1 Serial Boun dary Scan (JT AG) The CY7C1471BV25, CY7C1473BV25 , and CY7C1475BV25 incorporate a serial bounda ry sca n T est Access Port (T AP) . This port operates in accordance with IEEE S tandard 1 149.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 14 of 30 T AP Registers Registers are connected between the TDI and TDO balls and enable the scanning of data into and out of the SRAM test circuitry . Only on e register is selectable at a time through the instruction register .
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 15 of 30 no guarantee as to the value that is captured. Repeatable results may not be possible .
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 16 of 30 2.5V T AP AC T est Conditions Input pulse levels .................... .............. ........... .... V SS to 2.5V Input rise and fall time ............... ..........
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 17 of 30 T able 8. Iden tification Reg ister Definitions Instruction Field CY7C1471BV25 (2MX36) CY7C1473BV25 (4MX18) CY7C147.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 18 of 30 T able 1 1. Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ba ll ID Bit # 165-B a.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 19 of 30 T a ble 13. Boun dary Scan Exit Orde r (1M x 72 ) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ba ll ID Bit # 209-.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 20 of 30 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature ...................
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 21 of 30 Cap acit ance T ested ini tially and after any design or process change that may affect these parameters. Parameter Description T est Condit ions 100 TQFP Max 165 FBGA Max 209 FBGA Max Unit C ADDRESS Address Input Capacit ance T A = 25 ° C, f = 1 MHz, V DD = 2.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 22 of 30 Switching Characteristics Over the Operating R ange. Timing reference level is 1.25V when V DDQ = 2.5 V . T est conditions shown in (a) of “AC T est Loads and W aveforms” on page 21 unless otherwise noted.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 23 of 30 Switching W aveforms Figure 8 shows read-write timing waveform. [19, 20, 21] Figure 8.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 24 of 30 Figure 9 shows NOP , ST ALL and D ESELECT Cycles waveform. [19, 20, 22] Figure 9.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 25 of 30 Figure 10 shows ZZ Mode timing waveform. [23, 24] Figure 10. ZZ Mode Timing Switching W aveforms (continued) t ZZ I.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 26 of 30 Ordering Information Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www .cypress.com for actual products offered.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 27 of 30 Package Diagrams Figure 1 1. 100-Pin Thin Plastic Quad F latpack (14 x 20 x 1.4 mm), 51-85050 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 28 of 30 Figure 12. 165-Ball F BGA (15 x 17 x 1 .4 mm), 51-85165 Package Diagrams (continued) A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.45±0.05(165X) Ø0.25 M C A B Ø0.
CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev . *E Page 29 of 30 Figure 13. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167 Package Diagrams (continued) 51-85167-* * [+] Feedback.
Document #: 001-15013 Rev . *E Re vised February 29, 2008 Page 30 of 30 NoBL and No Bu s Latency are trademar ks of Cypress Semicondu ctor Co rporation. ZBT is a trademark of Integrat ed Device T echn ology , Inc. All products and company names me ntioned in this document may be the tr ademarks of their respe ctive hold er s.
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