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PRELIMIN ARY CY8CNP102B, CY8CNP102E N onvolatile Programmable System-on-Chip ( PSoC® NV) Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-43991 Rev .
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 2 of 38 Logic Block Diagram [+] Feedback.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 3 of 38 Pinout s Figure 1. Pin Diag ram - 100- Pin TQFP Pa ckage (14 x 14 x 1.4 mm) T able 1.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 4 of 38 18 P5_7 IO GPIO 19 P5_5 IO GPIO 20 P5_3 IO GPIO 21 P5_1 IO GPIO 22 P1_7 IO I2C Serial Clock (SCL), GPIO 23 P1_5 IO I2C Se.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 5 of 38 PSoC NV Functional Overview The PSoC NV provides a versatile microcontroller core (M8C), Flash program memo ry , nvSRAM dat a memory , and configurable analog and digital peripheral blocks in a single package.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 6 of 38 Programmable Digit al System The digital system cont ains 16 digital PSoC blocks. Each block is an 8-bit resource that is used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, whi ch are called user module references.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 7 of 38 Development T ools PSoC Designer is a Microsoft ® Windows b ased, integrated development environment for Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and ap plication run on Windows NT 4.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 8 of 38 Online Help System The online help system displays onl ine, context sensitive help for the user . Design ed for procedural and quick referen ce, each functional subsystem has its ow n context sensitive help.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 9 of 38 The last step i n the development process takes place i nside the PSoC Designer ’s Debugger subsystem. The Debugger downloads the HEX image to the In -Circuit Emulator (ICE) where it runs at full speed.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 10 of 38 3.3V Operation Absolute M aximum Ratin gs Operating T emperature T able 3. 3.3V Absolute Maximum Ratings (CY8CN P102B) Symbol Description Min Ty p Max Units Notes T STG S torage T emperature -55 25 +100 o C Higher storage temperatures reduce data retention time.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 1 1 of 38 DC Electrical Characterist ics The following DC electrical specifications list the guaranteed maximum and minimum sp ec ifications for the voltage and temperatu re range: 3.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 12 of 38 DC Operational Amplifi er Specifications The Operational Amplifier is a component of both the Analog Co n tinuous T ime PSoC blo cks and the Analog Switched Capacitor PSoC blocks.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 13 of 38 DC Analog Output Bu ffer Specifications T able 9. 3.3V DC Analog Output Buffer S pecifications (CY8CNP102B) Symbol Descr.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 14 of 38 DC Analog Reference Spe cifications The guaranteed specificat ions are measured through the Analog Continuo us T ime PSoC blocks. The power levels for AGND re fer to the power of the Analog C ontinuous T i me PSoC block.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 15 of 38 DC POR, SMP , and L VD Specifications T able 12. 3.3V DC POR, SMP , and L VD Specifications (CY8CNP102B) Symbol Description Min Ty p Max Unit s Vdd V alue for PPOR T rip (positive ramp) V PPOR0 R PORLEV[1:0] = 00b 2.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 16 of 38 DC Programming Specifications T able 13. 3.3V DC Programmi ng Specifications (CY8 CNP102B) Symbol Description Min Ty p Max Units Notes I DDPV Supply Current During Programming or V erify – 10 30 mA V ILP Input Low V oltage During Programming or V erify – – 0.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 17 of 38 AC Electrical Characterist ics The following AC electrical sp ecifications list the guaranteed maximum and minimum specifications for the voltage and temperatu re range: 3.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 18 of 38 In the following table, t HRECALL starts from the time Vcc rises above V SWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE occurs. Industrial grade devices require 15 ms maximum.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 19 of 38 AC Operational Amplifier Specifications Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Ti me PSoC block. AC Digital Block Specifications T able 17.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 20 of 38 AC Analog Output Buffer Specifications CRCPRS (PRS Mode) Maximum Input Clock Frequency – – 24.6 MHz 3.0V ≤ Vcc ≤ 3.6V CRCPRS (CRC Mode) Maximum Input Clock Frequency – – 24.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 21 of 38 AC Programming Specifications AC I 2 C Specif ications T able 20. 3.3V AC Programmi ng Specifications (CY8CNP10 2B) Symb.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 22 of 38 5V Operation Absolute M aximum Ratin gs Operating T emperature T able 22. 5V Absolute Maximum Ratings (CY8CNP102E) Symbol Description Min Ty p Ma x Unit s Notes T STG S torage T emperature -55 25 +10 0 o C Higher storage temperatures reduce data retention ti me.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 23 of 38 DC Electrical Characterist ics The following DC electrical specifications l ists the guaranteed maximum and minimum sp ecifications for the voltage and temperat ure ranges: 4.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 24 of 38 DC Operational Amplifier Specificati ons The Operational Amplifier is a co mponent of both the Anal og Continuous T ime PSo C blocks and the Analog Switched Capacitor PSoC blocks.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 25 of 38 DC Analog Output Bu ffer Specifications DC Analog Reference Spe cifications The guaranteed specificat ions are measured through the Analog Continuo us T ime PSoC blocks. The power levels for AGND re fer to the power of the Analog C ontinuous T i me PSoC block.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 26 of 38 DC Analog PSoC NV Block Specifications DC POR, SMP , and L VD Specifications T able 30. 5V DC Analog PSoC NV Block Specifications (CY8CNP102E) Symbol Description Min Ty p Max Units R CT Resistor Unit V alue (Contin uous Time) – 12.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 27 of 38 DC Programming Specifications T able 32. 5V DC Programming Specifications (CY8CNP102E) Symbol Description Min Ty p Max Units Notes I DDPV Supply Current During Programming or V erify – 10 30 mA V ILP Input Low V oltage Durin g Programming or V e rify – – 0.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 28 of 38 AC Electrical Characterist ics The following AC electrical specifications lists the guaranteed ma ximum and minimu m s pecifications for the voltage and temperat ure range: 4.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 29 of 38 In the following table, t HRECALL st arts from the time Vcc rises above V SWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no ST ORE takes place.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 30 of 38 AC Operational Amplifier Specifications Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Ti me PSoC block. AC Digital Block Specifications T able 36.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 31 of 38 AC Analog Output Buffer Specifications CRCPRS (CRC Mode) Maximum Input Clock Frequency – – 24.6 MHz 4.75V ≤ Vcc ≤ 5.25V . SPIM Maximum Input Clock Frequency – – 8.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 32 of 38 AC Programming Specifications AC I 2 C Specif ications T able 39. 5V AC Programming Specifications (CY8CNP102E) Symbol D.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Page 33 of 38 Switching W aveforms Figure 8. Au toStore /Power Up RECAL L Figure 9. PLL Lock T iming Diagram Figure 10.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Pa ge 34 of 38 Figure 1 1. External Cryst al O scillator St artup Timing Diagram Figure 12. 24 MHz Period Jitter (IMO) Timing Diagram Figure 13. 32 kHz Period Jitter (ECO) Timing Diagram Figure 14.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Pa ge 35 of 38 Part Numbering Nomenclature C Y 8 C N P 1 0 2 B - A X I Cypres s Microc ontroller C = CMOS NP = PSoC NV Family Processor Type: 1 = M8C (PSoC1 Based) Density: 01 = 1Mb 02 = 2Mb 12 = 512Kb B = 3 .
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Pa ge 36 of 38 Packaging Information This section describes the packaging specifica tions for t he PSoC NV device an d the thermal impedances for TQFP package. Note Emulation tools may require a larg er area on the target PCB than the chip’s footprint.
PRELIMINARY CY8CNP102B, CY8CNP102E Document #: 001-43991 Rev . *D Pa ge 37 of 38 Document History Page Document Title: CY8CNP102B/CY8CNP102E Nonvol atile Programmable System-o n-Chip (PSoC® NV) Document Number: 001-43991 REV .
Document #: 001-43991 Rev . *D Revised October 20 , 2008 Page 38 of 38 PSoC Designer™, Programmable System-on-Chip ™, an d PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress S em iconductor C orp. All other tra demarks or register ed trademarks refer enced herein ar e property of the re spective corpor ations.
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