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PmPPC7448: PowerPC™-Based Processor PMC Module User’s Manual from Emerson Network Power ™ Embedded Computing September 2007.
The informatio n in this manu al has been che cked and is beli eved to be accu rate and reli - able. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY EMERSON NETWORK POWER, EMBEDDED COMPUTING FOR ITS USE OR FOR ANY INACCURACIES. S pecifications are sub- ject to change without noti ce.
10006757-02 P mPPC7448 User’s Manual i Regulatory Agency Warnings & Notices The Emerson P mPPC7448 meet s the requi reme nts set forth by t he Federal Communica- tions Commission (FCC) in Title 47 of the Code of Federal Regu lations. The fo llowing infor- mation is provided as re quired by this agency.
Regulatory Agency Warnings & Notices (continued) PmPPC7448 User’s Manual 10006757-02 ii EC Declaration of Conformity According to EN 45014:1998 Manufacturer’s Na me: Emerson Network Power Embe.
10006757-02 P mPPC7448 User’s Manual iii Contents 1O v e r v i e w Components and Features . . . . . . . . . . . 1-1 Functional Overv iew . . . . . . . . . . . . . . . . 1-3 Physical Memory Map . . . . . . . . . . . . . . . 1-4 Additional I nformation .
Contents (continued) PmPPC7448 User’s Manual 10006757-02 iv Interrupt Pendin g Register (IPR) . . . 7-4 Product ID Register (PIR) . . . . . . . . . . . . . .7-5 EReady Register (ERdy) . . . . . . . . . . . . . . .7-5 Revision Registers . . . . . . .
Contents (continued) 10006757-02 P mPPC7448 User’s Manual v saveenv . . . . . . . . . . . . . . . . . . . . . .11-17 setenv . . . . . . . . . . . . . . . . . . . . . . . .11-17 Test Commands . . . . . . . . . . . . . . . . . . 11-17 diags . . . . . .
PmPPC7448 User’s Manual 10006757-02 vi (blank page ).
10006757-02 P mPPC7448 User’s Manual vii Figures Figure 1-1: General System Blo ck Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Figure 1-2: PmPPC7448 Memory Map . . . . . . . . . . . . . . . .
PmPPC7448 User’s Manual 10006757-02 viii (blank page ).
10006757-02 P mPPC7448 User’s Manual ix Tables Table 1-1: Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Table 1-2: Regulatory Agenc y Compliance . . . . . . . . .
PmPPC7448 User’s Manual 10006757-02 x (blank page ).
10006757-02 P mPPC7448 User’s Manual xi Registers Register 3-1: MPC7448 Hardware Imp lementation Dependent, HID0 . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Register 3-2: MPC7448 Hardware Imp lementation Dependent, HID1 . . . . . . . . . . .
PmPPC7448 User’s Manual 10006757-02 xii (blank page ).
10006757-02 PmPPC7448 User’s Manual 1-1 Section 1 Overview The Emerson PmPP C7448 module is a Processor PCI Mezzani ne Card (PPMC). It is ba sed on the Freescale® Semiconductor Po werPC™ MPC7 448 central p rocessor unit and prov ides additional processing power for the b aseboar d, which must be compat ible with PPMC architecture.
Overview: Components and Features PmPPC7448 User’s Manual 10006757-02 1-2 Note: GbE ports (0 and 1) are routed through the PHYs di rectly to connector P14.
Overview: Functional Ov erview 10006757-02 PmPPC7448 User’s Manual 1-3 FUNCTIONAL OVERVIEW The following block diagram provi des a functional overview for the PmPPC7448: Figure 1-1: General System B.
Overview: Physical Memory Map PmPPC7448 User’s Manual 10006757-02 1-4 PHYSICAL MEMORY MAP Fig. 1-1 illustrates the PmPPC7448 mem ory map: Figure 1-2: PmPPC7448 Memory Map 8000,0000 C000,0000 F810,00.
Overview: Physical Memory Map 10006757-02 PmPPC7448 User’s Manual 1-5 Table 1-1 su mmarizes the physical addresses for the PmPPC7448 and provides a refere nce to more detailed information: Table 1-1: Address Summary 1.If Monarch, read only; if non- Monarch, write on ly.
Overview: Additional Information PmPPC7448 User’s Manual 10006757-02 1-6 ADDITIONAL INFORMATION This section lists the PmPPC744 8 hardware regulatory certifications and briefly discu sses the terminology and notat ion conventions used in this manual.
Overview: Additional Information 10006757-02 PmPPC7448 User’s Manual 1-7 Note: EMC tes ting was perfor med with out the front panel se rial or Ethernet cables installed. These ports are for debug purposes only. Also, EMC test ing was not performed for t he configuration with the taller heatsink (for 15 mm connector stackup).
Overview: Additional Information PmPPC7448 User’s Manual 10006757-02 1-8 RoHS Compliance The PmPPC7448 is compli ant with the European Uni on’s RoHS (Restriction of Use of Haz- ardous Substances) .
Overview: Additional Information 10006757-02 PmPPC7448 User’s Manual 1-9 3.Frequently, the most current information regarding ad denda/e rrata for specif ic documents may be found on the corres ponding web site. Ethernet KSZ8721CL 3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver Data Sheet (Micrel® Inc.
PmPPC7448 User’s Manual 10006757-02 1-10 (blank page ).
10006757-02 P mPPC7448 User’s Manual 2-1 Section 2 Setup This chapter describes the physical layout of the boa rds, the setup process, and how to check for proper operat ion once the boards have been inst alled. This chapt er also includes troubleshooting, service, and warranty information.
Setup: PmPPC7448 Circuit Board PmPPC7448 User’s Manual 10006757-02 2-2 The following figures show the component maps for t he PmPPC7448 circuit board.
Setup: PmPPC7448 Circuit Board 10006757-02 P mPPC7448 User’s Manual 2-3 Figure 2-2: Component Map, Bottom (Rev . 06) C189 C245 C91 C249 C248 C274 C261 C263 C250 C265 C73 C251 C231 C215 C180 C247 C24.
Setup: PmPPC7448 Circuit Board PmPPC7448 User’s Manual 10006757-02 2-4 Connectors The PmPPC7448 has the following conne ctors: P1: This mini-USB (universal seri al bus) is the connection to the fron t panel 10/100 PHY Ether- net (port 2). Refer to Table 6-2 for the pin assignments.
Setup: PmPPC7448 Circuit Board 10006757-02 P mPPC7448 User’s Manual 2-5 LEDs The PmPPC7448 ha s fifteen green light-em itting diodes (LEDs) on the back side of the board (see Fig.
Setup: PmPPC7448 Circuit Board PmPPC7448 User’s Manual 10006757-02 2-6 Front Panel The PmPPC7448 has a single-wid e PPMC front pa nel wit h an Electrom agnetic Interferenc e (EMI) gasket. Note: The electr omagnetic compa tibility (EMC) test s used a PmPPC74 48 model that includ es a front panel assembly from Emerson.
Setup: PmPPC7448 Circuit Board 10006757-02 P mPPC7448 User’s Manual 2-7 Reset The reset signals are routed to the CPL D, unl ess stated otherwise. See Chapter 7 for the reset registers. The following sources can reset the PmPPC74 48: Power-on: This causes a hard reset to the entire board, incl uding the PCI interfaces.
Setup: PmPPC7448 Setup PmPPC7448 User’s Manual 10006757-02 2-8 Figure 2-5: Reset Diagram PMPPC7448 SETUP You need the following item s to set up and chec k the operation of th e Emerson PmPPC7448: .
Setup: PmPPC7448 Setup 10006757-02 P mPPC7448 User’s Manual 2-9 Caution: Do not install the boa rd in a rack or remove th e board from a rack while pow er is applied, at risk of damage to the board. Power Requirements Be sure your power supply is sufficient for th e PmPPC7448 circui t board.
Setup: PmPPC7448 Setup PmPPC7448 User’s Manual 10006757-02 2-10 Installing the Module Most PPMC-comp atible bas eboards have two sets of fo ur connector s (J11, J12 , J13, J14 and J21, J22, J2 3, J24), as defined b y the PMC standard P1 386.1. This allows th e PmPPC7448 to be installed i n either PPMC slo t.
Setup: Troubleshooting 10006757-02 P mPPC7448 User’s Manual 2-11 3 Align the P11 and P12 connect ors and gently press the module into pl ace until firmly mated. Caution: To avoid damaging the module and/or base board, do not force the module onto the baseboard.
Setup: Troubleshooting PmPPC7448 User’s Manual 10006757-02 2-12 ❐ Be sure the PmPPC7448 module is seated fi rmly on the PPMC host and t hat the PPMC host is seated firmly in the ca rd cage. ❐ Verify the boot ju mper setting i f the DMC is installe d (see page 10-9).
Setup: Troubleshooting 10006757-02 P mPPC7448 User’s Manual 2-13 Figure 2-8: Serial Num ber and Product ID on Bottom Side Product Repair If you plan to return the board to Emerson Network Power for service, visi t http://www.emersonem beddedcom puting.
Setup: Troubleshooting PmPPC7448 User’s Manual 10006757-02 2-14 Emerson Net work Power, Embedded Co mputing Test and Re pair Servic es Depart ment 8310 Excelsio r Drive Madison, WI 53717 RMA #__________ __ Please put the RMA number on the outside of the package so we can handle your problem efficiently.
10006757-02 P mPPC7448 User’s Manual 3-1 Section 3 Central Processing Unit This chapter is an overvi ew of the processor logic on the Pm P PC7448. It includes informa- tion on the CPU, exception handling, and ca c he memory.
Central Processing Unit: Processor Reset PmPPC7448 User’s Manual 10006757-02 3-2 Figure 3-1: MPC7448 Bl ock Diagram PROCESSOR RESET Circuitry on the PmPPC7448 mo dule resets the processor and the board.
Central Processing Unit: Processor Initia lization 10006757-02 P mPPC7448 User’s Manual 3-3 Hardware I mplementatio n Dependent 0 Register The Hardware Imple mentation Dep endent 0 (HID0 ) register contains bits for CPU-sp ecific features. Most of these bi ts are cleared on in itial power-up of the PmPPC74 48.
Central Processing Unit: Processor Initia lization PmPPC7448 User’s Manual 10006757-02 3-4 XAE: Extended Addressing Enabled 0 Disabled; the 4 MSB bits of the 36-bit physical ad dress are cleare d, 3.
Central Processing Unit: Processor Initia lization 10006757-02 P mPPC7448 User’s Manual 3-5 BHT: Branch History Tabl e Enable 0D i s a b l e d 1 Allows use of dynamic prediction 2048-entry BHT NOPDS.
Central Processing Unit: Exception Handling PmPPC7448 User’s Manual 10006757-02 3-6 PAR: Disable Precharge for ARTRY*, SHD0 *, and SHD1* pins 0 Signals d riven high whe n negated 1 Signals not drive.
Central Processing Unit: Exception Handling 10006757-02 P mPPC7448 User’s Manual 3-7 Instruction Fetch: Synchronous precise exceptions ar e taken in strict program order. Instruction Disp atch/Execution: Imprecise exceptions are dela yed until higher priority exce ptions are taken.
Central Processing Unit: Exception Processing PmPPC7448 User’s Manual 10006757-02 3-8 EXCEPTION PROCESSING When an excepti on occurs, the addr ess saved in Machine S tatus Save/Resto re register 0 (SRR0) helps d etermine where instruction pro c essing should resume when the exception handler returns control to the interrupted process .
Central Processing Unit: Exception Processing 10006757-02 P mPPC7448 User’s Manual 3-9 Register 3-3: CP U Machine State Register (MSR) VEC: AltiVec vector uni t available 0 Prevents AltiVec instruct.
Central Processing Unit: Cache Memory PmPPC7448 User’s Manual 10006757-02 3-10 SE: Single-Step Trace enable 0 Executes instructions normally 1 Single-step trace ex ception generated BE: Branch Tr ac.
Central Processing Unit: Cache Memory 10006757-02 P mPPC7448 User’s Manual 3-11 L2 Cache The internal 1 megabyte L2 cache i s an eight-way set associ ative instruction and data cache with ECC capability. Th e L2 cache is fully pipe lined to provide 32 bytes per clock to the L1 caches.
Central Processing Unit: Cache Memory PmPPC7448 User’s Manual 10006757-02 3-12 L2HWF: L2 Hardware Flush 0F l u s h d i s a b l e d 1 Flush enab led LVRAME: LVRAM enable 0 LVRAM mode disa bled 1L V R.
10006757-02 P mPPC7448 User’s Manual 4-1 Section 4 On-Card Memory Configuration The PmPPC7448 inc ludes the following me mory devices: • Up to 64 megabytes of Flash memory • Synchronous DRAM (SD.
On-Card Memory Configuration: On-Card SDRAM PmPPC7448 User’s Manual 10006757-02 4-2 If booting from user Flash, th e MV64460 cont ro ller initia lly maps one megabyte ad dressing of Flash memory (beginning at FF80,0000 16 ) at the top of the address space.
On-Card Memory Configuration: NVRAM Allocation 10006757-02 P mPPC7448 User’s Manual 4-3 Table 4-3: NVRAM Memo ry Map Address Offset (hex): Name: Window Size (bytes): 0x1E14-0x1FFF Reserved 492 0x1E0.
PmPPC7448 User’s Manual 10006757-02 4-4 (blank page ).
10006757-02 P mPPC7448 User’s Manual 5-1 Section 5 System Controller The Marvell MV64460 is an integrate d system controller with a PCI interface and communi- cation ports for high performa nce embedded cont rol applications.
System Controller: CPU Interface PmPPC7448 User’s Manual 10006757-02 5-2 CPU INTERFACE CPU interface featu res include: • 32-bit address and 64 -bit data buses • Support for Symmetrical Mu lti-P.
System Controller: Device Controller Interface 10006757-02 P mPPC7448 User’s Manual 5-3 • Up to 166 MH z clock frequency • Support for 256 megabyte s to 2 gigabytes • Up to two giga bytes addr.
System Controller: Internal (IDMA) Controller PmPPC7448 User’s Manual 10006757-02 5-4 Device Control Registers Each bank has its ow n parameters register an d can be programmed to 8, 1 6, or 32-bits wide. The device int erface consists of 128 byte s of write buffer and 128 bytes of read buffer.
System Controller: PCI Interface 10006757-02 P mPPC7448 User’s Manual 5-5 PCI Configura tion Space The PCI slave s upports Type 00 c onfiguration s pace header a s defined in th e PCI specifica - tion. The MV64 460 is a multi-fu nction devic e and the heade r is implemen ted in all fiv e functions.
System Controller: PCI Interface PmPPC7448 User’s Manual 10006757-02 5-6 Figure 5-3: Example PCI0 Address Map, Monarch Figure 5-4: Example P CI0 Address Map, Non-Monarch (Defaul t) 0000,0000 8000,00.
System Controller: PCI Bus Control Signals 10006757-02 P mPPC7448 User’s Manual 5-7 PCI Interface Registers PCI0 and PCI1 contain th e same set of internal register s, but are located at different offsets. A CPU access to the MV 64460 PCIx Configur atio n register is performed via the PCIx Config- uration Address and Data registers.
System Controller: PCI Bus Control Signals PmPPC7448 User’s Manual 10006757-02 5-8 C/BE[7:4 ]*: BUS COMMAND and BYTE E NABLES During the a ddress phase, the actua l bus command is transferred, otherwis e these bits are reserv ed. During a data pha se the lines are used a s byte enabl es.
System Controller: PCI Bus Control Signals 10006757-02 P mPPC7448 User’s Manual 5-9 PRESENT*: PRESENT When groun ded, this in put signal ind icates to a c arrier that a PPM C module is installed. RESET_OUT*: RESET OUTPUT This output signa l may be used to support a reset butto n or other reset source on the PPMC module.
System Controller: PMC Connector Pinouts PmPPC7448 User’s Manual 10006757-02 5-10 PMC CONNECTOR PINOUTS Each connector has 64 pins (see Fi g. 5-6 on page 5-12). P11 and P12 Pin Assignments P11 and P12 suppo rt the 32-bit PCI bus con nectors (see Table 5- 1 ).
System Controller: PMC Connector Pinouts 10006757-02 P mPPC7448 User’s Manual 5-11 P13 and P14 Pin Assignments P13 and P14 route the 64 -bit PCI, SIO, and Ethe rnet conf iguration signals to th e backplane. Eight general purpose input/output (GPIO) pi ns are provid ed on P14—these a re routed directly from the MV6446 0 multipurp ose pins.
System Controller: PMC Connector Pinouts PmPPC7448 User’s Manual 10006757-02 5-12 The following signals for the PCI inte rface are availabl e on connector P14 . GPIOx: GENERAL PURPOSE INPUT OUTPUT The se I/O signals (TTL) a re connected to MV64 460 MPP[19, 21:27] .
System Controller: Doorbell Registers 10006757-02 P mPPC7448 User’s Manual 5-13 DOORBELL REGISTERS The MV64460 uses the doorbell registers in the messaging unit (MU) to request interrupts on both the PCI and CPU buses.
System Controller: 66 MHz Bus Operation PmPPC7448 User’s Manual 10006757-02 5-14 66 MHZ BUS OPERATION Conventional PCI: In order fo r the PCI b us to operat e at 66 MHz, al l devices on the bus must be capable o f that speed.
10006757-02 P mPPC7448 User’s Manual 6-1 Section 6 Ethernet Interface The PmPPC7448 provides three ind ependent full du plex Ethernet p orts. Using the Marvell MV64460, these ports ar e configured to one 10/100 Mbps Medi a Independent Interface (MII) and two 10/100/100 0 Mbps Gigabit MII (GMII).
Ethernet Interface: Ethernet Address PmPPC7448 User’s Manual 10006757-02 6-2 ETHERNET ADDRESS The Ethernet add ress for your board is a un ique identifie r on a network and must n ot be altered. The ad dress consists of 48 (MA C[47:0] ) bits di vided into two equal parts.
Ethernet Interface: Ethernet Connection (P1) 10006757-02 P mPPC7448 User’s Manual 6-3 Figure 6-1: Front P anel Ethernet Connec tor (P1) Table 6-2: Front Panel Eth ernet Pin Assignments (P1) Figure 6-2: Ethernet Ca ble Assemb ly Caution: The Mini -USB cable conn ection to P1 does not have a lockin g mechanism.
PmPPC7448 User’s Manual 10006757-02 6-4 (blank page ).
10006757-02 P mPPC7448 User’s Manual 7-1 Section 7 CPLD This chapter li sts the regis ters implem ented by the c omplex progra mmable logic d evice (CPLD).
CPLD: Reset Registers PmPPC7448 User’s Manual 10006757-02 7-2 Register 7-2: Reset Comman d Register (RCR) at 0xf820,1000 SCL: Serial I 2 C Clock 1 T ri-states the PLD 0D r i v e s l o g i c l o w SD.
CPLD: Interrupt Registers 10006757-02 P mPPC7448 User’s Manual 7-3 SW: Software PCI reset driven when on-board hard reset is caused by a wr ite to the Reset Command regis- ter. 1E n a b l e d 0D i s a b l e d WD: WatchDog PCI reset driven when on-boa rd reset is caused by a timeout of the WatchDog timer.
CPLD: Interrupt Registers PmPPC7448 User’s Manual 10006757-02 7-4 Interrupt Enable Register (IER) Register 7-4: PmPPC7448 Interrupt Enable Register (IER) at 0xf820,2000 R: Reserved (default is 000) .
CPLD: Product ID Register (PIR) 10006757-02 P mPPC7448 User’s Manual 7-5 PRODUCT ID REGISTER (PIR) This read-only register identi fies the board as PmPPC7448.
CPLD: Board Configuration Registers PmPPC7448 User’s Manual 10006757-02 7-6 Hardware V ersion Register (HVR) Register 7-8: Hardware Vers ion Register (HVR) at 0xf820,7000 HVR: Hardware Version number This is hard c oded in the PL D and change s with every major PCB version.
CPLD: Board Configuration Registers 10006757-02 P mPPC7448 User’s Manual 7-7 DMC: Development Me zzanine Card insta llation option 1 DMC is installed 0 DMC is not inst alled Register 7-11: PmPPC7448.
PmPPC7448 User’s Manual 10006757-02 7-8 (blank page ).
10006757-02 P mPPC7448 User’s Manual 8-1 Section 8 Serial Input/Output The PmPPC7448 has two EIA-232 serial po rts. These ports operate be tween 9600 and 115,200 baud. Soft ware selects the spee d and these settings are stored in non-volatile memory.
Serial Input/Output: I2C Interface PmPPC7448 User’s Manual 10006757-02 8-2 BRGx Tuning Register A baud tuning mechanism adjusts the generated clock rat e to the receive clock rate. When baud tuning is enable d, the baud tuning mech anism monitors for a start bit (for example high-to-low transition ).
Serial Input/Output: I/O Connection 10006757-02 P mPPC7448 User’s Manual 8-3 Table 8-2: Front Panel Seri al Port Pin Assi gnments (P2) 1.Signals (pin s 2 and 3) can be swit ched as a factory build option.
PmPPC7448 User’s Manual 10006757-02 8-4 (blank page ).
10006757-02 P mPPC7448 User’s Manual 9-1 Section 9 Real-Time Clock The standard real- time clock (RTC) for th e PmPPC7448 is p rovided by an M41T 00 device from STMicroelectronics. Th is device has an integrat ed year-2000-c ompatible RTC, power sense circuitry, and uses eight bytes of non-vol atile RAM for the clock/calendar fu nction.
Real-Time Clock: Clock Operation PmPPC7448 User’s Manual 10006757-02 9-2 1 Seconds register 2 Minutes register 3 Century/Hours register 4 Day register 5 Date register 6 Month register 7 Years register 8 Control register The M41T00 clock co ntinually monitors the suppl y voltage (Vcc) for an out of tolerance condition .
Real-Time Clock: Clock Operation 10006757-02 P mPPC7448 User’s Manual 9-3 ST: Stop bit 1=Stops t he oscillator 0=Restarts the oscillator within one second CEB: Century Enable Bit 1=Causes CB to togg.
PmPPC7448 User’s Manual 10006757-02 9-4 (blank page ).
10006757-02 P mPPC7448 User’s Manual 10-1 Section 10 Development Mezzanine Card The Developme nt Mezzanine Card (DMC) is an opti onal plug-on card mounted on the bac k of the PmPPC7448 b oard to expedite p roduc t development.
Development Mezzanine Card: DMC Circuit Board PmPPC7448 User’s Manual 10006757-02 10-2 Figure 10-1: DMC Com ponent Maps, Top and Bottom (Revision 01) Serial Numbers Before you insta ll the DMC in a system, you shoul d record the follo wing information: ❐ The board serial number: 667C- ____________ _____________ _____________ .
Development Mezzanine Card: Connectors 10006757-02 P mPPC7448 User’s Manual 10-3 It is useful to have these nu mbers available when you contact Technical Support or Test and Repair Services at Emerson Network Power.
Development Mezzanine Card: Connectors PmPPC7448 User’s Manual 10006757-02 10-4 1. When pin 75 is grounded, this no tifies the PmPPC7448 that a DM C module is attached—presenc e detect (PD). 3.3 V: 3.3 V is the power supply to the DMC (analog). CPLD_TCK: PLD Test Cloc k is an input to DMC and part of t he PLD JTAG in terface.
Development Mezzanine Card: Connectors 10006757-02 P mPPC7448 User’s Manual 10-5 DMC_OE*: Output Enable for DMC Flash i s an input to DMC. WE0*: Write Enable for DMC Flash is an input to DMC. LA(17:2): Latched Address for DMC Fl ash is an input to DMC.
Development Mezzanine Card: Connectors PmPPC7448 User’s Manual 10006757-02 10-6 P2 EIA-232 Interface Use the standard serial cable, Emers o n part number C00076 62-00, to access connector P2 .
Development Mezzanine Card: PmPPC7448 to DMC JTAG 10006757-02 P mPPC7448 User’s Manual 10-7 PMPPC7448 TO DMC JTAG Figure 10-4: PmPPC7448 to DMC JTAG Block Diagram P3 JTAG/COP The JTAG/COP interface provides for bo undary-scan testing of the CPU and the PmPPC7448.
Development Mezzanine Card: PmPPC7448 to DMC JTAG PmPPC7448 User’s Manual 10006757-02 10-8 Table 10-4: DMC P3 Pin Assignment s 2. Pin 14 is no t installed. MPC7448 CKSTP_OUT*: Checkstop Out put—when asserted, this output si gna l indicates that the CPU has detect ed a checkstop condition an d has ceased operation.
Development Mezzanine Card: DMC Jumpers (JP1) 10006757-02 P mPPC7448 User’s Manual 10-9 Table 10-5: DMC P4 Pin Assignment s CPLD_TCK: Test Clock Input—this is the clo ck input to the boundary scan test (BST) c ircuitry. Some operations occur at the rising edge, wh ile others occur at the falling edg e.
Development Mezzanine Card: Debug/Status LEDs PmPPC7448 User’s Manual 10006757-02 10-10 JP3: This is a user-defined j umper. JP4: JP4 is the MV6446 0 serial ROM configurat ion jumper. If JP4 is instal led, the MV64460 wil l not try to configure from the serial ROM.
Development Mezzanine Card: DMC Setup 10006757-02 P mPPC7448 User’s Manual 10-11 DMC SETUP You need the following item s to set up an d check the ope ration of the Emerson DMC.
Development Mezzanine Card: DMC Setup PmPPC7448 User’s Manual 10006757-02 10-12 Figure 10-8: DMC Loc ation on PmPPC7448 684- XXXXXX 1000XXXX-XX SP ARE ENET BOOT JP3 JP4 CPLD JT AG COP/JT AG PORT 1 P.
Development Mezzanine Card: Troubleshooting 10006757-02 P mPPC7448 User’s Manual 10-13 TROUBLESHOOTING In case of difficulty, use thi s checklist: ❐ Be sure the PmPPC7448 mod ule is seated firmly on the baseboard and t hat the baseboard is s eated firmly in the c ard cage.
Development Mezzanine Card: Troubleshooting PmPPC7448 User’s Manual 10006757-02 10-14 Emerson Net work Powe r Test and Re pair Servic es Depart ment 8310 Excelsio r Drive Madison, WI 53717 RMA #__________ __ Please put the RMA number on the outside of t he package so we can handle your problem efficiently.
10006757-02 P mPPC7448 User’s Manual 11-1 Section 11 Monitor The PmPPC7448 moni tor is based on the Uni ver sal Boot (U-Boot) program, available under the GNU General Public License (GPL). Fo r instru ctions on ho w to obtain the source code for this GPL progra m, please vis it http://www .
Monitor: Basic Operation PmPPC7448 User’s Manual 10006757-02 11-2 Figure 11-1: Exampl e Monitor Start-up Disp lay BASIC OPERATION The PmPPC7448 mon itor performs various conf igura tion tasks upon power-up or reset. This section desc ribes the monitor operation durin g initializati on of the PmPPC7448 board.
Monitor: Basic Operation 10006757-02 P mPPC7448 User’s Manual 11-3 Figure 11-2: Power-up/Reset Sequence Flowchart RESET Initialize HID0 Initialize MSR Relocate the base of the MV64460 internal regis.
Monitor: Monitor Recovery and Updates PmPPC7448 User’s Manual 10006757-02 11-4 POST Diagnostic Results The PmPPC7448 Powe r-On Self-Test (POST ) diagnostic results ar e stored as a 32-bit valu e in I 2 C NVRAM at the offset 0x1DD8-0x1DDB.
Monitor: Monitor Recovery and Updates 10006757-02 P mPPC7448 User’s Manual 11-5 1 Issue the following com mand, where serial_number is the board’s serial numb er, at the monitor prompt: PM/PPC-7448 (1.8) => moninit serial_num ber If the monitor recovers, skip to step 5.
Monitor: Monitor Recovery and Updates PmPPC7448 User’s Manual 10006757-02 11-6 PM/PPC-7448 (1.8) => moninit serial_num ber 100000 If moninit( ) fails, bu rn the new monitor to a ROM and fol low the recovery steps in “Recov- ering the Monitor” on page 11 -4.
Monitor: Monitor Recovery and Updates 10006757-02 P mPPC7448 User’s Manual 11-7 KatanaQp(1.0.a) => protect off e8100000 e8a3ffff KatanaQp(1.0.a) => erase e8100000 e8a3f fff KatanaQp(1.0.a) => cp.b 90100000 e81000 00 200000 6 From the KatanaQP console, compare the copi ed data to the original.
Monitor: Accessing the Console Over Ethernet PmPPC7448 User’s Manual 10006757-02 11-8 ACCESSING THE CONSOLE OVER ETHERNET To interact with the monitor command line ov er Ethernet, use the Ne tConsole feature built into the monitor an d an appropriate clien t application.
Monitor: Boot Commands 10006757-02 P mPPC7448 User’s Manual 11-9 Command S yntax The monitor uses the fo llowing basic command syn tax: <Command> <argument 1> <argument 2> <ar gument 3> • The command l ine accepts three different argument format s: string, numeric, and symbolic.
Monitor: Boot Commands PmPPC7448 User’s Manual 10006757-02 11-10 bootelf The bootelf command boots from an ELF image in memory, where address is the load address of the ELF im age. DEFINITION: bootelf [addr ess] bootm The bootm command boots an appl ication image st ored in memory, passing any entered arguments to the called ap plicatio n.
Monitor: Memory Commands 10006757-02 P mPPC7448 User’s Manual 11-11 dhcp The dhcp command invokes a Dynamic Host Configuration Prot ocol (DHCP) client to obtain IP and boot parameters by sendin g ou t a DHCP request and wa iting for a response from a server.
Monitor: Memory Commands PmPPC7448 User’s Manual 10006757-02 11-12 DEFINITION: cmp [.b, .w, .l] addr1 addr2 count cp The cp command copies count objects located at the source address to the target address. If the target address is located in th e range of the Flash dev ice, it will pro gram the Flash with count objects from th e source address.
Monitor: Memory Commands 10006757-02 P mPPC7448 User’s Manual 11-13 mm The mm command modifies me mory one objec t at a time. Once started, the command line prompts for a n ew value at th e starting a ddress. After a ne w value is entered, pressing ENTER auto-increments the a ddress to the next locati on.
Monitor: Flash Commands PmPPC7448 User’s Manual 10006757-02 11-14 00080070: ffffffff ffffffff ffffffff ff ffffff ................ FLASH COMMANDS The Flash commands affect the StrataFlash devic es on the PmPPC7448 circui t board. There is one Flash ba nk on the PmPPC7 448 board.
Monitor: EEPROM/I2C Commands 10006757-02 P mPPC7448 User’s Manual 11-15 protect The protect com m and enables or disables the Flash se ctor protection for the specified Flash sector. Protection is implemented using soft ware only. The protec tion mechanism inside the physical Flash part i s not being used.
Monitor: EEPROM/I2C Commands PmPPC7448 User’s Manual 10006757-02 11-16 eeprom read devaddr addr off cnt eeprom write devaddr addr off cnt icrc32 The icrc32 computes a CRC32 checksum. DEFINITION: icrc32 chip a ddress[.0, .1, .2] count iloop The iloop command reads in an i nfinite loop on the specified address range.
Monitor: Environment Parameter Commands 10006757-02 P mPPC7448 User’s Manual 11-17 ENVIRONMENT PARAMETER COMMANDS The monitor uses on-boa rd, non-volatile memo ry for the storage of environment parame- ters. Environment parameters are stored as ASCII strings with the following format.
Monitor: Other Commands PmPPC7448 User’s Manual 10006757-02 11-18 diags The diags command runs th e Power-On Self-Test (POST). DEFINITION: diags mtest The mtest command perf orms a simp le SDRAM read/write test. DEFINITION: mtest [start [end [pattern]]] um The um command is a destructive memory test.
Monitor: Other Commands 10006757-02 P mPPC7448 User’s Manual 11-19 DEFINITION: coninfo crc32 The crc32 command computes a CRC32 checksum on count bytes starting at addre ss . DEFINITION: crc32 address count date The date command will set or get the dat e and time, and reset the real-time clock (RTC) device.
Monitor: Other Commands PmPPC7448 User’s Manual 10006757-02 11-20 help The help (or ? ) command displays the online help. Wi thout arguments, al l commands are displayed wi th a short usage m essage for each. To obtain mo re detailed i nformation fo r a specific command, enter the de sired command as an ar gument.
Monitor: Other Commands 10006757-02 P mPPC7448 User’s Manual 11-21 moninit <serial#> <src_address> pci The pci command enumerates the PCI bus i f the Pm PPC7448 is the Monarch boa rd. It dis- plays enumeration information about each detected device.
Monitor: Environment Variables PmPPC7448 User’s Manual 10006757-02 11-22 script The script command runs a list of moni tor commands out of memory. The list is an ASCII string of commands separated by the ; character and terminated with the ;; chara c- ters.
Monitor: Environment Variables 10006757-02 P mPPC7448 User’s Manual 11-23 bootfile " " Path to boot file on serv er (used with TFTP)—set thi s to the “path/file.
Monitor: Environment Variables PmPPC7448 User’s Manual 10006757-02 11-24 The monitor supports optional environment v ari ables that e nable addition al functionalit y. The moninit command ( see “moninit” on pa ge 11-20) only affe cts the standard environ- ment variables and does not set any paramet ers for these optional variables.
Monitor: Troubleshooting 10006757-02 P mPPC7448 User’s Manual 11-25 1. The monin it command d oes not initial ize these variab les. Each paramet er is only define d if a change from the default se tting is desi red and is not defined after initializat ion of the configu ration variable s.
PmPPC7448 User’s Manual 10006757-02 11-26 (blank page ).
10006757-02 P mPPC7448 User’s Manual 12-1 Section 12 Acronyms ASCII American Standard Code for Information Interchang e CPLD Complex Programmable Logic Device CPM Communication Processor Module cPSB.
Acronyms: PmPPC7448 User’s Manual 10006757-02 12-2 RMA Return Merchandise Authorizat ion RTC Real-time Clock SDRAM Synchronous Dynamic Random Access Memory SO-DIMM Small-outl ine Dual In-line Memo r.
10006757-02 P mPPC7448 User’s Manual i-3 Index A acronyms . . . . . . . . . . . . . . . . . . . 12-1 address map, PCIO examples . . . . . 5-6 air flow rate . . . . . . . . . . . . . . . . . . . 2-9 B baud rate generator (BRG) registers 8-1 binary download format .
Index (continued) PmPPC7448 User’s Manual 10006757-02 i-4 environment parameter commands 11-17 environment variables . . . . . .11-22 Flash commands . . . . . . . . . . .11-14 Flash programming . . . . . . . . . 11-1 memory commands . . . . . . . .11-11 Motorola S-record .
Index (continued) 10006757-02 P mPPC7448 User’s Manual i-5 SDRAM controller . . . . . . . . . . . . 5-2 SROM . . . . . . . . . . . . . . . . . . . . . 4-2 timer/counters . . . . . . . . . . . . . . 5-4 two-wire se rial interfa ce (TWSI) .8 - 2 T table of contents .
PmPPC7448 User’s Manual 10006757-02 i-6 (blank page ).
10006757-02 P mPPC7448 User’s Manual Notes ____________ __________ _____________ _____________ __________ ____________ ___________ ___________ ____________ __________ _____________ _____________ ___.
Emerson Netwo rk Power, Embedded Co mputing 8310 Excelsior Drive ■ Madison, WI 53717-1935 USA US Toll Free: 1-800-356-9602 ■ Voice: +1-608-831-5500 ■ FAX: 1-608-831-4249 Email: info@ar tesyncp.
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