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Document Number: DSP56366UM Rev. 4 08/2006 DSP56366 24-Bit Digital Signal Pr ocessor User Manual.
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DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor TOC-1 1 DSP56366 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 TOC-2 Freescale Semiconductor 3.1 Data and Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 Reserved Memory Spaces . . . . . .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor TOC-3 6.5.1 Host Receive Data Register (HORX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.5.2 Host Transmit Data Register (HOTX) . .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 TOC-4 Freescale Semiconductor 6.6.1.4 ICR Host Flag 0 (HF0) Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 6.6.1.5 ICR Host Flag 1 (HF1) Bit 4 . . .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor TOC-5 7.4.6.2 HCSR I 2 C/SPI Selection (HI2C)—Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.4.6.3 HCSR Serial Host Interface Mode (HM[1:0])—Bits 3–2 .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 TOC-6 Freescale Semiconductor 8.2.10 Frame Sync for Transmitter (FST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 -7 8.2.11 High Frequency Clock for Transmitter (HCKT) .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor TOC-7 8.3.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23 . . . . . . . . . . . . 8-26 8.3.4 ESAI Receive Control Register (RCR) . . . . . . . . . . . . . . .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 TOC-8 Freescale Semiconductor 8.3.11 ESAI Time Slot Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40 8.3.12 Transmit Slot Mask Registers (TSMA, TSMB) .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor TOC-9 9.3.4.3 RCCR_1 Rx High Freq. Clock Direction (RHCKD) - Bi t 23 . . . . . . . . . . . . . . . . . . . . 9-9 9.3.5 ESAI_1 Receive Control Register (RCR_1) . . . . . . . . .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 TOC-10 Freescale Semiconductor 10.5.7.2 DAX Transmit Underrun Error Flag (XAUR)—Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.5.7.3 DAX Block Transfer Flag (XBLK)—Bit 2 . . . . .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor TOC-11 11.3.4.12 TCSR Timer Compare Flag (TCF) Bit 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.3.4.13 TCSR Reserved Bits (Bits 3, 10, 14, 16-19, 22, 23) .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 TOC-12 Freescale Semiconductor B.4 Interrupt Source Priorities (within an IPL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B -10 B.5 Host Interface—Quick Reference .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor LOF-1 Figure 1-1 DSP56366 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Figure 2-1 Signals Identified by Functional Group .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 LOF-2 Freescale Semiconductor Figure 7-4 SHI Programming Mode l—DSP Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Figure 7-5 SHI I/O Shift Register (IOSR) . . .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor LOF-3 Figure 9-11 TSMA_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 Figure 9-12 TSMB_1 Register . . .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 LOF-4 Freescale Semiconductor Figure D-20 ESAI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-35 Figure D-21 ESAI_1 Multiplex Control Register .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor LOT-1 Table 2-1 DSP56364 Functional Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Table 2-2 Power Inputs . . . . . . . . . . . . .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 LOT-2 Freescale Semiconductor Table 6-12 Host Mode Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Table 6-13 INIT Command Effect . . . .
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor i Preface This manual describes the DSP56366 24-bit digital sign al processor (DSP), its memory , operating modes, and peripheral modules. The DSP56366 is a member of the DSP56300 family of programmable CMOS DSPs.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 ii F reescale Semico nductor SECTION 6— HOST INTERFACE (HDI08) • Describes the HDI08 pa rallel host interface.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor iii • The word “assert” means that a high true (active high) signal is pulled high to V CC or that a low true (active low) signal is pulled low to ground.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 iv F reescale Semico nductor NO TES.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 1-1 1 DSP56366 Over view 1.1 Intr oduction This manual describes the DSP56366 24-bit digital sign al processor (DSP), its memory , operating modes, and peripheral modules.
DSP56300 Core Description DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 1-2 F reescale Semico nductor 1.2 DSP56300 Core Description The DSP56366 uses the DSP56300 core, a high-performa.
DSP56366 Audio Processor Arc hitecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 1-3 — Off-chip expansion up to two 16M × 24-bit word of Data memory . — Off-chip expansion up to 16M × 24-bit word of Program memory .
DSP56300 Core Functional Blocks DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 1-4 F reescale Semico nductor • Instruction cache controller • PLL-based clock oscillator • OnCE module • JT AG T AP • Memory In addition, the DSP56366 provides a set of on-chip peripherals, described in Section 1.
DSP56300 Core Functional Blocks DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 1-5 the A or B accumulator . A 56-bit resu lt can be stored as a 24-bit operand. The LSP can either be truncated or rounded into the MSP .
DSP56300 Core Functional Blocks DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 1-6 F reescale Semico nductor • Nested hardware DO loops • Fast auto-return interrupts The PCU impleme.
DSP56300 Core Functional Blocks DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 1-7 • End-of-block-transfer interrupts • T riggering from interrupt lines and all peripherals 1.
P eripher al Overvi ew DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 1-8 F reescale Semico nductor ALU. Memory space includes internal RAM and ROM and can be expanded of f-chip under software control. There is an instruction cache, made using program RA M.
P eripheral Overview DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 1-9 1.5.1 Host Interface (HDI08) The host interface (HDI08) is a byt e-wide, full-duplex, double-buf fered, pa rallel port that can be connected directly to the data bus of a host processor .
P eripher al Overvi ew DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 1-10 F reescale Semico nductor 1.5.4 Enhanced Serial A udio Interface (ESAI) The ESAI provides a full-duplex serial.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-1 2 Signal/Connection Descriptions 2.1 S ignal Gr oupings The input and output signals of th e DSP56364 are organized into functi onal groups, which are listed in Ta b l e 2 - 1 and illustrated in Figure 2-1 .
Signal Groupings DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-2 F reescale Semico nductor Figure 2-1 Signals Identified b y Functional Group PORT A ADDRESS BUS A0-A17 VCCA (3) GNDA .
Pow e r DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-3 2.2 P ower 2.3 Gr ound T able 2-2 P ower Inputs P ower Name Description V CCP PLL P ower — V CCP is V CC de dicated for PLL use.
Cloc k and PLL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-4 F reescale Semico nductor 2.4 Clock and PLL GND A (4) Address Bus Ground — GND A is an isolated ground f or sections of the addre ss bus I/O drivers . This connection must be tied e xter nally to all other chip ground connecti ons.
External Memory Expansion P ort (Port A) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-5 2.5 E xternal Memory Expansion P o r t (P or t A) When the DSP56364 .
External Memory Expansion P ort (P ort A) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-6 F reescale Semico nductor WR Output T r i-stated Write Enable — When the DSP is the bus master , WR is an active-low output that is asser ted to wr ite external memor y on the data bus (D0-D23).
Interrupt and Mode Cont rol DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-7 2.6 Interrupt and Mode Control The interrupt and mode control signals select the chip’ s operating m ode as it comes out of hardware reset.
Interrupt and Mode Control DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-8 F reescale Semico nductor T ab le 2-8 Interrupt and Mode Control Signal Name T ype State during Reset Signa.
P ARALLEL HOST INTERF A CE (HDI08) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-9 2.7 P ARALLEL HOST INTERF A CE (HDI08) The HDI08 provides a fast, 8-bit, para llel data port that may be connect ed directly to the host bus.
P ARALLEL HOST INTERF A CE (HDI08) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-10 F reescale Semico nductor HA2 Input GPIO disconnected Host Address Input 2 — When the HDI08 is programmed to interface a non-multiple xed host bus and the HI func tion is selected, this si gnal is line 2 of the host address (HA2) input bus.
P ARALLEL HOST INTERF A CE (HDI08) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-11 HCS Input GPIO disconnected Host Chip Select — When HD I08 is programmed to interface a nonmultiplex ed host bus and the HI function is selecte d, this signal is th e host chip select (HCS) input.
Serial Host Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-12 F reescale Semico nductor 2.8 S erial Host Interface The SHI has five I/O signals that can be configured to allow the SH I to operate in eith er SPI or I 2 C mode.
Serial Host Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-13 MISO Input or output T r i-stated SPI Master-In-Sla ve-Out — When the SPI is configur ed as a master , MISO is the master data input line.
Serial Host Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-14 F reescale Semico nductor SS Input T ri-stated SPI Slave Select — This signal is an activ e low Schmitt-trigger input when configured for the SPI mode . When conf igured for the SPI Sla ve mode , this signal is used to enable the SPI slave f or transf er .
Enhanced Serial Au d i o I n t e rf a c e DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-15 2.9 E nhanced Serial A udio Interface T ab le 2-11 Enhanced Serial.
Enhanced Serial A udio Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-16 F reescale Semico nductor FST Input or output GPIO disconnected Frame Sync for T ransmitter — This is the transmitter frame sync input/output signal.
Enhanced Serial Au d i o I n t e rf a c e DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-17 SDO5 Output GPIO disconnected Serial Data Output 5 — When progr ammed as a transmitter , SDO5 is used to transmit data from the TX 5 serial tr ansmit shift register .
Enhanced Serial A udio Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-18 F reescale Semico nductor SDO2/ SDO2_1 Output GPIO disconnected Serial Data Output 2 — When progr .
Enhanced Serial Audio Interface_1 DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-19 2.10 Enhanced Serial A udio Interface_1 T able 2-12 Enhanced Serial A udio.
Enhanced Serial A udio Interface_1 DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-20 F reescale Semico nductor SCKR_1 Input or output GPIO disconnected Receiver Serial Clock_1 — SCKR provides the receiv er serial bit clock f or the ESAI.
SPDIF T ransmitter Digi tal A udio Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 2-21 2.11 SPDIF T ransmitter Digital A udio Interface SDO4_1 Output .
Timer DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 2-22 F reescale Semico nductor 2.12 Timer 2.13 JT A G/OnCE Interface T a ble 2-14 Timer Signal Signal Name Ty p e State during Reset.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-1 3 Memory Configuration 3.1 Data and Program Memory Maps The on-chip memory configuration of the DSP56366 is a.
Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-2 F reescale Semico nductor T ab le 3-2 On-chip RAM Memory Locations Bit Settings RAM Me mory Locations MSW1 MSW0 CE MS SC Prog. RAM Prog. Cache X Data RAM Y Data RAM X X 0 0 X $0000 - $0BFF n.
Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-3 Figure 3-1 Memor y Maps for MSW=(X,X), CE=0, MS=0, SC=0 Figure 3-2 Memor y Maps .
Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-4 F reescale Semico nductor Figure 3-3 Memory Maps f or MSW=(0,0), CE=0 MS=1, SC=0 Figure 3-4 Memory Maps f.
Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-5 Figure 3-5 Memory Maps f or MSW=(1,0), CE=0, MS=1, SC=0 Figure 3-6 Memory Maps f.
Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-6 F reescale Semico nductor Figure 3-7 Memory Maps f or MSW=(0,1), CE=1, MS=1, SC=0 Figure 3-8 Memory Maps .
Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-7 Figure 3-9 Memor y Maps for MSW=(X,X), CE=0, MS=0, SC=1 Figure 3-10 Memory Maps .
Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-8 F reescale Semico nductor Figure 3-11 Memory Maps f or MSW=(0,0), CE=0, MS=1, SC=1 Figure 3-12 Memory Map.
Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-9 Figure 3-13 Memory Maps f or MSW=(1,0), CE=0, MS=1, SC=1 Figure 3-14 Memory Maps.
Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-10 F reescale Semico nductor Figure 3-15 Memory Maps f or MSW=(0,1), CE=1, MS=1, SC=1 Figure 3-16 Memory Ma.
Data and Program Memory Maps DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-11 3.1.1 Reserved Memory Spaces The reserved memory spaces should not be accessed by the user . They are reserved for future expansion.
Internal I/O Memory Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-12 F reescale Semico nductor while the DSP is in Debug mode. As a result, subseque nt instructions might be fetched according to the new memory configuration (after the swit ch), and thus might execute improperly .
Internal I/O Memor y Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-13 DMA1 X:$FFFFEB DMA SOURCE ADDRESS REGISTER (DSR1) X:$FFFFEA DMA DESTINA TION ADDRES.
Internal I/O Memory Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-14 F reescale Semico nductor HDI08 X:$FFFFC7 HOST TRANSMIT REGISTER (HO TX) X:$FFFFC6 HOST RECEIVE RE GISTER (HO.
Internal I/O Memor y Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-15 ESAI X:$FFFFBC ESAI RECEIVE SL O T MASK REGISTER B (RSMB) X:$FFFFBB ESAI RECEIVE SL.
Internal I/O Memory Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-16 F reescale Semico nductor X:$FFFF97 Reser ved X:$FFFF96 Reser ved X:$FFFF95 Reser ved SHI X:$FFFF94 SHI RECEI.
Internal I/O Memor y Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 3-17 Y :$FFFF A C Reser ved Y: $ F F F FA B Reser ved Y: $ F F F FA A Reser ved Y: $ F F.
Internal I/O Memory Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 3-18 F reescale Semico nductor ESAI_1 Y :$FFFF9C ESAI_1 RECEIVE SLO T MASK REGISTER B (RSMB_1) Y :$FFFF9B ESAI_1 R.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-1 4 Core Configuration 4.1 Intr oduction This chapter contains DSP56300 core configuration information deta ils specific to the DSP56366.
Operating Mode Regist er (OMR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-2 F reescale Semico nductor 4.2.1 Asynchr onous Bus Arbitr ation Enable (ABE) - Bit 13 The asynchronous bus arbitration mode is activated by setting the ABE b it in the OMR register .
Operating Mode Register (OMR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-3 The Instruction Cache should be initialized with the new instructions according to the following procedure: These steps should be executed from external memory or by downl oad via host interface: 1.
Operating Mod es DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-4 F reescale Semico nductor ; do #(PATCH_DATA_END-PATCH_DATA_START+1),PATCH_LOOP movem p:(r1)+,x0 movem x0,p:(r2)+ nop .
Operating Modes DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-5 6 0110 $ F F 0 0 0 0 B o o t s t r a p f r o m S H I ( s l a v e I 2 C mode) (HCKFR=1, 100ns .
Interrupt Priori ty Registers DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-6 F reescale Semico nductor 4.4 Interrupt Priority Registers There are two interrupt priority registers in the DSP56366: 1. IPR-C is dedicated for DSP56300 Core interrupt sources.
Interrupt Priori ty Register s DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-7 Figure 4-1 Interrupt Priority Regi ster P Figure 4-2 Interrupt Prior ity Regis.
Interrupt Priori ty Registers DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-8 F reescale Semico nductor T ab le 4-5 Interrupt Sour c es Priorit ies Within an IPL Priority Interrupt S.
Interrupt Priori ty Register s DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-9 SHI Receive FIFO Full SHI T ransmit Data SHI Receive F IFO Not Empty HOST Comm.
Interrupt Priori ty Registers DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-10 F reescale Semico nductor T ab le 4-6 DSP56366 Inte rrupt V ectors Interrupt Starting Address Interrupt.
Interrupt Priori ty Register s DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-11 VBA:$44 0 - 2 SHI Receive FIFO Not Empty VBA:$46 0 - 2 Reserved VBA:$48 0 - 2.
DMA Request Sources DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-12 F reescale Semico nductor 4.5 DMA Request Sources The DMA Request Source bits (DRS0-DR S4 bits in the DMA Control/S tatus registers) encode the source of DMA requests used to trigger the DMA transfer s.
PLL Initialization DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-13 4.6 P LL Initialization 4.6.1 PLL Multiplication F actor (MF0-MF11) The DSP56366 PLL multiplication factor is set to 6 during hardware re set, i.
JT A G Boundary Scan Register (BSR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-14 F reescale Semico nductor 4.9 JT A G Boundary Scan Register (BSR) The boundary scan register (BSR) in the DSP56366 JT AG implementation contains bits for all device signal and clock pins and asso ciated control signals.
JT A G Boundary Sc an Register (BSR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-15 17 D13 Input/Output Data 93 HAD6 — Control 18 D12 Input/Output Data 9.
JT A G Boundary Scan Register (BSR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-16 F reescale Semico nductor 43 A7 Output3 Data 119 HSCKR — Control 44 A6 Output3 Data 120 HSCKR I.
JT A G Boundary Sc an Register (BSR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 4-17 69 EXT AL Input Data 145 SS I nput Data 70 SCKT_1 — Control 146 SCK/S.
JT A G Boundary Scan Register (BSR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 4-18 F reescale Semico nductor NO TES.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 5-1 5 General Purpose Input/Output 5.1 Intr oduction The DSP56362 provides up to 37 bidirectional signals that can be confi gured as GPIO signals or as peripheral dedicated signals.
Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 5-2 F reescale Semico nductor 5.2.4 P or t E Signals and Registers Port E has 10 signals, shared with the ESAI_1. Six of the ESAI_1 signals have their own pin, so each of the six signals, if not used as an ESAI_1 signal, can be configured indi vidually as a GPIO signal.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-1 6 Host Interface (HDI08) 6.1 Intr oduction The host interface (HDI08) is a byt e-wide, full-duplex, double-buf fered, pa rallel port that can be connected directly to the data bus of a host processor .
HDI08 Features DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-2 F reescale Semico nductor — Bit addressing instructions (e.g. BCHG , BCLR, BSET , BTST , JCLR, JSCLR, JSET , JSSET) simplify I/O service routines.
HDI08 Host Port Signals DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-3 — Cycle-stealing DMA with initialization • Dedicated Interrupts: — Separate int.
HDI08 Block Diagram DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-4 F reescale Semico nductor 6.4 HDI08 Block Diag ram Figure 6-1 shows the HDI08 registers. The top row of registers (HCR, HSR, HDDR, HDR, HBAR, HPCR, HOTX, HORX) can be accessed the DSP core.
HDI08 – DSP-Side Pr ogrammer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-5 Figure 6-1 HDI08 Bl ock Dia gram 6.5 HDI08 – DSP-Side Programmer’ s Model The DSP core threats the HDI08 as a memory-mapped peripheral occupyi ng eight 24-bit words in X data memory space.
HDI08 – DSP-Side Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-6 F reescale Semico nductor The eight host processor registers cons ists of two data re gist ers and six control regist ers. All registers can be accessed by the DSP core but not by the external processor .
HDI08 – DSP-Side Pr ogrammer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-7 NO TE When writing data to a pe ripheral device, there is a two-cycle pipeline delay until any status bits affected by th e operation are updated.
HDI08 – DSP-Side Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-8 F reescale Semico nductor 6.5.3.4 HCR Host Flags 2,3 (HF2,HF3) Bits 3-4 HF2 and HF3 bits are used as a general-purpose flags for DSP to host communicati on.
HDI08 – DSP-Side Pr ogrammer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-9 If HDM1 or HDM0 are set, the DMA mode is enabled, and the HOREQ signal is used to request DMA transfers (the value of the HM1, HM0, HLEND and HDREQ bi ts in the ICR have no affect).
HDI08 – DSP-Side Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-10 F reescale Semico nductor for the DMA controller to supply the HA2, HA1, and HA 0 signals. For 16- or 24-bit data transfers, the DSP CPU interrupt rate is reduced by a factor of 2 or 3, resp ectively , from the host request rate – i.
HDI08 – DSP-Side Pr ogrammer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-11 by the HDI08 hardware when the interrupt request is serviced by the DSP core. The host can clear HC, which also clears HCP .
HDI08 – DSP-Side Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-12 F reescale Semico nductor 6.5.5.2 HB AR Reserved Bits 8-15 These bits are reserved. They read as zero and shou ld be written with zero for future compatibility .
HDI08 – DSP-Side Pr ogrammer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-13 6.5.6.2 HPCR Host Address Line 8 Enable (HA8EN) Bit 1 If the HA8EN bit is set and the HDI08 is used in multiplexed bus mode, then HA8/HA1 is used as host address line 8 (HA8).
HDI08 – DSP-Side Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-14 F reescale Semico nductor 6.5.6.9 HPCR Host Request Open Drain (HROD) Bit 8 The HROD bit controls the output drive of the hos t request signals.
HDI08 – DSP-Side Pr ogrammer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-15 Figure 6-8 Dual str obes bus 6.
HDI08 – DSP-Side Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-16 F reescale Semico nductor 6.5.8 Host Data Register (HDR) The HDR register holds the data va lue of the corresponding bits of the HDI08 pins which are configured as GPIO pins.
HDI08 – DSP-Side Pr ogrammer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-17 6.5.10 Host Interface DSP Core Interrupts The HDI08 may request interrupt service from either the DSP core or the host processor .
HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-18 F reescale Semico nductor Figure 6-11 HSR-HCR Ope ration 6.6 HDI08 – External Host Programmer’ s Model The HDI08 has been designed to provide a simple, hi gh speed interface to a host processor .
HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-19 One of the most innovative features of the host interfac e is the host command feature. W ith this feature, the host processor can issue vectored interrupt reque sts to the DSP core.
HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-20 F reescale Semico nductor 6.6.1.1 ICR Receive Request Enable (RREQ) Bit 0 In interrupt .
HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-21 6.6.1.3 ICR Double Host Request (HDRQ) Bit 2 The HDRQ bit determines the functions of the HOREQ/HTRQ and HACK/HRRQ signals as shown in T a ble 6-1 1 .
HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-22 F reescale Semico nductor 6.6.1.6 ICR Host Little Endian (HLEND) Bit 5 If the HLEND bit is cleared, the HDI08 can be accessed by the host in big endian byte order .
HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-23 from the host request rate – i.e., for every two or thre e host processor data transfers of one byte each, there is only one 24-bit DSP CPU interrupt.
HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-24 F reescale Semico nductor The host processor can select the starting address of a ny of the 128 possible interr upt routines in the DSP by writing the interrupt routine address divided by 2 in to the HV bits.
HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-25 written by the host processor . TXDE can be set by the host processor using the initialize feature. TXDE may be used to assert the external HOREQ signal if the TREQ bit is set.
HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-26 F reescale Semico nductor 6.6.4 Interrupt V ector Register (IVR) The IVR is an 8-bit read/write register which typically contains the interrupt vector number used with MC68000 Family processor vectored interrupts.
HDI08 – External Host Programmer’ s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-27 6.6.7 Host Side Register s After Reset T a ble 6-15 shows the result of the four kinds of reset on bits in each of the HDI08 registers seen by the host processor .
Servicing The Host Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-28 F reescale Semico nductor 6.7 S ervicing The Host Interface The HDI08 can be serviced by using one of the following protocols: • Polling • Interrupts 6.
Servicing The Host Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 6-29 Figure 6-16 HDI08 Host Request Structur e 6.
Servicing The Host Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 6-30 F reescale Semico nductor.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-1 7 Serial Host Interface 7.1 Intr oduction The Serial Host Interface (SHI) is a serial I/O interface that provides a path for commu nication and program/coefficient data transfers between the DSP and an external host processor .
Serial Host Interface Internal Arch itecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-2 F reescale Semico nductor 7.2 S erial Host Interface Internal Ar chitecture The DSP views the SHI as a memory-mapped peripheral in the X data memory space.
Serial Host Interfa ce Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-3 user ’ s responsibility to select the proper clock rate within the range as defined in the I 2 C and SPI bus specifications.
Serial Host Interface Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-4 F reescale Semico nductor Figure 7-4 SHI Programming Mod el—DSP Side HCKFR 8 15 14 13 12 11 .
Serial Host Interfa ce Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-5 The SHI interrupt vector table is shown in Ta b l e 7 - 1 and the exception prioritie s generated by the SHI are shown in Ta b l e 7 - 2 .
Serial Host Interface Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-6 F reescale Semico nductor Figure 7-5 SHI I /O Shift Register ( IOSR) 7.4.2 SHI Host T ransmit Da ta Register (H TX)—DSP Side The host transmit data register (HTX) is used for DSP- to-Host data transfers.
Serial Host Interfa ce Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-7 7.4.4.1 HSAR Reserved Bits—Bits 19, 17–0 These bits are reserved. They read as zero and shou ld be written with zero for future compatibility .
Serial Host Interface Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-8 F reescale Semico nductor Figure 7-6 SPI Data-T o-Clock T iming Diagram If CPOL is cleared, it pr oduces a steady-state low valu e at the SCK pin of the ma ster device whenever data is not being transferred.
Serial Host Interfa ce Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-9 When the SHI is in master mode and CPHA = 1, the DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE.
Serial Host Interface Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-10 F reescale Semico nductor When HFM[1:0] = 00, the filter is bypassed (spikes are not filtered out). This mode is useful when higher bit-rate transfers are required and the SHI operates in a noise-free environment.
Serial Host Interfa ce Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-11 7.4.6.1.1 SHI Individual Reset While the SHI is in the individual r.
Serial Host Interface Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-12 F reescale Semico nductor It is recommended that an SHI individual reset be generated (HEN cleared) before changing HCKFR. HCKFR is cleared during hardwa re reset and software reset.
Serial Host Interfa ce Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-13 7.4.6.8 HCSR Idle (HIDLE)—Bit 9 The read/write control/status bi t HIDLE is used only in the I 2 C master mode; it is i gnored otherwise.
Serial Host Interface Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-14 F reescale Semico nductor transmit-underrun-error interrupt serv ice from the interrupt controller . HTIE is cleared by hardware reset and software reset.
Serial Host Interfa ce Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-15 If a transmit interrupt occurs with HTUE set, the transmit-underrun interrupt v ector is generated. If a transmit interrupt occurs with HTUE cleared, the re gular transmit-data interrupt vector is generated.
Characteristics Of The SPI Bus DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-16 F reescale Semico nductor 7.4.6.18 Host Bus Error (HBER)—Bit 21 The read-only status bit HBER indicates, when set, that an SHI bus error occurred when operating as a master (HMST set).
Characteristics Of The I 2 C Bus DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-17 7.6.1 Overview The I 2 C bus protocol must conform to the following rules: • Data transfer may be initiate d only when the bus is not busy .
Characteristics Of The I 2 C Bus DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-18 F reescale Semico nductor Figure 7-9 Ac knowledgmen t on the I 2 C Bus A device generating a signal is called a transmitter , and a device receiv ing a signal is called a receiver .
SHI Prog ramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-19 Figure 7-11 I 2 C Bus Pr otocol For Host Read Cyc le NO TE The first data byte in a write-bus cycl e can be used as a user -predefined control byte (e.
SHI Pr ogramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-20 F reescale Semico nductor If a write to HTX occurs, its contents are transferred to IOSR between da ta word transfers. The IOSR data is shifted out (via MISO) and received data is shifte d in (via MOSI).
SHI Prog ramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-21 It is recommended that an SHI individual reset (H EN cleared) be generated before beginning data reception in order to reset the receive FIFO to its initial (empty) state (e.
SHI Pr ogramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-22 F reescale Semico nductor In a receive session, only the receive path is enabled and HTX to IOSR transfers are inhibited.
SHI Prog ramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-23 may be used to inte rrupt the external I 2 C master device.
SHI Pr ogramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-24 F reescale Semico nductor the HREQ line between two SHI-equippe d DSPs, one opera ting as an I 2 C master device and the other as an I 2 C slave device, enables full hardware handshaking.
SHI Prog ramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 7-25 7.7.5 SHI Operation During DSP Stop The SHI operation cannot continue when the DSP is in the stop state, because no DSP clocks are active.
SHI Pr ogramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 7-26 F reescale Semico nductor NO TES.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-1 8 Enhanced Serial A UDIO Interface (ESAI) 8.1 Intr oduction The Enhanced Serial Audio Interfac e (ESAI) provi.
Introd uction DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-2 F reescale Semico nductor Figure 8-1 ESAI Block Diagram SDO1 [PC10] SDO0 [PC11] Shift Register RX0 TX5 SDO5/SDI0 [PC6] S.
ESAI Data and Contr ol Pins DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-3 8.2 E SAI Data and Contr ol Pins Three to twelve pins are require d for operation, depending on the opera ting mode selected and the number of transmitters and receivers enable d.
ESAI Data and Control Pins DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-4 F reescale Semico nductor 8.2.4 Serial T ransmit 3/Receive 2 Data Pin (SDO3/SDI2) SDO3/SDI2 is used as the .
ESAI Data and Contr ol Pins DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-5 When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register .
ESAI Data and Control Pins DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-6 F reescale Semico nductor SCKT may be programmed as a general-purpose I/O pi n (PC3) when the ESAI SC KT function is not being used.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-7 8.2.10 Frame Sync f or T ransmitter (FST) FST is a bidirectional pin providing the fra.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-8 F reescale Semico nductor special-purpose time slot register . The following paragraphs give detail ed descriptions and operations of each bit in the ESAI registers.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-9 Figure 8-3 ESAI Cloc k Generator Functiona l Block Diagram 8.3.1.2 TCCR T ransmit Prescaler Rang e (TPSR) - Bit 8 The TPSR bit controls a fixed divide -by-eight prescaler in series with the variable prescaler .
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-10 F reescale Semico nductor operational (see Figure 8-3 ). The maximum internally generated bit clock frequency is Fosc/4; the minimum internally generated bit clock frequency is Fosc/(2 x 8 x 256)=Fosc/4096.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-11 Figure 8-4 ESAI Frame Sync Gener ator Functional Bloc k Diagram 8.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-12 F reescale Semico nductor 8.3.1.5 TCCR T ransmit Clock P olarity (TCKP) - Bit 18 The T ransmitter Clock Polarity (TCK P) bit controls on which bit cloc k edge data and frame sync are clocked out and latched in.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-13 . Hardware and software reset clear all the bits in the TCR register .
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-14 F reescale Semico nductor 8.3.2.3 TCR ESAI T ransmit 2 Enable (TE2) - Bit 2 TE2 enables the transfer of data from TX2 to the tr ansmit shift register #2.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-15 The SDO4/SDI1 pin is the data input pin for RX1 if TE4 is cl eared and RE1 in the RCR register is set. If both RE1 and TE4 are cleared the trans mitter and receiver are disabled, and the pin is tri- stated.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-16 F reescale Semico nductor 2. If the data word is right-aligne d (TW A=1), and zero padding is disabled (P ADC=0), then the first data bit is repeated before the transmission of the data word.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-17 Figure 8-6 Normal and Netw ork Operation Normal Mode SERIAL CLOCK FRAME SYNC SERIAL D.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-18 F reescale Semico nductor 8.3.2.10 TCR Tx Slot and W or d Length Select (TSWS4-TSWS0) - Bits 10-14 The TSWS4-TSWS0 bits are used to select the length of the slot and the length of the data words being transferred via the ESAI.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-19 8.3.2.11 TCR T ransmit Frame Sy nc Length (TFSL) - Bit 15 The TFSL bit selects the length of frame sync to be generated or recognized. If TFSL is cleared, a word-length frame sync is selected.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-20 F reescale Semico nductor Figure 8-7 Frame Length Selection DA T A DA T A SERIAL CLOC K RX, TX FRAME SYNC WORD LENGTH: TFSL=0, RFSL=0 RX, TX SERIAL D A T A NO TE: F rame sync occurs while data is v alid.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-21 8.3.2.12 TCR T ransmit Frame Sync Relative Timing (TFSR) - Bit 16 TFSR determines the relative timing of the tr ansmit frame sync signal as referred to the serial data lines, for a word length frame sync only (TFSL=0).
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-22 F reescale Semico nductor 8.3.2.17 TCR T ransmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21 The TEDIE control bit is used to enable the transmit even slot data in terr upts.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-23 Hardware and software reset clear all the bits of the RCCR register .
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-24 F reescale Semico nductor 8.3.3.5 RCCR Receiver Cloc k P olarity (RCKP) - Bit 18 The Receiver Clock Polarity (RCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-25 In the synchronous mode when RCKD is set, the SCKR pin becomes the OF0 out put flag. If RCKD is cleared, then the SCKR pin becomes the IF0 input flag.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-26 F reescale Semico nductor 8.3.3.10 RCC R Receiver High Frequency Clock Direction (RHCKD) - Bit 23 The Receiver.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-27 8.3.4.1 RCR ESAI Receiver 0 Enable (RE0) - Bit 0 When RE0 is set and TE5 is cleared, the ESAI receiv er 0 is enabled and samples data at the SDO5/SDI0 pin.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-28 F reescale Semico nductor 8.3.4.7 RCR Receiver W or d Al ignment Control (R W A) - Bit 7 The Receiver W ord Alignment Control (R W A) bit defines the alignment of the data word in relation to the slot.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-29 T a ble 8-11 ESAI Receive Slot and W ord Lengt h Selection RSWS4 RSWS3 RSWS2 RSWS1 RS.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-30 F reescale Semico nductor 8.3.4.10 RCR Receiver Frame Sync Length (RFSL) - Bit 15 The RFSL bit selects the lengt h of the receive frame sync to be generated or recogn ized.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-31 8.3.4.13 RCR Receive Exception Inte rrupt Enable (REIE) - Bit 20 When REIE is set, the DSP is interrupted when both RDF and ROE in the SAISR status register are set.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-32 F reescale Semico nductor Hardware and software re set clear all the bits in the SAICR regis ter . 8.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0 The Serial Output Flag 0 (OF0) is a data bit used to hold data to be send to the OF0 pin.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-33 the transmit and receive s ections. When SYN is set, the synchronous mode is chosen an d the transmit and receive sections use common cl ock and frame sync signals.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-34 F reescale Semico nductor Figure 8-11 SAICR SYN Bit Op eration 8.3.6 ESAI Status Register (SAISR) The S tatus Register (SAISR) is a read-only status regi ster used by the DSP to read the status and serial input flags of the ESAI.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-35 8.3.6.1 SAISR Serial Input Flag 0 (IF0) - Bit 0 The IF0 bit is enabled only when the .
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-36 F reescale Semico nductor a word is received, it indicates (only in the netw ork mode) that the frame sync did not occur during reception of that word. RFS is cleare d by hardware, software, ESAI individua l, or ST OP reset.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-37 during the second time slot in the frame. TFS is useful in network mode to identify the start of a frame. TFS is cleared by hardware, software , ESAI individual, or ST OP reset.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-38 F reescale Semico nductor TSR disabled time slot period in network mode (as if data were be ing transmitted after the TSR was written).
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-39 Figure 8-14 ESAI Data P ath Pr ogramming Model ([R/T]SHFD=1) SDI 23 16 15 87 0 7 0 70.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-40 F reescale Semico nductor 8.3.7 ESAI Receive Shift Register s The receive shift registers (see Figure 8-13 and Figure 8-14 ) receive the incoming data from the serial receive data pins.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-41 transmitter empty condition (TDE=1), or to tri-stat e the transmitter data pi ns. TSMA and TSMB should each be considered as containing half a 32-bit register TSM.
ESAI Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-42 F reescale Semico nductor NO TE When operating in normal mode, bit 0 of the mask register must be set, otherwise no output is generated.
Operating Modes DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-43 NO TE When operating in normal mode, bit 0 of the mask register must be set to one, otherwise no input is received. 8.4 Operating Modes ESAI operating mode are selected by the ESAI control registers (TC CR, TCR, RCCR, RCR and SAICR).
Operating Mod es DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-44 F reescale Semico nductor 8.4.3 ESAI Interrupt Requests The ESAI can generate eight differen t interrupt requests (ordered from th e highest to the lowest priority) : 1.
Operating Modes DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-45 8. ESAI T r ansmit Data Occurs when the transmit interrupt is enabled (TIE =1), at least one.
Operating Mod es DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-46 F reescale Semico nductor Data clock and frame sync signals can be generated internally by the DSP or may be obtained from external sources.
GPIO - Pins and Regi sters DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-47 RCCR and SAICR registers.Th e output data bits (OF2, OF1 and OF0) and the input data bits (IF2, IF1 and IF0) are double buffered to/from th e HCKR, FSR and SCKR pins.
GPIO - Pins and Regi sters DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-48 F reescale Semico nductor 8.5.3 P or t C Data register (PDRC) The read/write 24-bit Port C Data Register (see Figure 8-21 ) is used to read or write data to/from ESAI GPIO pins.
ESAI Initialization Examples DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 8-49 8.6 E SAI Initialization Examples 8.6.1 Initializing the ESAI Using Individual Reset • The ESAI should be in its individual reset state (PCRC = $000 and PRRC = $000).
ESAI Initialization Examples DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 8-50 F reescale Semico nductor • Configure the control registers TCCR and TCR according to the operating mode, making sure to clear the transmitter enable bits (TE0 - TE5).
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-1 9 Enhanced Serial A udio Interface 1 (ESAI_1) 9.1 Intr oduction The Enhanced Serial Audio Interface I (ESAI_1) is the second ESAI periphe ral in the DSP56366.
Introd uction DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-2 F reescale Semico nductor Figure 9-1 ESAI_1 Block Dia gram Clock / Frame Sync Generators and Control Logic SDO1_1 [PE10].
ESAI_1 Data and Contr ol Pins DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-3 9.2 E SAI_1 Data and Contr ol Pins The ESAI_1 has 6 dedicated pi ns and shares 4 pins with the ESAI. The pins are de scribed in the following sections.
ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-4 F reescale Semico nductor 9.2.6 Serial T ransmit 5/Receiv e 0 Data Pin (SDO5_1/SDI0_1) SDO5_1/SDI0_1 transmit.
ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-5 The ESAI_1 also contains the GPIO Port E functionality , described in Section 9.
ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-6 F reescale Semico nductor 9.3.2.1 TCCR_1 Tx High Freq. Clock Divider (TFP3-TF P0) - Bits 14–17 Since the ES.
ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-7 Figure 9-4 ESAI_1 Clock Generator Functional Bloc k Diagram FLAG0 OUT (SYNC MODE) FL.
ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-8 F reescale Semico nductor Figure 9-5 ESAI_1 Frame Sync Generator Function al Block Diag ram 9.3.3 ESAI_1 T ransmit Control Register (TCR_1) The read/write T r ansmit Control Re gister (TCR_1) controls the ESAI _1 transmitter sec tion.
ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-9 9.3.4 ESAI_1 Receive Cloc k Contr ol Register (RCCR_1) The read/write Receive Clock .
ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-10 F reescale Semico nductor 9.3.5 ESAI_1 Receive Contr ol Register (RCR_1) The read/write Receive Control Register (R CR_1) controls the ESAI_1 receiver section.
ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-11 9.3.8 ESAI_1 Receive Shift Register s The receive shift registers receive the incoming data from the serial receive data pins.
ESAI_1 Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-12 F reescale Semico nductor 9.3.12 ESAI_1 Time Sl ot Register (TSR_1) The write-only T ime Slot Register (TSR _1) is ef fectively a null data register that is used when the data is not to be transmitted in the available transmit time slot.
Operating Modes DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-13 9.4 Operating Modes 9.4.1 ESAI_1 After Reset Hardware or software reset clears the EMUXR re .
GPIO - Pins and Regi sters DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-14 F reescale Semico nductor 9.5.2 P ort E Direction Register (PRRE) The read/write 24-bit Port E Direct ion Register (PRRE) in conjunction with the Port E Control Register (PCRE) controls the functionali ty of the ESAI_1 GPIO pins.
GPIO - Pins and Regi sters DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 9-15 1 1 1 0 9876543210 Y :$FFFF9D PD11 PD10 PD9 PD8 PD7 PD6 PD4 PD3 PD1 PD0 23 22 21 20 19 18 17 16 15 14 13 12 Reser ved bit - read as z ero; should be written with zero for future compatibility .
GPIO - Pins and Regi sters DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 9-16 F reescale Semico nductor NO TES.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 10-1 10 Digital A udio T ransmitter 10.1 Intr oduction The Digital Audio T ransmitter (DAX) is a serial audio interface module that outputs digital audio data in the AES/EBU, CP-340 and IEC958 formats.
D AX Signals DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 10-2 F reescale Semico nductor Figure 10-1 Digital A udio T ransmitter (D AX) Bloc k Diagram 10.
D AX Pr ogramming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 10-3 • Parity generator (PR TYG) • Preamble generator • Biphase encoder • Clock multiplexer • Control state machine XADR, XADBUF A, XADBUFB and XADS R creates a FIFO-like data pa th.
D AX Internal Ar chitecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 10-4 F reescale Semico nductor 10.5 D AX Internal Ar chitecture Hardware components shown in Figure 10-1 are described in the following sections. The DAX programming model is illustrated in Figure 10-2 .
D AX Internal Ar chitecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 10-5 10.5.1 D AX A udio Data Register (XADR) XADR is a 24-bit write-only re gister . One frame of audio data, which is to be tran smitted in the next fr ame slot, is transferred to this register .
D AX Internal Ar chitecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 10-6 F reescale Semico nductor 10.5.4.2 D AX Channel A Us er Data (XU A)—Bit 11 The value of the XUA bit is transmitte d as the thirtieth bit (B it 29) of the channel A subframe in the next frame.
D AX Internal Ar chitecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 10-7 10.5.6.1 Audio Data Register Empty Interrupt Enable (XDIE)—Bit 0 When the XDIE bit is set, the audio data register empty inte rrupt is enabled and send s an interrupt request signal to the DSP if the XADE status bit is set.
D AX Internal Ar chitecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 10-8 F reescale Semico nductor 10.5.7.1 D AX A udio Data Register Empty (XADE)—Bit 0 The XADE status flag indicates th at the DAX audio data register XADR and the audio data buf fer XADBUF A are empty (and ready to rece ive the next frame’ s audio data).
D AX Internal Ar chitecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 10-9 10.5.8 D AX P a rity Generator (PR TYG) The PR TYG generates the parity bit for the subframe being transmitted. The gene rated parity bit ensures that subframe bits four to thirty-one w ill carry an even number of ones and zeroes.
D AX Programming Consideratio ns DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 10-10 F r eescale Semiconductor • The internal DSP core clock—assumes 1024 × Fs • DAX clock input .
D AX Pr ogramming Considerations DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 10-11 non-audio data bits of the next frame are stored in XNADR a nd one frame of audio data to be transmitted in the next frame is stored in th e FIFO by two consecutive MOVEP inst ructions to XADR.
GPIO (PORT D) - Pins and Register s DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 10-12 F r eescale Semiconductor Figure 10-6 Examples of data or ganization in memory 10.6.5 D AX Operation During Stop The DAX operation cannot continue when the DSP is in the stop state since no DSP clocks are active.
GPIO (POR T D) - Pi ns and Register s DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 10-13 10.7.2 P ort D Direction Register (PRRD) The read/write 24-bit Port D Direct ion Register controls the direction of the DAX GPIO pins.
GPIO (PORT D) - Pins and Register s DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 10-14 F r eescale Semiconductor 10.7.3 P o r t D Data Register (PDRD) The read/write 24-bit Port D Data Register is used to read or write data to/fro m the DAX GPIO pins.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-1 11 Timer/ Event Counter 11.1 Intr oduction This section describes the internal timer/event counter in the DSP56366.
Timer/Event Counter Architecture DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-2 F reescale Semico nductor 11.2.2 Individual Timer Bloc k Diagram Figure 1 1-2 shows the structure of an indi vidual timer module. The three timer s are identical in structure, but only timer 0 is externally accessible.
Timer/Event Counter Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-3 11.3 Timer/Event Counter Pr ogramming Model The DSP56366 views each timer as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data memory space.
Timer/Event Counte r Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-4 F reescale Semico nductor Figure 11-3 Timer Module Pr ogrammer’ s Model DO DI DIR 15 14 13 1.
Timer/Event Counter Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-5 11.3.1 Prescaler Counter The prescaler counter is a 21-bit counter that is decr emented on the rising edge of the prescaler input clock.
Timer/Event Counte r Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-6 F reescale Semico nductor 11.3.2.3 TPL R Reserved Bit 23 This reserved bit is read as zero and should be written with zero for future compatibility .
Timer/Event Counter Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-7 Clearing the TE bit disables th e timer . The TE bit is cl eared by the hardware RESET signal or the software RESET instruction.
Timer/Event Counte r Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-8 F reescale Semico nductor T a ble 11-2 Timer Contr ol Bits f or Timer 0 Bit Settings Mode Char.
Timer/Event Counter Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-9 11.3.4.5 TCSR In vert er (INV) Bit 8 The INV bit affects the polarity of the incoming signal on the TIO0 input signal and the polarity of the output pulse generated on the TIO0 output signal.
Timer/Event Counte r Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-10 F r eescale Semiconductor NO TE The INV bit affects both th e timer and GPIO modes of operation.
Timer/Event Counter Programming Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-11 The DO bit is cleared by the hardware RESET signal or the softwa re RESET instruction. This bit is not in use for timers 1 and 2.
Timer Modes of Operation DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-12 F r eescale Semiconductor 11.3.5 Timer Load Register (TLR) The TLR is a 24-bit write-only register . In all modes, the counter is prel oaded with the TLR value after the TE bit in the TCSR is set and a first event occurs.
Timer Modes of Operatio n DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-13 — Event counter , mode 3: Internal timer interrupt generated by an external clo.
Timer Modes of Operation DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-14 F r eescale Semiconductor 11.4.1.2 Timer Pulse (Mo de 1) In this mode, the timer generates a compare interrupt when the timer count reaches a preset value. In addition, timer 0 provides an exte rnal pulse on its TIO0 signal.
Timer Modes of Operatio n DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-15 When the counter value matches the value in the TCPR, the polarity of the TIO0 output signal is inverted. The TCF bit in the TCSR is set and a compare in terrupt is generated if the TCIE bit is set.
Timer Modes of Operation DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-16 F r eescale Semiconductor 11.4.2 Signal Measurement Modes The following signal measurement modes are provided: • Measurement input width • Measurement input period • Measurement capture These functions are av ailable only on timer 0.
Timer Modes of Operatio n DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-17 11.4.2.3 Measurement In put P eriod (Mode 5) In this mode, the timer counts the period between the reception of signal edges of the same polarity across the TIO0 signal.
Timer Modes of Operation DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-18 F r eescale Semiconductor clock signal can be taken from either the DSP56366 clock divided by two (CLK/2) or fr om the prescaler clock output. Each subsequent cloc k signal increments the counter .
Timer Modes of Operatio n DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-19 The duty cycle of the TIO0 signal is determined by the value in the TC PR. When the value in the TLR is incremented to a value equal to the value in the TCPR, the TIO0 signal is toggled.
Timer Modes of Operation DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-20 F r eescale Semiconductor 11.4.4.2 W atchdog T oggle (Mode 10) In this mode, the timer generates an interrupt at a preset rate. T ime r 0 also toggles the output on TIO0.
Timer Modes of Operatio n DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor 11-21 11.4.6.2 Timer B ehavior during Stop During the execution of the ST OP inst ruction, the timer clocks are disabled, timer ac tivity is stopped, and the TIO0 signal is disconnect ed.
Timer Modes of Operation DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 11-22 F r eescale Semiconductor NO TES.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor A-1 Appendix A Bootstrap R OM Contents A.1 DSP56366 Bootstrap Pr ogram ; BOOTSTRAP CODE FOR DSP56366 Rev. 0 silicon - (C) Copyright 1999 Motorola Inc. ; ; ; Revision 0.
DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 A-2 F reescale Semico nductor ; Program ROM, without loading the Program RAM. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Operation mode MD:MC:MB:MA=0011 is reserved.
DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor A-3 ; The HOST 8051 bootstrap code expects to read 3 bytes forming a 24-bit word ; spe.
DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 A-4 F reescale Semico nductor ;; ;;;;;;;;;;;;;;;;;;;; DSP I/O REGISTERS ;;;;;;;;;;;;;;;;;;;;;;;; ;; M_AAR1 EQU .
DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor A-5 SHILD ; This is the routine which loads a program through the SHI port. ; The SHI operates in the slave ; mode, with the 10-word FIFO enabled, and with the HREQ pin enabled for ; receive operation.
DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 A-6 F reescale Semico nductor ; MD:MC:MB:MA=0001 EPROMLD move #BOOT,r2 ; r2 = address of external EPROM movep #.
DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor A-7 ; E - i8051 - Dual strobes multiplexed bus with negative strobe pulses ; dual negative request. ; F - MC68302 - Single strobe non-multiplexed bus with negative strobe ; pulse single negative request.
DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 A-8 F reescale Semico nductor ; future compatability ; HEN = 0 When the HPCR register is modified ; HEN should .
DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor A-9 ; HROD = 0 Host request is active when enabled ; spare = 0 This bit should be set .
DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 A-10 F reescale Semico nductor ;======================================================================== ; MD:M.
DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor A-11 ;; r5 = test fail flag = $000000 lua (r5)-,r7 ;; r7 = test pass flag = $FFFFFF bu.
DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 A-12 F reescale Semico nductor move y:(r0)+,a1 ;; a0=a2=0 eor x0,a add a,b ;; accumulate error in b _loopd else.
DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor A-13 BURN_END ORG PL:,PL: PATTERNS dsm 4 ;; align for correct modulo addressing ORG PL.
DSP56366 Bootstrap Program DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 A-14 F reescale Semico nductor move x0,x:(r0)+ move #$1,x0 move x0,x:(r0)+ move #$2,x0 move x0,x:(r0)+ move #$3.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-1 Appendix B Equates ;********************************************************************************* ; EQUAT.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-2 F reescale Semico nductor ;------------------------------------------------------------------------ ; Interrupt Request Pins ;.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-3 I_ESAIRLS EQU I_VEC+$36 ; ESAI Receive Last Slot I_ESAITD EQU I_VEC+$38 ; ESAI Transmit Data I_ESAITE.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-4 F reescale Semico nductor I_HI08TX EQU I_VEC+$62 ; Host Transmit Data Empty I_HI08CM EQU I_VEC+$64 ; Host Command (Default) ;-.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-5 ; ; EQUATES for I/O Port Programming ; ;-------------------------------------------------------------.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-6 F reescale Semico nductor M_IAL1 EQU 1 ; IRQA Mode Interrupt Priority Level (high) M_IAL2 EQU 2 ; IRQA Mode Trigger Mode M_IBL.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-7 M_D4L0 EQU 20 ; DMA4 Interrupt Priority Level (low) M_D4L1 EQU 21 ; DMA4 Interrupt Priority Level (hi.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-8 F reescale Semico nductor ;------------------------------------------------------------------------ ; Register Addresses Of DM.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-9 M_DCR3 EQU $FFFFE0 ; DMA3 Control Register ; Register Addresses Of DMA4 M_DSR4 EQU $FFFFDF ; DMA4 Sou.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-10 F reescale Semico nductor M_DRS1 EQU 12 ;DMA Request Source bit 1 M_DRS2 EQU 13 ;DMA Request Source bit 2 M_DRS3 EQU 14 ;DMA .
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-11 ;------------------------------------------------------------------------ ; ; EQUATES for Phase Lock.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-12 F reescale Semico nductor M_PEN EQU 18 ; PLL Enable Bit M_COD EQU 19 ; PLL Clock Output Disable Bit M_PD EQU $F00000 ; PreDiv.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-13 M_BA1W EQU $3E0 ; Area 1 Wait Control Mask (BA1W0-BA14) M_BA1W0 EQU 5 ;Area 1 Wait Control Bit 0 M_B.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-14 F reescale Semico nductor M_BRW0 EQU 2 ;Out of Page Wait States bit 0 M_BRW1 EQU 3 ; Out of Page Wait States bit 1 M_BPS EQU .
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-15 M_BAM EQU 6 ; Address Muxing M_BPAC EQU 7 ; Packing Enable M_BNC EQU $F00 ; Number of Address Bits t.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-16 F reescale Semico nductor M_S EQU 7 ; Scaling Bit M_I0 EQU 8 ; Interupt Mask Bit 0 M_I1 EQU 9 ; Interupt Mask Bit 1 M_S0 EQU .
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-17 M_BE EQU 10 ; Burst Enable M_TAS EQU 11 ; TA Synchronize Select M_BRT EQU 12 ; Bus Release Timing M_ABE EQU 13 ;Async.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-18 F reescale Semico nductor M_XBLK EQU 2 ; DAX Block Transferred (XBLK) ; non-audio bits in XNADR M_XVA EQU 10 ; DAX Channel A .
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-19 ; HSAR bits M_HA6 EQU 23 ; SHI I2C Slave Address (HA6) M_HA5 EQU 22 ; SHI I2C Slave Address (HA5) M_.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-20 F reescale Semico nductor ; control bits in HCKR M_HFM1 EQU 13 ; SHI Filter Model (HFM1) M_HFM0 EQU 12 ; SHI Filter Model (HF.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-21 M_RCR_1 EQU $FFFF97 ; ESAI_1 Receive Control Register (RCR_1) M_TCCR_1 EQU $FFFF96 ; ESAI_1 Transmit.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-22 F reescale Semico nductor M_RCR EQU $FFFFB7 ; ESAI Receive Control Register (RCR) M_TCCR EQU $FFFFB6 ; ESAI Transmit Clock Co.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-23 M_RS21 EQU 5 ; ESAI M_RS20 EQU 4 ; ESAI M_RS19 EQU 3 ; ESAI M_RS18 EQU 2 ; ESAI M_RS17 EQU 1 ; ESAI .
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-24 F reescale Semico nductor M_TS27 EQU 11 ; ESAI M_TS26 EQU 10 ; ESAI M_TS25 EQU 9 ; ESAI M_TS24 EQU 8 ; ESAI M_TS23 EQU 7 ; ES.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-25 M_TS1 EQU 1 ; ESAI M_TS0 EQU 0 ; ESAI ; RCCR Register bits M_RHCKD EQU 23 ; ESAI M_RFSD EQU 22 ; ESA.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-26 F reescale Semico nductor M_RPM1 EQU 1 ; ESAI M_RPM0 EQU 0 ; ESAI ; RCR Register bits M_RLIE EQU 23 ; ESAI M_RIE EQU 22 ; ESA.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-27 M_THCKD EQU 23 ; ESAI M_TFSD EQU 22 ; ESAI M_TCKD EQU 21 ; ESAI M_THCKP EQU 20 ;ESAI M_TFSP EQU 19 ;.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-28 F reescale Semico nductor M_TLIE EQU 23 ; ESAI M_TIE EQU 22 ; ESAI M_TEDIE EQU 21 ; ESAI M_TEIE EQU 20 ; ESAI M_TPR EQU 19 ; .
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-29 M_ALC EQU 8 ;ESAI M_TEBE EQU 7 ; ESAI M_SYN EQU 6 ; ESAI M_OF2 EQU 2 ; ESAI M_OF1 EQU 1 ; ESAI M_OF0.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-30 F reescale Semico nductor M_HORX EQU $FFFFC6 ; HOST Receive Register (HORX) M_HBAR EQU $FFFFC5 ; HOST Base Address Register (.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-31 M_HCSEN EQU $3 ; HOST Chip Select Enable M_HREN EQU $4 ; HOST Request Enable M_HAEN EQU $5 ; HOST Ac.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-32 F reescale Semico nductor M_TCSR0 EQU $FFFF8F ; TIMER0 Control/Status Register M_TLR0 EQU $FFFF8E ; TIMER0 Load Reg M_TCPR0 E.
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor B-33 M_TOF EQU 20 ; Timer Overflow Flag M_TCF EQU 21 ; Timer Compare Flag ; Timer Prescaler Register Bit .
Equates DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 B-34 F reescale Semico nductor NO TES.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor C-1 Appendix C JT A G BSDL -- FILENAME : 56366TQFP_revA.bsdl -- -- M O T O R O L A S S D T J T A G S O F T W A R .
JT A G BSDL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 C-2 F reescale Semico nductor CAS_: out bit; EXTAL: in bit; CVCC: linkage bit_vector(0 to 1); CGND: linkage bit_vector(0 to 1).
JT A G BSDL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor C-3 "QVCCH: (20, 49, 95), " & "HP: (43, 42, 41, 40, 37, 36, 35, 34, 33, 32, 31, 22.
JT A G BSDL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 C-4 F reescale Semico nductor attribute INSTRUCTION_OPCODE of DSP56366 : entity is "EXTEST (0000)," & "SAMP.
JT A G BSDL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor C-5 "28 (BC_1, *, control, 1)," & "29 (BC_6, D(2), bidir, X, 28, 1, Z)," &.
JT A G BSDL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 C-6 F reescale Semico nductor "80 (BC_1, RESET_, input, X)," & "81 (BC_1, *, control, 1)," & ".
JT A G BSDL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor C-7 "133 (BC_1, *, control, 1)," & "134 (BC_6, SDOI41, bidir, X, 133, 1, Z),".
JT A G BSDL DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 C-8 F reescale Semico nductor NO TES.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-1 Appendix D Pr ogrammer’ s Reference D .1 Introduction This section has been compiled as a reference for programmers.
Internal I/O Memory Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-2 F reescale Semico nductor T ab le D-1. Inter nal I/O Memory Map Peripheral Address Register Name IPR X:$FFFFFF.
Internal I/O Memor y Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-3 DMA4 X:$FFFFDF DMA SOURCE ADDRESS REGISTER (DSR4) X:$FFFFDE DMA DESTINA TION ADDRESS.
Internal I/O Memory Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-4 F reescale Semico nductor ESAI X:$FFFFBC ESAI RECEIVE SL O T MASK REGISTER B (RSMB) X:$FFFFBB ESAI RECEIVE SLO.
Internal I/O Memor y Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-5 X:$FFFF99 Reser ved X:$FFFF98 Reser ved X:$FFFF97 Reser ved X:$FFFF96 Reser ved X:$F.
Internal I/O Memory Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-6 F reescale Semico nductor Y: $ F F F FA 7 Reser ved Y: $ F F F FA 6 Reser ved Y: $ F F F FA 5 Reser ved Y: $ F.
Internal I/O Memor y Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-7 ESAI_1 Y :$FFFF9C ESAI_1 RECEIVE SLO T MASK REGISTER B (RSMB_1) Y :$FFFF9B ESAI_1 RE.
Interrupt V ector Addresses DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-8 F reescale Semico nductor D .3 Interrupt V ector Ad dresses T able D-2.
Interrupt V ector Addresses DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-9 VBA:$42 0 - 2 SHI T ransmit Underrun Error VBA:$44 0 - 2 SHI Rece ive FIFO Not Em.
Interrupt Source Priori ties (within an IPL) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-10 F reescale Semico nductor D .4 Interrupt Source Prio rities (within an IPL) T abl e D-3.
Interrupt Sou rce Priorities (within an IPL) DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-11 HOST T ransmit Data Interrupt D AX T ransmit Underr un Error D .
Host Interface—Quick Reference DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-12 F reescale Semico nductor D .5 Host Interface—Quick Ref erence T abl e D-4.
Host Interface—Quick Reference DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-13 HPCR 0 HGEN Host GPIO Enable 0 1 GPIO pin disconnected GPIO pins active 0 -.
Host Interface—Quick Reference DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-14 F reescale Semico nductor HSR 0 HRDF Host Receive Data Full 0 1 no receive data to be read receive data register is full 00 0 1 H TDE Host T ransmit Data Empty 1 0 transmit data register empty transmit data reg.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-15 D .6 Programming Sheets The worksheets shown on the following pages contain li stings of major programmable registers for the DSP56366.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-16 F reescale Semico nductor Figure D- 1. Status R egister ( SR) Application: Dat e: Programmer : Sheet 1 of 5 Centra.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-17 Figure D-2. Operating Mode Register (OMR) Chip Operating Modes MOD(D:A) Reset Vector Description See Core Configuration Section.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-18 F reescale Semico nductor Figure D-3. Interrupt Priority Register–Core (IPR–C) Application: Date: Programmer: .
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-19 Figure D-4. Interrupt Priority Regist er – P eripherals (IPR–P) Application: Date: Pr.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-20 F reescale Semico nductor Figure D-5. Phase Loc k Loop Contr ol Register (PCTL) Application: Date: Programmer: She.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-21 Figure D-6. Ho st Receive and Host T ransmit Data Register s Application: Date: Programme.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-22 F reescale Semico nductor Figure D-7. Host Control a nd Status Register s Application: Date: Programmer: Sheet 2 o.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-23 Figure D-8. Host Base Ad dress and Host P or t Contr ol Application: Date: Programmer: Sh.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-24 F reescale Semico nductor Figure D-9. Host Interrupt Contr ol and Interrupt Status Application: Date: Programm er:.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-25 Figure D-10. Host Inte rrupt V ector and Command V ector Application: Date: Programmer : .
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-26 F reescale Semico nductor Figure D-11. Host Re ceive and T ransmit Byte Register s Application: Date: Programmer: .
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-27 Figure D-12. SHI Sla ve Address and Clock Contr ol Registers 10 Application: Date: Progra.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-28 F reescale Semico nductor Figure D-13. SHI T ransmit and Receive Data Register s Application: Date: Programmer: Sh.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-29 Figure D-14. SHI Host Control/Status Register HBUSY I 2 C SPI Mode 0 Stop event Not Busy .
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-30 F reescale Semico nductor Figure D-15. ESAI T ransmit Clock Control Register Application: Date: Programmer : 15 6 .
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-31 Figure D-16. ESAI T ransmit Contr ol Register 15 6 5 4 19 18 17 16 10 9 8 7 14 13 12 11 T.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-32 F reescale Semico nductor Figure D-17. ESAI Receive Cloc k Control Regist er 15 6 5 4 19 18 17 16 10 9 8 7 14 13 1.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-33 Figure D-18. ESAI Receive Contr o l Register 15 6 5 4 19 18 17 16 10 9 8 7 14 1 2 13 1 1 .
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-34 F reescale Semico nductor Figure D-19. ESAI Common Contr ol Register 1 5 654 19 18 17 16 10 9 8 7 14 12 13 11 OF0 .
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-35 Figure D-20. ESAI Status Register 1 5 654 19 18 17 16 10 9 8 7 14 13 12 11 IF0 3210 IF2 23 22 21 20 IF1 RFS RDF Description Description 0 1 Holds data sent fr om SCKR pin.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-36 F reescale Semico nductor Figure D-21. ESAI_1 Multiple x Control Regis ter 1 5 654 19 18 17 16 10 9 8 7 14 12 13 1.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-37 Figure D-22. ESAI_1 T ransmit Clock Contr ol Register Application: Date: Programmer : 15 .
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-38 F reescale Semico nductor Figure D-23. ESAI_1 T ransmit Control Register 15 6 5 4 19 18 17 16 10 9 8 7 14 13 12 11.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-39 Figure D-24. ESAI_1 Receive Cloc k Contr ol Register 15 6 5 4 19 1 8 17 16 10 9 8 7 14 13.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-40 F reescale Semico nductor Figure D-25. ESAI_1 Receive Contr ol Register 15 6 5 4 19 18 17 16 10 9 8 7 14 1 2 13 1 .
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-41 Figure D-26. ESAI_1 Common Contr ol Register 1 5 654 19 18 17 16 10 9 8 7 14 12 13 11 OF0.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-42 F reescale Semico nductor Figure D-27. ESAI_1 Status Register 1 5 654 19 18 17 16 10 9 8 7 14 13 12 11 IF0 3210 IF2 23 22 21 20 IF1 RFS RDF Description Description 0 1 Holds da ta sent from SCK R_1 pin .
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-43 Figure D-28. D AX Non-Audio Data Register DAX 15 14 13 12 1 1 1 0 9876543210 DAX Non-Audi.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-44 F reescale Semico nductor Figure D-29. D AX Control and Status Re gisters XBLK DAX Block transfer 0 not last frame.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-45 Figure D-30. Timer Prescaler Lo ad and Prescaler Count Register s (TPLR, TPCR) Applicatio.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-46 F reescale Semico nductor Figure D-31. Timer Contr ol/Status Register Note that for Timers 1 and 2, TC (3:0 ) = 0000 is the on ly valid combination.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-47 Figure D-32. Timer Load, Compare and Count Register s Application: Date: Programmer: Shee.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-48 F reescale Semico nductor Figure D-33. GPIO P ort B Application: Date: Programmer: Sheet 1 of 4 GPIO 1 5 1 4 1 3 1.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-49 Figure D-34. GPIO P ort C Application: Date: Programmer: Sheet 2 of 4 GPIO 2 3 1 1 987654.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-50 F reescale Semico nductor Figure D-35. GPIO P ort D Application: Date: Programmer: Sheet 3 of 4 GPIO 2 3 6543210 P.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 F reescale Semiconductor D-51 Figure D-36. GPIO P o rt E Application: Date: Programmer: Sheet 4 of 4 GPIO 2 3 1 1 98765.
Programming Sheets DSP56366 24-Bit Digital Signal Processor User Manual, Rev . 4 D-52 F reescale Semico nductor NO TES.
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor Index-1 Inde x Numerics 5 V tolerance 1 A adder modulo 5 offset 5 reverse-carry 5 address bus 1 Address Generation Unit 5 add.
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Index-2 Freescale Semiconductor triggered by timer 21 DO bit 10 DO loop 6 DRAM 8 DSP56300 core 2 DSP56300 Family Manual i, 2 DSP56303 Technical Data .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor Index-3 Transmit Data In Master Mode 24 Transmit Data In Slave Mode 22 I 2 C Bus Acknowledgment 18 I 2 C Mode 1 IEC958 10, 1 .
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Index-4 Freescale Semiconductor R reserved bits in TCSR register bits 3, 10, 14, 16–19, 22, 23 11 in TPCR 6 in TPLR 6 RESET 8 reverse-carry adder 5.
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Freescale Semiconductor Index-5 TC0–TC3 bits 7 TCF 11 TCIE bit 7 TCPR 12 TCR 12 TCSR register 6 bit 0—Timer Enable bit (TE) 6 bit 2—Timer Compa.
DSP56366 24-Bit Digital Sign al Processor, Rev . 4 Index-6 Freescale Semiconductor.
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