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M68HC08 Micr ocontr oller s freescale.com MC68HC908MR32 MC68HC908MR16 Data Sheet MC68HC908MR32 Rev. 6.1 07/2005.
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MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 3 Freescale™ and the Freescal e logo are trade marks of Freescale Semicon ductor, Inc. This product incorporates Su perFlash® technology licensed from SST. © Freescale Semiconductor, Inc.
Revision History MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 4 Freescale Semiconductor The following revision history table summarize s changes contained in this document. For your convenience, the page number de signators have been linked to the appropriate loca tion.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 5 List of Chapters Chapter 1 General Descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 2 Memory . . . .
List of Chapters MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 6 Freescale Semiconductor.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 7 Table of Contents Chapter 1 General Description 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 8 Freescale Semiconductor 2.8.7 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.8.8 Stop Mode .
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 9 4.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.4.1 Crystal Amplifier Input Pin (OSC1).
Table of Contents MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 10 Freescale Semiconductor Chapter 7 Central Processor Unit (CPU) 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 11 Chapter 10 Input/Output (I/O) Ports (PORTS) 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 12 Freescale Semiconductor 12.6.2 Software Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.6.3 Output Port Control .
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 13 13.7.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13.7.4 SCI Status Register 1 . . .
Table of Contents MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 14 Freescale Semiconductor 15.5.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 15.5.2 Transmission Format When CPHA = 0 .
MC68HC908MR32 • MC68HC90 8MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 15 Chapter 17 Timer Interface B (TIMB) 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents MC68HC908MR32 • MC68HC90 8MR16 Data Sheet, Rev . 6.1 16 Freescale Semiconductor 18.3 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 18.3.1 Functional Descriptio n .
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 17 Chapter 1 General Description 1.1 Introduction The MC68HC908MR32 is a member of the low-cost , high-performance M68HC08 Family of 8- bit microcontroller units (MCUs).
General De scription MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 18 Freescale Semiconductor • Available packages: – 64-pin plastic quad f lat pack (QFP) – 56-pin shrink dual in -line .
MC68HC908MR32 • MC6 8HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 19 MCU Block Diagram Figure 1-1. MCU Block Diagram CLOCK GENERATOR MODULE SYSTEM INTEGRATION MODULE SERIAL COMMUNICATIONS.
General De scription MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 20 Freescale Semiconductor 1.4 Pin Assignments Figure 1-2 shows the 64-pin QFP pin assignments and Figure 1 -3 shows the 56-pin SDIP pin assignments.
Pin Assignments MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 21 Figure 1-3. 56-Pin SDIP Pin Assignments PTA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 .
General De scription MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 22 Freescale Semiconductor 1.4.1 Power Supply Pins (V DD and V SS ) V DD and V SS are the power supply and grou nd pins. Th e MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply.
Pin Assignments MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 23 1.4.6 External Filter Capacitor Pin (CGMXFC) CGMXFC is an external filter capacitor connection for the CGM. See Chapter 4 Clock Generator Module (CGM) . 1.
General De scription MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 24 Freescale Semiconductor 1.4.15 PWM Gr ound Pin (PWMGND) PWMGND is the ground pin for the pulse-width modu lator module (PWMMC). This dedicated ground pin is used as the ground for the six high-current PWM pins.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 25 Chapter 2 Memory 2.1 Introduction The central processor unit (CPU08) can address 6 4 Kb ytes of memory space.
Memory MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 26 Freescale Semiconductor 2.4 I/O Section Addresses $0000–$005F, shown in Figure 2-2 , contain most of the control, status, and data registers.
Memory Ma p MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 27 $0000 ↓ $005F I/O REGISTERS — 96 BYTES $0060 ↓ $035F RAM — 768 BYTES $0360 ↓ $7FFF UNIMPLEMENTED.
Memory MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 28 Freescale Semiconductor Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $0000 Port A Data Register (PTA) See page 103 . Read: PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Write: Reset: Unaffected by reset $0001 Port B Data Register (PTB) See page 104 .
Memory Ma p MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 29 $000E TIMA Status/Control Regist er (TASC) See page 226 . Read: TOF TOIE TSTOP 00 PS2 PS1 PS0 Write: 0 TRST R Reset: 0 0 1 0 0 0 0 0 $000F TIMA Counter Re gister High (TACNTH) See page 227 .
Memory MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 30 Freescale Semiconductor $001A TIMA Channel 2 Register High (TACH2H) See page 232 . Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write: Reset: Indeterminate after rese t $001B TIMA Channel 2 Register L ow (TACH2L) See page 232 .
Memory Ma p MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 31 $0026 PWM Counter Re gister High (PCNTH) See page 143 . Read: 0 0 0 0 Bit 11 Bit 10 Bi t 9 Bit 8 Write: Reset: 0 0 0 0 0 0 0 0 $0027 PWM Counter Register Low (PCNTL) See page 143 .
Memory MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 32 Freescale Semiconductor $0032 PWM 5 Value Regis ter High (PMVAL5H) See page 145 . Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write: Reset: 0 0 0 0 0 0 0 0 $0033 PWM 5 Value Reg ister Low (PVAL5L) See page 145 .
Memory Ma p MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 33 $003E SCI Baud Rate Regi ster (SCBR) See page 177 . Read: 0 0 SCP1 SCP0 0 SCR2 SCR1 SCR0 Write: R R R Reset: 0 0 0 0 0 0 0 0 $003F IRQ Status/Control Register (ISCR) See page 94.
Memory MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 34 Freescale Semiconductor $0053 TIMB Counter Register Low (TBCNTL) See page 246 . Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 $0054 TIMB Counter Modulo Regist er High (TBMODH) See page 246 .
Memory Ma p MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 35 $FE00 SIM Break Status Regist er (SBSR) See page 191 . Read: RR R R R R B W R Write: Reset: 0 $FE01 SIM Reset Status Regist er (SRSR) See page 192 .
Memory MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 36 Freescale Semiconductor Table 2-1 is a list of vector locations. T able 2-1. V ector Ad dresses Address Vector Low $FFD2 SCI t r ansmit.
Monitor ROM MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 37 2.6 Monitor ROM The 240 bytes at addresses $FE10–$FEFF are reserved ROM addresses that con tain the instructions for the monitor functions. See 18.3 Monitor ROM (MON) .
Memory MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 38 Freescale Semiconductor During a subroutine call, the CPU uses two bytes of the stack to store the return address. The st ack pointer decrements during pu shes and increments during pulls.
FLASH Memory (FLASH) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 39 HVEN — High-Voltage Enable Bit This read/write bit enab les the charge pump to dr ive high voltages for program and erase operations in the array.
Memory MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 40 Freescale Semiconductor 2.8.3 FLASH M ass Erase Operation Use this step-by-step proce dure to erase the entire FLASH memory. 1. Set both the ERASE bit and the MASS bit in the FLASH control register.
FLASH Memory (FLASH) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 41 2.8.4 FLASH Program Operation Use the following step-by-step procedure to progra m a row of FLASH memory. Figure 2-4 shows a flowchart of the programming algorithm.
Memory MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 42 Freescale Semiconductor Figure 2-4. FLASH Programming Flowchart SET HVEN BIT READ THE FLASH BLOCK PROTECT REGISTER WRITE ANY DATA TO AN.
FLASH Memory (FLASH) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 43 2.8.5 FLASH Bl ock Protection Due to the ability of the on-board charge pump to erase and program.
Memory MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 44 Freescale Semiconductor Figure 2-6. FLASH Block Protect Start Addre ss Refer to Table 2-2 for examples of the protect start addre ss.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 45 Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction This section describes the 10-bit analog-to-digital converter (ADC).
MC68HC908MR32 • MC6 8HC908MR16 Data Sheet, Rev . 6.1 46 Freescale Semiconductor Analog-to-Digital Converter (ADC) Figure 3-1. Block Diagram Highlighting ADC Block and Pins CLOCK GENERATOR MODULE SYS.
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 47 Figure 3-2. ADC Block Diagram 3.3.1 ADC Port I/O Pins PTC1/ATD9:PTC0/ATD8 and PTB7/ATD7:PT B0/ATD0 are general-purpose I/O pins that are shared with the ADC channels.
Analog-to-Digital Converter (ADC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 48 Freescale Semiconductor 3.3.3 Conversion Time Conversion starts after a write to the ADSCR. A conversion is between 16 and 17 ADC clock cycles, therefore: The ADC conversion time is determined by the clock source chose n and the divide ratio selected.
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 49 significant bits (LSB), located in the ADC da ta regist er low, ADRL, can be ignored. However, ADRL must be read after ADRH or else the interlocking wi ll prevent all new conversio ns from being stored.
Analog-to-Digital Converter (ADC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 50 Freescale Semiconductor 3.4 Interrupts When the AIEN bit is set, the ADC mo dule is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is gene rated if the COCO bit is at 0.
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 51 3.6.5 ADC Voltage In (ADVIN) ADVIN is the input voltage signal from one of the 10 ADC channels to the ADC module. 3.6.6 ADC External Connections This section describes the ADC external con nections: V REFH and V REFL , ANx, and grounding.
Analog-to-Digital Converter (ADC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 52 Freescale Semiconductor 3.7.1 ADC Status and Control Register This section describes the funct ion of the ADC status and control register (ADSCR). Writing ADSCR aborts the current conversion and initiates a new conversion.
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 53 The voltage levels supplied from internal reference n odes as specified in Table 3-1 are used to verify the operation of the ADC both in p roduction test and for user applications.
Analog-to-Digital Converter (ADC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 54 Freescale Semiconductor 3.7.2 ADC Data Register High In left justified mode, this 8-bit result register holds the eight MSBs of the 10-bit result. This register is updated each time an ADC single c hannel conversion complete s.
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 55 In 8-bit mode, this 8-bit result regist er holds the ei ght MSBs of the 10-bit result. This re gister is updated each time an ADC conversion completes. In 8-bit mode, this register contains no interlocking with ADRH.
Analog-to-Digital Converter (ADC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 56 Freescale Semiconductor ADICLK — ADC Input Clock Select Bit ADICLK selects either bus clock or CGMXCLK as t he input clock source to generate the internal ADC clock.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 57 Chapter 4 Clock Generator Module (CGM) 4.1 Introduction This section describes the clo ck generator module (CGM, version A). The CGM generates the crystal clock signal, CGMXCLK, which operates at the fre quency of the crystal.
Clock Generator Modu le (CGM) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 58 Freescale Semiconductor Figure 4-1. CGM Block Diagram A d d r .
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 59 4.3.1 Crystal Os cillator Circuit The crystal oscillator circuit consists o f an inverting am plifier and an external cr ystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the ou t put.
Clock Generator Modu le (CGM) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 60 Freescale Semiconductor The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to th e final reference frequency, f RDV .
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 61 The PLL also may operate in manual mode (AUTO = 0) . Manual mode is use d by systems that do not require an indicator of the lock condition for proper operatio n.
Clock Generator Modu le (CGM) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 62 Freescale Semiconductor 5. Calculate the bus frequency, f BUS , and compare f BUS with f BUSDES . 6. If the calculated f BUS is not within the tolerance limits of the a pplication, select another f BUSDES or another f RCLK .
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 63 two to correct the duty cycle. Therefore, th e bus cl ock frequency, which is one-half of the base clock frequency, is one-fourth the frequency o f the selected clock (CGMXCLK or CGMVCLK).
Clock Generator Modu le (CGM) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 64 Freescale Semiconductor Figure 4-3 also shows the external components fo r the PLL: • Bypass capaci tor, C BYP • Filter capacitor, C F NOTE Routing should be done with great care t o minimize signal cross talk and noise.
CGM Regis ters MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 65 4.4.6 Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output sign al. It runs at the full speed of the crystal (f XCL K ) and comes directly from the crys tal oscillator circuit.
Clock Generator Modu le (CGM) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 66 Freescale Semiconductor 4.5.1 PLL Control Register The PLL control registe r (PCTL) contains the interrupt enable a nd flag bits, the on/off switch, and the base clock selector bit.
CGM Regis ters MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 67 if the PLL is off. Therefore, PLLON cannot be cleared when BCS is se t, and BCS cannot be set when PLLON is cl ear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register .
Clock Generator Modu le (CGM) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 68 Freescale Semiconductor XLD — Crystal Loss Detect Bit When the VCO output, CGMVCLK, is driving CGMOUT, this read/write bit ca n indicate whethe r the crystal reference frequency is active or not.
Interrupts MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 69 NOTE The multiplier select bits have built-in pr otection that prevents them from being written when the PLL is on (PLLON = 1).
Clock Generator Modu le (CGM) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 70 Freescale Semiconductor 4.8 Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters.
Acquisition/Lock Ti me Specifications MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 71 required to reduce the frequ ency error. Therefore, the slower the reference the longe r it takes to make these corrections. This parameter is also under user co ntrol via the choice of crystal frequency, f XCL K .
Clock Generator Modu le (CGM) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 72 Freescale Semiconductor The K factor in the equations is derived from internal PLL parameters. K ACQ is the K factor when the PLL is configured in acqu isition mode, and K TRK is the K factor when the PLL is configured in tracking mode.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 73 Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configurat ion register (CONFIG).
Configuration Register (CONFIG) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 74 Freescale Semiconductor 5.3 Configuration Register EDGE — Edge - Align Enable Bit EDGE determines if the motor control PWM will o perate in edge-aligned mode or cente r-aligned mode.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 75 Chapter 6 Computer Operating Properly (COP) 6.1 Introduction This section describes the computer operating prop er ly module, a free-running counter that generates a reset if allowed to overflow.
Computer Opera ting Properly (COP) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 76 Freescale Semiconductor The COP counter is a free-running , 6-bit counter preceded by the 13-bit system integration module (SIM) counter.
COP Control Register MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 77 6.3.6 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). See Chapter 5 Configu ration Register (CONFIG) .
Computer Opera ting Properly (COP) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 78 Freescale Semiconductor.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 79 Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (cen tral processor unit) is an e nhanced and fully object-code- compatible version of the M68HC05 CPU.
Central Processor Unit (CPU) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 80 Freescale Semiconductor Figure 7-1. CPU Registers 7.3.1 Accumulator The accumulator is a general-purpose 8-bit registe r. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operation s.
CPU Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 81 7.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location o n the stack. During a reset, the stack pointer is preset to $00FF.
Central Processor Unit (CPU) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 82 Freescale Semiconductor 7.3.5 Condition Code Register The 8-bit condition cod e register contains the interrupt mask and five flags that indicate the re sults of the instruction just executed.
Arithmetic/Logic Unit (ALU ) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 83 Z — Zero Flag The CPU sets the zero flag when an arithmetic o peration, logic operation, or data manipulation produces a result of $00.
Central Processor Unit (CPU) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 84 Freescale Semiconductor 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instr uction set.
Instruction Set Summary MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 85 BHS rel Branch if Higher or Same (Same as BCC) PC ← (PC) + 2 + rel ? ( C ) = 0 ––––.
Central Processor Unit (CPU) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 86 Freescale Semiconductor CLR opr CLRA CLRX CLRH CLR opr ,X CLR ,X CLR opr ,SP Clear M ← $00 A ← $00 X ← $00 .
Instruction Set Summary MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 87 JMP opr JMP opr JMP opr ,X JMP opr ,X JMP ,X Jum p PC ← J u m p A d d r e s s ––––.
Central Processor Unit (CPU) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 88 Freescale Semiconductor PULA Pull A from Stack SP ← (SP + 1); Pul l ( A ) –––––– I N H 8 6 2 PULH P.
Opcode Map MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 89 7.8 Opcode Map See Table 7-2 . SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (.
MC68HC908MR32 • MC6 8HC908MR16 Data Sheet, Rev . 6.1 90 Freescale Semiconductor Central Processor Unit (CPU) T able 7-2. Opcode Map Bit Manipulation Branch Read-Modify-Write Control Register/Memory .
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 91 Chapter 8 External Interrupt (IRQ) 8.1 Introduction This section describes the extern al interrupt (IRQ) module, which supports exte rnal interrupt functions.
External Interrupt (IRQ) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 92 Freescale Semiconductor Interrupt signals on the IRQ pin are latched into the IRQ1 latch.
IRQ Pin MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 93 Figure 8-3. IRQ Interrupt Flowchart FROM RESET I BIT SET? FETCH NEXT YES NO INTERRUPT? INSTRUCTION SWI INSTRUC.
External Interrupt (IRQ) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 94 Freescale Semiconductor A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE1 bit is set, the IRQ pin is both falling-edge -sensitive and low-level- sensitive.
IRQ Status and Control Register MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 95 IMASK1 — IR Q Interrupt Mask Bit Writing a logic 1 to this read/write bit disables IRQ interrupt requests.
External Interrupt (IRQ) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 96 Freescale Semiconductor.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 97 Chapter 9 Low-Voltage Inhibit (LVI) 9.1 Introduction This section describes the low-vo ltage inhibit (LVI) module, which monitors the voltage on the V DD pin and can force a reset when the V DD voltage falls to the LVI trip voltage.
Low-Voltage Inhibit (LVI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 98 Freescale Semiconductor Once an LVI reset o ccurs, the MCU remains in reset until V DD rise s above a voltage, V LVRX + V LVHX . V DD must be above V LVRX + V LVHX for only one CPU cycle to bring the MCU out of reset.
LVI Status and Control Register MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 99 9.4 LVI Status and Control Re gister The LVI status register (LVISCR) flags V DD voltages below the V LVRX level .
Low-Voltage Inhibit (LVI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 100 Freescale Semiconductor With the LVIRST bit in the confi guration register programmed to 1, the LVI module can generate a reset and bring the MCU out of wait mode. 9.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 101 Chapter 10 Input/Output (I/O) Ports (PORTS) 10.1 Introduction Thirty-seven bidirectional input-output (I/O) pins and se ven input pins fo rm six parallel port s. All I/O pins are programmable as inputs or out puts.
Input/Output (I/O) Ports (PORTS) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 102 Freescale Semiconductor $0005 Data Direction Register B (DDRB) See page 105 . Read: DDRB7 DDRB6 DDRB5 D DRB4 DDRB3 DDRB2 DDRB1 D DRB0 Write: R e s e t : 00000000 $0006 Data Direction Re gister C (DDRC) See page 106 .
Port A MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 103 10.2 Port A Port A is an 8-bit, general-purpose, bid irectional I/O port. 10.2.1 Port A Data Register The port A data register (PTA) con tains a data latch for each of the eight port A pins.
Input/Output (I/O) Ports (PORTS) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 104 Freescale Semiconductor Figure 10-4. Port A I/O Circuit When bit DDRAx is a logic 1, reading add ress $0000 reads the PTAx data latch. Wh en bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin.
Port B MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 105 10.3.2 Data Dir ection Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresp onding port B pin; a logic 0 disable s the output buffer.
Input/Output (I/O) Ports (PORTS) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 106 Freescale Semiconductor 10.4 Port C Port C is a 7-bit, general-purpose, bidi rectional I/O port that shares two of its pins with the analog-to-digital convertor module (ADC).
Port D MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 107 Figure 10-10 shows the port C I/O logic. Figure 10-10. Port C I/O Circuit When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin.
Input/Output (I/O) Ports (PORTS) MC68HC908MR32 • MC68HC90 8MR16 Data Sheet, Rev . 6.1 108 Freescale Semiconductor Figure 10-12 shows the port D input logic. Figure 10-12. Port D Input Circuit Reading address $0003 reads th e voltage level on the pin.
Port E MC68HC908MR32 • MC68HC90 8MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 109 10.6.2 Data Dir ection Register E Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresp onding port E pin; a logic 0 disables the output buffer.
Input/Output (I/O) Ports (PORTS) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 110 Freescale Semiconductor 10.7 Port F Port F is a 6-bit, special function port that shares four of its pins with the serial peripheral interface module (SPI) and two pins with the serial communications interface (SCI).
Port F MC68HC908MR32 • MC68HC90 8MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 111 Figure 10-18 shows the port F I/O logic. Figure 10-18. Port F I/O Circuit When bit DDRFx is a logic 1, r eading address $0009 read s the PTFx data latch. When bit DDRFx is a logic 0, reading address $0009 reads the voltage level on the pin.
Input/Output (I/O) Ports (PORTS) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 112 Freescale Semiconductor.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 113 Chapter 11 Power-On Reset (POR) 11.1 Introduction This section describes the power-on re set (POR) module. 11.2 Functional Description The POR module provides a known, stable signal to the microcontroller unit (MCU) at power-on.
Power-On Reset (POR) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 114 Freescale Semiconductor.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 115 Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC) 12.1 Introduction This section describes the pulse-width modulator for motor control (PWMMC, version A). The PWM module can generate three complementar y PWM pairs or six independent PWM signals .
MC68HC908MR32 • MC6 8HC908MR16 Data Sheet, Rev . 6.1 116 Freescale Semiconductor Pulse-Width Modulator f o r Motor Control (PWMMC) Figure 12-1. Block Diagram Highlighting PWMMC Block and Pins CLOCK .
Features MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 117 Figure 12-2. PWM Module Block Diagram Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $0020 PWM Control Regis ter 1 (PCTL1) See page 146.
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 118 Freescale Semiconductor $0025 PWM Output Control Register (PWMOUT ) See page 154. Read: 0 OUTCTL OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 Write: Reset: 0 0 0 0 0 0 0 0 $0026 PWM Counter Register Hig h (PCNTH) See page 143.
Features MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 119 $0030 PWM 4 Value Register Hig h (PVAL4H) See page 145. Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write: Reset: 0 0 0 0 0 0 0 0 $0031 PWM 4 Value Register Low (PVAL4L) See page 145.
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 120 Freescale Semiconductor 12.3 Timebase This section provides a discussion of t he timebase. 12.3.1 Resolution In center-aligned mode, a 12-bit up/d own counter is used to create the PWM period.
Timebase MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 121 For edge-aligned mode, a 12-bit up-onl y counter is used to create the PWM period. Therefore, the PWM resolution in edge-aligned mod e is one clock (highest resolution is125 ns @ f OP = 8 MHz) as shown in Figure 12-5 .
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 122 Freescale Semiconductor 12.3.2 Prescaler To permit lower PWM freq uencies, a prescaler is prov ide d which will divide the PWM clock frequency by 1, 2, 4, or 8.
PWM Generators MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 123 For ease of software, the LDFQx bits are buffer ed. When the LDFQx bits are changed, the reload frequency will not change until the previous reload cycle is completed.
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 124 Freescale Semiconductor Figure 12-8. Center-Aligned PWM Value Loading Figure 12-9.
PWM Generators MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 125 Figure 12-11. Edge-Aligned Modulus Loading 12.4.2 PWM Data Overflow and Underflow Conditions The PWM value registers are 16-bit registers. Althou gh the counter is only 12 bits, the u ser may write a 16-bit signed value to a PWM value reg ister.
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 126 Freescale Semiconductor 12.5 Output Control This subsection discus ses output control.
Output Control MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 127 When complementary operation is used, tw o additional features are provided : • Dead-time insertion .
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 128 Freescale Semiconductor Figure 12-14. Dead-Time Gen erators FAULT POLARITY/OUTPUT DRIVE PWM.
Output Control MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 129 Figure 12-15. Effects of Dead-Time Insertion Figure 12-16.
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 130 Freescale Semiconductor Figure 12-17. Dead-Time and Small Pulse Widths 12.
Output Control MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 131 For a typical motor drive inverter as shown in Figure 12-13 , for a given top/b ottom transistor pair,.
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 132 Freescale Semiconductor To allow for correction based on different current se nsing methods or co rrection controlled by software, the ISENS1 and ISENS0 bits in PWM control register 1 are provided to choose the corr ection method.
Output Control MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 133 Figure 12-20. Top/Bottom Correction for PWMs 1 and 2 12.5.4 Output Polarity The output polarity of the PWMs is determined by two options: TOPNEG and BOTNEG.
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 134 Freescale Semiconductor Figure 12-21. PWM Polarity UP/DOWN COUNTER MODULUS = 4 PWM <= 0 .
Output Control MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 135 12.5.5 PWM Output Port Control Conditions may arise in which the PWM pins need to be individually controlled. This is made po ssible by the PWM output control register (PW MOUT) shown in Figure 12-22 .
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 136 Freescale Semiconductor Figure 12-23. Dead-Time Insertion During OUTCTL = 1 Figure 12-24.
Fault Protecti on MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 137 12.6 Fault Protection Conditions may arise in th e exter nal drive circuitry which require t hat the PWM sig nals become inactive immediately, such as an overcurrent fault condition .
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 138 Freescale Semiconductor Figure 12-26. PWM Disab ling Scheme FINT2 CYCLE START LOGIC HIGH FO.
Fault Protecti on MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 139 Figure 12-27. PWM Disabling Decode Scheme 12.6.1.1 Fault Pin Filter Each fault pin incorporates a filter to assist in determining a genuine fault condition.
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 140 Freescale Semiconductor Figure 12-28. PWM Disabling in Autom atic Mode IIf prior to a vector fetch, the inte rrupt request latch is cleared by one of the actions listed, a CPU interrupt will no longer be requested.
Fault Protecti on MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 141 Figure 12-30. PWM Disabling in Manua l Mode (Example 2) 12.
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 142 Freescale Semiconductor 12.7 Initialization and the PWMEN Bit For proper operation, all registers should be initia lized and the LDOK bit should be set before enablin g the PWM via the PWMEN bit.
PWM Operation in Wait Mode MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 143 12.8 PWM Operation in Wait Mode When the microcontroller is put in low-power wait mode via the WAIT instruction, all clocks to the PWM module will continue to run.
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 144 Freescale Semiconductor 12.9.2 PWM Counte r Modulo Registers The PWM counter modulus registers (PMODH and PMODL) ho ld a 12-bit unsigned number that determines the maximum count for the up/down or up -only counter.
Control Logic Block MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 145 12.9.3 PWMx Value Registers Each of the six PWMs has a 16-bit PW M value register. The 16-bit signed value stored in this register determi nes the duty cycle of the PWM.
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 146 Freescale Semiconductor 12.9.4 PWM Control Register 1 PWM control register 1 (PCTL1) controls PWM enabling/ disabling, the lo ading of new modulus, prescaler, PWM values, and the PWM correction method.
Control Logic Block MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 147 NOTE The ISENSx bits are not buffered. Changing the current sensing method can affect the present PWM cycle.
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 148 Freescale Semiconductor 12.9.5 PWM Control Register 2 PWM control register 2 (PCTL2) con trols the PWM load frequency, the PWM correction method, and the PWM counter prescaler.
Control Logic Block MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 149 NOTE When reading this bit, th e value read is the buffer value (not necessarily the value the output control block is current ly using).
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 150 Freescale Semiconductor 12.9.6 Dead-Time Write-Once Register The dead-time write-once re gister (DEADTM) holds an 8-bit value which specifies the number of CPU clock cycles to use for the dead-time when complement ary PWM mode is selected.
Control Logic Block MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 151 FMODE4 —Fault Mode Selection for Fault Pin 4 Bit ( autom atic versus manual mode) This read/write bit allows the u ser to select between automatic and manual mode faults.
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 152 Freescale Semiconductor 12.9.9 Fault Status Register The fault status register (FSR) is a read-only register that indicates the current fault status.
Control Logic Block MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 153 FFLAG1 — Fault Event Flag 1 The FFLAG1 event bit is set within two CPU cycles after a rising edge on fault pin 1. To clear the FFLAG1 bit, the user must write a 1 to the FTACK1 bit in the fault acknowledge register.
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 154 Freescale Semiconductor DT2 — Dead-Time 2 Bit Current sensing pin IS1 is mon itored immediately before dead-time ends due to the assertion of PWM2.
PWM Glossary MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 155 12.10 PWM Glossary CPU cycle — One internal bus cycle (1/ f OP ) PWM clock cycle (or period) — One tick of the PWM counter (1/f OP with no prescaler). See Figure 12-47 .
Pulse-Width Modulator f o r Motor Control (PWMMC) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 156 Freescale Semiconductor PWM Load Frequency — Frequency at which new PWM parameters get loaded into the PWM. See Figure 12-48 . Figure 12-48.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 157 Chapter 13 Serial Communications Interface Module (SCI) 13.1 Introduction This section describes the serial communica.
MC68HC908MR32 • MC6 8HC908MR16 Data Sheet, Rev . 6.1 158 Freescale Semiconductor Serial Commun ications Inte rface Module (SCI ) Figure 13-1. Block Diagram Highlighting SCI Block a nd Pins CLOCK GEN.
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 159 13.3 Functional Description Figure 13-2 shows the structure of the SCI module. The SC I allows full-du plex, asynchronous, NRZ serial communication among the MCU and remote device s, in cluding other MCUs.
Serial Communications In terface Modu le (SCI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 160 Freescale Semiconductor 13.3.1 Data Format The SCI uses the standard no n-return-to-zero mark/space data fo rmat illustrated in Figure 13-4 . Figure 13-4.
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 161 13.3.2 Transmitter Figure 13-5 shows the structure of the SCI transmitter.
Serial Communications In terface Modu le (SCI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 162 Freescale Semiconductor 13.3.2.1 Character Length The transmitter can accommod ate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length.
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 163 13.3.2.4 Idle Characters An idle character contains all 1s and has no start, st op, or parity bit. Id le character length depends on the M bit in SCC1.
Serial Communications In terface Modu le (SCI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 164 Freescale Semiconductor Figure 13-6. SCI Receiver Block Diagram 13.3.3.1 Character Length The receiver can accommodat e either 8-bit or 9-bit data.
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 165 13.3.3.2 Character Reception During an SCI reception, the receive shift reg ister shi fts characters in from th e PTF4/RxD pin. The SCI data register (SCDR) is the read-onl y buffer between the internal data bus and the receive shift register.
Serial Communications In terface Modu le (SCI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 166 Freescale Semiconductor If start bit verification is not successful, the RT cl ock is reset and a new sea rch for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10.
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 167 13.3.3.4 Framing Errors If the data recovery logic does not d etect a 1 where t he stop bit should be in an incoming ch aracter, it sets the framing error bit, FE, in SCS1.
Serial Communications In terface Modu le (SCI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 168 Freescale Semiconductor • Noise flag (NF) — The NF bit is set when t he SCI det ects noise on incoming data or break characters, including start, data, and stop bits.
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 169 13.6.2 PTF4/RxD (Receive Data) The PTF4/RxD pin is the serial data in put to the SCI receiver.
Serial Communications In terface Modu le (SCI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 170 Freescale Semiconductor ENSCI — Enable SCI Bit This read/write bit enable s the SCI and the SCI baud rate gen erator. Clearing ENSCI sets the SCTE and TC bits in SCI statu s register 1 and disables transmitter interrupts.
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 171 13.7.2 SCI Cont rol Register 2 SCI control register 2 (SCC2): • Enables these CPU interrupt requests:.
Serial Communications In terface Modu le (SCI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 172 Freescale Semiconductor SCRIE — SCI Receive Interrupt Enable Bit This read/write bit enables th e SCRF bit to generate SCI receiver CPU inte rrupt requests.
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 173 13.7.3 SCI Cont rol Register 3 SCI control register 3 (SCC3): • Stores the ninth SCI data b it receiv.
Serial Communications In terface Modu le (SCI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 174 Freescale Semiconductor 13.7.4 SCI Status Register 1 SCI status register 1 (SCS1) contai ns fl.
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 175 IDLE — Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receive r input. IDLE generates an SCI error CPU interrupt request if the ILIE bit in SCC2 is also set.
Serial Communications In terface Modu le (SCI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 176 Freescale Semiconductor In applications that are sub ject to software latency or in which it i.
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 177 RPF —Reception-in-Progress Flag This read-only bit is set when the receiver de tects a logic 0 during the RT1 time period of the start bit search. RPF does not generat e an interrupt request.
Serial Communications In terface Modu le (SCI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 178 Freescale Semiconductor SCR2–SCR0 — SCI Baud Rate Select Bits These read/write bits select the SCI bau d rate divisor as shown in Table 13-6 .
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 179 T able 13-7. SCI Baud Rate Selection Exa mples SCP1:SCP0 Prescaler Divisor (PD) SCR2:SCR1:SCR 0 Baud Rate Divisor (BD) Baud Rate (f OP = 7.3728 MHz) Baud Rate (f OP = 4.
Serial Communications In terface Modu le (SCI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 180 Freescale Semiconductor.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 181 Chapter 14 System Integration Module (SIM) 14.1 Introduction This section describes the system inte gration module (SIM). Together with the centra l processor unit (CPU), the SIM controls all micr ocontroller unit (MCU) activities.
System Integration Module (SIM) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 182 Freescale Semiconductor Figure 14-1. SIM Block Diagram 14.2 SIM Bus Clock Control and G eneration The bus clock generator provides system clock signa ls for the CPU and peripherals on the MCU.
Reset and System Initialization MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 183 Figure 14-2. CGM Clock Signals 14.2.3 Clocks in Wait Mode In wait mode, the CPU clocks are inactive. The SIM also pr oduces two sets of clocks for oth er modules.
System Integration Module (SIM) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 184 Freescale Semiconductor Figure 14-3. External Reset Timing 14.3.2 Active Resets from Internal Sources All internal reset sources actively pu ll the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals.
Reset and System Initialization MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 185 14.3.2.1 Power-On Reset (POR) When power is first applied to the MCU, the power- on reset (POR) module ge nerates a pulse to indicate that power-on has occurred.
System Integration Module (SIM) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 186 Freescale Semiconductor signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, V HI on the RST pin disables the COP module.
Exception Control MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 187 14.5 Exception Control Normal, sequential program execution can be changed in three different ways: 1. Interrupts: a. Maskable hardware CPU interrupts b.
System Integration Module (SIM) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 188 Freescale Semiconductor Figure 14-8. Interrupt Processing NO NO YES AS MANY INTERRUPTS AS EXIST ON CHIP SWI I.
Exception Control MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 189 Figure 14-9. Interrupt Recovery 14.5.1.1 Hardware Interrupt s A hardware interrupt does not stop t he current instruction. Processing of a hardware interrupt be gins after completion of the current instruction.
System Integration Module (SIM) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 190 Freescale Semiconductor 14.5.1.2 Software Interrupt (SWI) Instruction The software interrupt (SWI) instruction is a non-maska ble instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register.
SIM Regi sters MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 191 Figure 14-13. Wait Recovery from Internal Reset 14.6.2 Stop Mode In stop mode, the SIM counter is reset an d the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode.
System Integration Module (SIM) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 192 Freescale Semiconductor SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. 14.
SIM Regi sters MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 193 14.7.3 SIM Break Flag Control Register The SIM break control register (SBFCR) con tains a bit that enables software to clear status bits while the MCU is in a break state.
System Integration Module (SIM) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 194 Freescale Semiconductor.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 195 Chapter 15 Serial Peripheral Interface Module (SPI) 15.1 Introduction The serial peripheral interface (SPI) module allows full-duplex, synchronous, serial co mmunications with peripheral devices.
MC68HC908MR32 • MC6 8HC908MR16 Data Sheet, Rev . 6.1 196 Freescale Semiconductor Serial Peripheral In terface Module (SPI) Figure 15-1. Block Diagram Highligh ting SPI Block and Pins CLOCK GENERATOR.
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 197 15.4 Functional Description Figure 15-2 shows the structure of the SPI module and Figure 15-3 shows the locations a nd contents of the SPI I/O registers.
Serial Peripheral In terface Module (SPI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 198 Freescale Semiconductor 15.4.1 Master Mode The SPI operates in master mode wh en the SPI master bit, SPMSTR, is set. NOTE Configure the SPI modules as master or sla ve before enabling them.
Transmission Formats MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 199 SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control register with SPRF set and then readin g the SPI data register.
Serial Peripheral In terface Module (SPI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 200 Freescale Semiconductor The clock phase (CPHA) control bit selects one of tw o fundamentally different transmission formats. The clock phase and polarity sh ould be identical for the master SPI device and the communicating slave device.
Transmission Formats MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 201 When CPHA = 0 for a slave, th e falling edge of SS indicates the beginning of th e transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with t he MSB of its data.
Serial Peripheral In terface Module (SPI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 202 Freescale Semiconductor When CPHA = 1, the first SPSCK cycl e begins with an edge on the SPSCK line from its inactive to its active level.
Error Conditions MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 203 15.6 Error Conditions These flags signal SPI error conditions: • Overflow (OVRF) — Failing to read the SPI data register bef ore the next full byte enters the shift register sets the OVRF bit.
Serial Peripheral In terface Module (SPI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 204 Freescale Semiconductor In this case, an overflow can easily be missed. Since no more SPRF interrupts can be generated until this OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed.
Error Conditions MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 205 OVRF individually to generate a re ceiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. In a master SPI with the mode fault enable bit (MODFE N) set, the mode fault flag (MODF) is set if SS goes to logic 0.
Serial Peripheral In terface Module (SPI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 206 Freescale Semiconductor 15.7 Interrupts Four SPI status flags can be enabled to gen erate CPU interrupt requests as shown in Table 15-2 .
Resetting the SPI MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 207 15.8 Resetting the SPI Any system reset completely resets the SPI. Partia l resets occur whenever th e SPI enable bit (SPE) is low. Whenever SPE is low: • The SPTE flag is set.
Serial Peripheral In terface Module (SPI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 208 Freescale Semiconductor Figure 15-12. SPRF/SPTE CPU Interrupt Timing 15.10 Low-Power Mode The WAIT instruction puts the MCU in a low power-consumption standby mode.
I/O Signals MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 209 The SPI has limited inter-integrated circuit (I 2 C) capability (requiring software support) as a master in a single-master environment.
Serial Peripheral In terface Module (SPI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 210 Freescale Semiconductor When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as a general-purpose I/O regardless of the state of the MODFEN control bit.
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 211 SPRIE — SPI Receiver Interrupt Enable Bit This read/write bit enable s CPU interrupt requests generated by the SPRF bit. T he SPRF bit is set when a byte transfers from the shift register to the receive data register.
Serial Peripheral In terface Module (SPI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 212 Freescale Semiconductor SPE — SPI Enable Bit This read/write bit enabl es the SPI module. Clearing SPE causes a partial reset of the SPI . See 15.8 Resetting the SPI .
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 213 OVRF — Overflow Bit This clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift registe r.
Serial Peripheral In terface Module (SPI) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 214 Freescale Semiconductor Use this formula to calculate the SPI baud rate: where: CGMOUT = base clock output of the clock generator module (CGM) BD = baud rate divisor 15.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 215 Chapter 16 Timer Interface A (TIMA) 16.1 Introduction This section describes the timer in terface module A (T IMA).
MC68HC908MR32 • MC6 8HC908MR16 Data Sheet, Rev . 6.1 216 Freescale Semiconductor Timer Interface A (TIMA) Figure 16-1. Block Diagram Highlighting TIMA Block and Pins CLOCK GENERATOR MODULE SYSTEM IN.
Features MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 217 Figure 16-2. TIMA Block Diagram PTE3/TCLKA PRESCALER PRESCALER SELECT TCLK INTERNAL 16-BIT COMPARATOR PS2 PS.
Timer Interface A (TIMA) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 218 Freescale Semiconductor Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $000E TIMA Status/Control Regist er (TASC) See page 226 . Read: TOF TOIE TSTOP 00 PS2 PS1 PS0 Write: 0 TRST R Reset: 0 0 1 0 0 0 0 0 $000F TIMA Counter Re gister High (TACNTH) See page 227 .
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 219 16.3 Functional Description Figure 16-2 shows the TIMA structure. The central component of the TI MA is the 16-bit TIMA counter that can operate as a free-running counter or a modulo up-counte r.
Timer Interface A (TIMA) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 220 Freescale Semiconductor x referring to the active channel number). When an ac tive ed ge occurs on the pin of an input capture channel, the TIMA latches the co ntents of the TI MA counter into the TIMA channel registers, TACHxH–TACHxL.
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 221 Use this method to synchronize unbu ffered changes in the output compare value on chann el x: • When changing to a smaller value, enable channe l x output compare interrupts and write the new value in the output compare interrupt routine.
Timer Interface A (TIMA) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 222 Freescale Semiconductor to clear the channel pin on output compare if the polarity of the PWM pulse is 1 (ELSxA = 0). Program the TIMA to set the pin if the polarity of the PWM pulse is 0 (EL SxA = 1).
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 223 duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise.
Timer Interface A (TIMA) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 224 Freescale Semiconductor 4. In TIMA channel x status an d control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode se lect bits, MSxB–MSxA.
I/O Signals MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 225 The TIMA remains active after the execution of a WAIT instruction. In wait mode, the TIMA register s are not accessible by the CPU. Any enabled CPU interrupt request from the TIMA can bring the MCU out of wait mode.
Timer Interface A (TIMA) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 226 Freescale Semiconductor TOF — TIMA Overflow Flag This read/write flag is set when the T IMA counter reaches the modulo va lue programmed in the TIMA counter modulo registers.
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 227 PS[2:0] — Prescaler Select Bits These read/write bits select eithe r the PTE3/TCLKA pin or one of the seven prescaler outputs as th e input to the TIMA counter as Table 16 -1 shows.
Timer Interface A (TIMA) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 228 Freescale Semiconductor 16.7.3 TIMA Counter Modulo Registers The read/write TIMA modulo registers contain the mod ulo value for the TIMA counter.
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 229 CHxF — Channel x Flag Bit When channel x is an input cap ture channel, this read/write bit is set when an active edge occurs on the channel x pin.
Timer Interface A (TIMA) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 230 Freescale Semiconductor MSxB — Mode Select Bit B This read/write bit selects buffere d output compare/PWM operation. MSxB exists only in the TIMA channel 0 and TIMA channel 2 stat us and control registers.
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 231 TOVx — Toggle-On-Overflow Bit When channel x is an output compare channel, this re ad/write bit controls the behavior of the channel x output when the TIMA counter overflows.
Timer Interface A (TIMA) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 232 Freescale Semiconductor 16.7.5 TIMA C hannel Registers These read/write registers contain t he captured TIMA counter value of the input capture function or the output compare value of the o utput compare function.
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 233 Register Name and Address : TACH2L — $001B B i t 7 654321 B i t 0 Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3.
Timer Interface A (TIMA) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 234 Freescale Semiconductor.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 235 Chapter 17 Timer Interface B (TIMB) 17.1 Introduction This section describes the timer interface module B (T IMB).
MC68HC908MR32 • MC6 8HC908MR16 Data Sheet, Rev . 6.1 236 Freescale Semiconductor Timer Interface B (TIMB) Figure 17-1. Block Diagram Highlighting TIMB Block and Pins CLOCK GENERATOR MODULE SYSTEM IN.
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 237 Figure 17-2. TIMB Block Diagram Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $0051 TIMB Status/Control Regist er (TBSC) See page 244 .
Timer Interface B (TIMB) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 238 Freescale Semiconductor 17.3.1 TIMB Counter Prescaler The TIMB clock source can be one of the se ven prescaler outputs or the TIMB clock pin, PTE0/TCLKB . The prescaler generates seven clock rates from the inte rnal bus clock.
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 239 whether the TIMB channel flag (CH0F–CH1F in TBSC0–TBSC 1 registers) is set or clea r. When the status flag is set, a CPU interrupt is generated if enabled.
Timer Interface B (TIMB) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 240 Freescale Semiconductor 17.3.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the PTE1/TCH0B pin.
Functional Description MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 241 The value in the TIMB channel registers determines th e pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 incremen ts.
Timer Interface B (TIMB) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 242 Freescale Semiconductor currently active channel to prevent writing a new value to the active channel. Writing to the active channel reg isters is the same as generating unbuffered PWM signals.
Interrupts MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 243 17.4 Interrupts These TIMB sources can generate interrup t requests: • TIMB overflow flag (TOF) — The timer overflow flag (TOF) bit is set when the TIMB counter reaches the modulo value programmed in the TIMB counter modulo registers.
Timer Interface B (TIMB) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 244 Freescale Semiconductor 17.7 I/O Registers These input/output (I/O) registers contro l and monitor TIMB operation: .
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 245 TSTOP — TIMB Stop Bit This read/write bit stops the TIMB counter. Countin g resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMB counter un til software clears the TSTOP bit.
Timer Interface B (TIMB) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 246 Freescale Semiconductor 17.7.2 TIMB C ounter Registers The two read-only TIMB counter registers contain the high and low bytes of the value in the TIMB counte r. Reading the high byte (TBCNTH) latch es the contents of the low byte (TBCNTL) into a buffer.
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 247 17.7.4 TIMB Channel Stat us and Control Registers Each of the TIMB channel status and cont rol register.
Timer Interface B (TIMB) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 248 Freescale Semiconductor MSxB — Mode Select Bit B This read/write bit selects buffere d output compare/PWM operation. MSxB exists only in the TIMB channel 0. Setting MS0B disables the channel 1 status a nd control register and reverts TCH1B to general-purpose I/O.
I/O Registers MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 249 NOTE When TOVx is set, a TIMB counter overflow takes preceden ce over a channel x output compare if both occur at t he same time.
Timer Interface B (TIMB) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 250 Freescale Semiconductor 17.7.5 TIMB C hannel Registers These read/write registers contain t he captured TIMB counter value of the input capture function or the output compare value of the o utput compare function.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 251 Chapter 18 Development Support 18.1 Introduction This section describes the break modu le, the moni tor read-only memory (MON), a nd the monitor mode entry methods. 18.
Development Support MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 252 Freescale Semiconductor Figure 18-1. Break Module Block Diagram A d d r . R e g i s t e r N a m e B i t 7 654321 B i t 0 $FE00 SIM Break Status Register (SBSR) See page 255.
Break Module (BRK) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 253 18.2.1.2 CPU During Break Interrupts The CPU starts a break interrupt by: • Loading the instruct.
Development Support MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 254 Freescale Semiconductor 18.2.3.1 Break Status and Control Register The break status and control register (BRKSCR) conta ins break module enable and status bits. BRKE — Break Enable Bit This read/write bit enable s breaks on break addres s register matches.
Monitor ROM (MON) MC68HC908MR32 • MC68HC90 8MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 255 18.2.3.3 Break Status Register The break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode. The flag is useful in application s requiring a return to wait mode after exiting from a break interrupt.
Development Support MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 256 Freescale Semiconductor Features include: • Normal user-mode pin functionality • One pin dedicated to serial communicati on between monitor ROM and host computer • Standard mark/space non-return-to-zero (NRZ) communication with host computer • 4800 baud–28.
Monitor ROM (MON) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 257 Figure 18-8. Monitor Mode Circuit + + + + 10 M Ω X1 V DD V HI MC145407 MC74HC125 MC68HC908MR16/ RST IRQ CGMXFC OSC1 OSC2 V SSA V SS V DD PTA0 V DD 10 k Ω 0.
MC68HC908MR32 • MC6 8HC908MR16 Data Sheet, Rev . 6.1 258 Freescale Semiconductor Development Support T able 18-2. Monitor Mode Signal Requirements and Options IRQ RESET (S1) $FFFE /$FFFF PLL PTC3 PTC4 PTC2 (S2) External Clock (1) 1. External clock is derived by a 32.
Monitor ROM (MON) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 259 Enter monitor mode by either: • Executing a software interr upt instruction (SWI) or • Applying a logic 0 and then a logic 1 to the RST pin Once out of reset, the MCU waits f or the host to send eight security bytes.
Development Support MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 260 Freescale Semiconductor 18.3.1.5 Echoing As shown in Figure 18-11 , the monitor ROM immedia tely echoes each received byte back to th e PTA0 pin for error checking. Figure 18-11.
Monitor ROM (MON) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 261 T able 18-3. READ (Read Memory) Command Description Read byte from memor y Operand 2-byte address in high-byte:low-byte order Data Retur ned Retur ns contents of specified address Opcode $4A Command Sequence T able 18-4.
Development Support MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 262 Freescale Semiconductor A sequence of IREAD or IWRITE commands can acce ss a block of memory sequentially over the full 64-Kbyte memory map.
Monitor ROM (MON) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 263 18.3.1.8 Baud Rate With a 4.9152-MHz crystal and the PTC2 pin at lo gic 1 durin g reset, data is transferred between the monitor and host at 4800 baud.
Development Support MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 264 Freescale Semiconductor Figure 18-13. Monitor Mode Entry Timing BYTE 1 BYTE 1 ECHO BYTE 2 BYTE 2 ECHO BYTE 8 BYTE 8 ECHO .
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 265 Chapter 19 Electrical Specifications 19.1 Introduction This section contains electrical an d timing specifications.
Electrical Specifications MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 266 Freescale Semiconductor 19.3 Functional Operating Range 19.4 Thermal Characteristics Characteristic Symbol Value Unit Operating t emperature range (1) MC68HC908MR24CFU MC68HC908MR24VFU 1.
DC Electrical Characteristics MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 267 19.5 DC Electrical Characteristics Charact eristic (1) 1. V DD = 5.0 Vdc ± 10%, V SS = 0 Vdc, T A = T L to T H , unless otherwise noted. Symbol Min Typ (2) 2.
Electrical Specifications MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 268 Freescale Semiconductor 19.6 FLASH Memory Characte ristics 19.7 Control Timing Characteristic Symbol Min Typ Max Unit RAM data retenti on v oltag e V RDR 1.
Serial Peripheral Inte rface Characteristics MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 269 19.8 Serial Peripheral Interface Characteristics Diagram Number (1) 1.
Electrical Specifications MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 270 Freescale Semiconductor Figure 19-1. SPI Master Timing NOTE SS PIN OF MASTER HELD HIGH MSB IN SS INPUT SPCK, CPOL =.
Serial Peripheral Inte rface Characteristics MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 271 Figure 19-2. SPI Slave Timi ng Note: Not defined, but normally MSB of ch.
Electrical Specifications MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 272 Freescale Semiconductor 19.9 TImer Interface Module Characteristics 19.
CGM Acquisition/Lock Time Specifications MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 273 19.12 CGM Acquisition/Lo ck Time Specifications Description Symbol Min Typ Max Notes Filter capacitor multiply f actor C FA C T — 0.
Electrical Specifications MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 274 Freescale Semiconductor 19.13 Analog-to-Digital Co nverter (ADC) Characteristics Characteristic Symbol Min Typ Max Unit Notes Supply v olta ge V DDAD 4.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 275 Chapter 20 Ordering Information and Mechanical Specifications 20.1 Introduction This section provides ordering inform.
Ordering Information and Mechanical Specifications MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 276 Freescale Semiconductor 20.3 64-Pin Plastic Quad Flat Pack (QFP).
56-Pin Shrink Du al In-Line Pac kage (SDIP) MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 277 20.4 56-Pin Shrink Dual In-Line Package (SDIP).
Ordering Information and Mechanical Specifications MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 278 Freescale Semiconductor.
MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 Freescale Semiconductor 279 Appendix A MC68HC908MR16 The information contained in this d ocument pertains to the MC68HC908MR16 with the exception of that shown in Figure A-1 .
MC68HC908MR16 MC68HC908MR32 • MC68 HC908MR16 Data Sheet, Rev . 6.1 280 Freescale Semiconductor $0000 ↓ $005F I/O REGISTERS — 96 BYTES $0060 ↓ $035F RAM — 768 BYTES $0360 ↓ $7FFF UNIMPLEMEN.
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