Gebruiksaanwijzing /service van het product MPC5200B van de fabrikant Freescale Semiconductor
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MPC5200B User s Guide Document Number : MPC5200BUG Re v . 1 05/2005.
T able of Contents Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor TO C - 1 Chapter 1 Introduction 1.1 Overview ......... ................ ............. ................ ............. ............... ........
Ta b l e O f C o n t e n t s Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 TO C - 2 F reescale Semiconductor 4.2.2 Hard Reset—HRESET ...... ................ ................ ............... .............. ............... .........
T able of Contents Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor TO C - 3 Chapter 7 System Integration Unit ( SIU ) 7.1 Overview ......... ................ ............. ................ ............. .....
Ta b l e O f C o n t e n t s Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 TO C - 4 F reescale Semiconductor 7.3.2.1.16 GPS GPIO Simple Inte rrupt Status Register—MBAR + 0x0B3C ........... ...................... ......... ........
T able of Contents Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor TO C - 5 8.4.4.3 Bank Active Command ................ ................ ............... ................ ................ ............... ....
Ta b l e O f C o n t e n t s Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 TO C - 6 F reescale Semiconductor 9.7.4.4 LPC Rx / Tx FIFO Alarm Re gister—MBAR + 0x3C4C ........... ......................................................
T able of Contents Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor TO C - 7 10.3.3.1.4 Tx Enables PCITER(RW)—MBAR + 0x380 C ............. ............ ...................... ......... ......... ........ ...
Ta b l e O f C o n t e n t s Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 TO C - 8 F reescale Semiconductor 10.4.6.2 Addressing ..... ............. ................ ................ ............... ................ ............... .
T able of Contents Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor TO C - 9 11.3.3.5 ATA Drive Error Register—MBA R + 0x3A64 ................. ................ ............... ................ .............
Ta b l e O f C o n t e n t s Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 TO C - 1 0 F reescale Semiconductor 12.4.3.2 USB HC Period Current Endpoint Descrip tor Register —MBA R + 0x101C .......... ........... ......... .........
T able of Contents Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor TO C -1 1 13.12.22 SDMA Initiator Priority 24 Register—MBAR + 0x1254 ....... ............................................ .................
Ta b l e O f C o n t e n t s Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 TO C - 1 2 F reescale Semiconductor 14.5.17 FEC Descriptor Individual Address 2 Register—MBAR + 0x311C ... ........... ............ ........ ..............
T able of Contents Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor TO C -1 3 15.2.14 Codec Clock Register (0x20)—CCR ..... .................................................................. ......... ......
Ta b l e O f C o n t e n t s Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 TO C - 1 4 F reescale Semiconductor 15.3.3.4 Configuration Sequence for AC97 Mode ....... ................ ............... ................ ............... .
T able of Contents Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor TO C -1 5 Chapter 17 Serial Peripheral Interface ( SPI ) 17.1 Overview ......... ................ ............. ................ ............
Ta b l e O f C o n t e n t s Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 TO C - 1 6 F reescale Semiconductor 19.5.4 MSCAN Control Register 1 (CANCTL1) —MBAR + 0x0901 ........... ........... ............ ........... ........... .
T able of Contents Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor TO C -1 7 Chapter 20 Byte Data Link Controller (BDLC) 20.1 Overview ......... ................ ............. ................ ...............
Ta b l e O f C o n t e n t s Pa ra g ra p h Pag e Number Number MPC5200B Users Guide, Rev . 1 TO C - 1 8 F reescale Semiconductor 20.8.8.1 Transmitting Or Receiv ing A Block Mode Message ....... ................ ................. ................ ....
List of Figures Figure Pa g e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor LOF-1 1-1 Simplified Block Diag ram—MP C5200 ............. ........... ........... ............ ............................................ .. .....
List of Figures Figure Pa g e Number Number MPC5200B Users Guide, Rev . 1 LOF-2 F reescale Semiconductor 12-2 Communication Channel s ..... ................ ............... ................ ................ ............. ................ ... .........
List of Figures Figure Pa g e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor LOF-3 19-11 Initialization Request /Acknowledge Cycle ...... ................................. ............ ...................... ........ ..... .....
List of Figures MPC5200B Users Guide, Rev . 1 LOF-4 F reescale Semiconductor Notes.
List of T ables Ta b l e Pa g e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor LO T -1 2-1 Signals by Ball / Pin ........... ............. ................ ............... ................ ............. ................ .... ...
List of T ables Ta b l e Pa g e Number Number MPC5200B Users Guide, Rev . 1 LO T -2 Freescale Semiconductor 5-19 CDM PSC2 Mclo ck Config ................ ............... .............. ............... ................ ............... ......... .. ....
List of T ables Ta b l e Pa g e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor LO T -3 7-51 SLT 0 Terminal Count Regist er .............. ................................. ..................... ........ ......... ........ . ....
List of T ables Ta b l e Pa g e Number Number MPC5200B Users Guide, Rev . 1 LO T -4 Freescale Semiconductor 10-9 Special Cyc le Message Encodings ...... ............... ................ ............. ................ ............... .......... . .....
List of T ables Ta b l e Pa g e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor LO T -5 12-8 USB HC Period Current Endpoint Descri ptor Register ..... ...................... ................................. ............ ...... .
List of T ables Ta b l e Pa g e Number Number MPC5200B Users Guide, Rev . 1 LO T -6 Freescale Semiconductor 14-1 Signal Properti es ..... ............... ................ ............... .............. ............... ................ ......... .... .
List of T ables Ta b l e Pa g e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor LO T -7 15-9 Stop-Bit L engths ..... ............. ................ ............. ................ ............... .............. .............. ....
List of T ables Ta b l e Pa g e Number Number MPC5200B Users Guide, Rev . 1 LO T -8 Freescale Semiconductor 15-63 Tx FIFO Control (0x88) ............. ....................................................... ............ ........... ........ ......... .
List of T ables Ta b l e Pa g e Number Number MPC5200B Users Guide, Rev . 1 F reescale Semico nductor LO T -9 18-5 I 2 C Control Register ........ ............... ................ ............. ................ ............... ................ .......
List of T ables Ta b l e Pa g e Number Number MPC5200B Users Guide, Rev . 1 LO T -10 Freescale Semiconductor 20-16 BDLC Receiver VPW Symbol Ti ming for Binary Frequencies ..... ................ .................. ............... ............. ........
MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 1 Revision History Release Date A uthor Summary of Changes 0 26MAR2005 AS Initial V ersion 0.1 26MAR2005 AS, TB , PL Updated PCI, PSC , BestComm, I2C , GPIO , CDM chapters . 0.2 03MA Y2005 AE Cross refs, h yperlinks, T OC, V erso , and fonts .
MPC5200B Users Guide, Rev . 1 F reescale Semiconductor.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 1-1 Chapter 1 Intr oduction 1.1 Overview The digital communication ne tworking and consumer markets re quire significant processor perfor mance to enable operating systems and applications such as VxW orks ™ , QNX ™ , JA V A and soft modems.
MPC5200B Users Guide, Rev . 1 1-2 F reescale Semiconductor Architecture — IrDA mode from 2400 bps to 4 Mbps • Fast Ethernet Controller (F EC) — Supports 100Mbps IEEE 802.3 MII, 10Mbps IEEE 802.3 MII, 10Mbps 7-wire interface • Universal Serial Bus Controller (USB) — USB Revision 1.
Arc hitectur e MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 1-3 A dynamically managed extern al pin multiplexing sche me minimizes overall pin c ount. The result is low cost packaging and board assem bly costs. Figure 1-1 shows a simplified MPC5200B block diagram.
MPC5200B Users Guide, Rev . 1 1-4 F reescale Semiconductor Architecture The MPC5200B supports a dual extern al bus architectur e consisting of: 1. an SDRAM Bus 2. a multi-function L ocalPlus Bus The SDRAM Bus has a Memory Controller inte rface which supports standard SDRAM and D ouble Data Rate ( DDR ) SDRAM devices.
Arc hitectur e MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 1-5 Figure 1-2. MPC5200B-Based System 1.2.1 Embedded e300 Core The MPC5200B embedded e300 core is derived f r om Freescale’ s (formerly Moto rola) MPC603e family of Re duced Instruction Set Compu ter ( RISC ) microprocessors.
MPC5200B Users Guide, Rev . 1 1-6 F reescale Semiconductor Architecture Up to 3 instructions can be issued and retire d per clock. Most instructions execute in a single cycl e. The core contains an int egrated Floating Point Unit ( FPU ), a Data Cache Memory Management Unit and an Instruction Cache Memory Management Unit.
Arc hitectur e MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 1-7 MSCAN supports both standard and extended id entifier ( ID ) message formats specified in BOSCH CAN protocol sp ecification, revision 2.
MPC5200B Users Guide, Rev . 1 1-8 F reescale Semiconductor Architecture 1.2.5.5 Functional Pin Multiple xing Many serial / parallel port pins serve multiple functi ons, allowing flexibility in optimizing the system to me et a specific set o f integration requirements.
Arc hitectur e MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 1-9 A W ake Up capability is supported by CAN, R TC, several GPIOs and the interrupt lines. Therefore, the MPC5200B can be shut down to a low-power standby mode, then re-enabled by one of the W ake Up inputs without resetting the MPC5200B.
MPC5200B Users Guide, Rev . 1 1-10 F reescale Semiconductor Architecture.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-1 Chapter 2 Signal Descriptions 2.1 Overview The MPC5200B contains a e300 core, an inte rnal DMA engine, Best Comm, multiple functional blocks and associated I/O ports. There are two external data/address bus structures, th e LocalPlus bus and SDRAM bus.
MPC5200B Users Guide, Rev . 1 2-2 F reescale Semiconductor Overview Figure 2-1. 272-Pin PBGA Pin Detail Ta b l e 2 - 1 gives a list of MPC5200 B I / O signa ls sorted by package ball name. Ta b l e 2 - 2 gives the same list sorted by signal name. Many signal pins can h ave multiple functi ons depending on internal regi ster settings.
MPC5200B Users Guide, Rev . 1 F reescale Semiconductor 2-3 Figure 2-2. 272-Pi n PBGA — T op Vie w A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A1 1 A12 A13 A14 A15 A16 A17 A18 A19 A20 TEST_MODE_1 JT AG_T.
MPC5200B Users Guide, Rev . 1 2-4 F reescale Semiconductor Pinout T ables Figure 2-3. MPC5200B P eripheral Muxing 2.2 Pinout T ables T able 2-1. Signal s by Ball / P in B a l l/P i n Pin Name B a l l/.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-5 A11 PSC1_1 C06 PSC3_3 A12 PSC6_2 C07 PSC3_0 A13 PORRESET C08 CORE_PLL_A VDD A14 SRESET C09 PSC2_0 A15 SYS_XT AL_IN C10 PSC1_2.
MPC5200B Users Guide, Rev . 1 2-6 F reescale Semiconductor Pinout T ables E01 TIMER_7 J10 VSS_IO/CORE E02 TIMER_6 J11 VSS_IO/CORE E03 TIMER_5 J12 VSS_IO/CORE E04 VDD_IO J17 MEM_MDQ _ 22 E17 VDD_MEM_IO.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-7 M09 VSS_IO/CORE T18 MEM_MDQ _ 30 M10 VSS_IO/CORE T19 MEM_MDQ _ 3 M11 VSS_IO/CORE T20 MEM_MDQ _ 2 M12 VSS_IO/CORE U01 PCI_REQ .
MPC5200B Users Guide, Rev . 1 2-8 F reescale Semiconductor Pinout T ables V13 EXT_AD _ 0 Y10 EXT_AD _ 10 V14 LP_ALE Y11 EXT_AD _ 7 V15 LP_CS2 Y12 EXT_AD _ 3 V16 LP_CS5 Y13 LP_TS V17 A T A_DRQ Y14 LP_C.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-9 T able 2-2. Signals b y Signal Name Signal Name B a l l/P i n Signal Name B a l l/P i n A T A_D ACK Y18 EXT_AD _ 6 U11 A T A_.
MPC5200B Users Guide, Rev . 1 2-10 F reescale Semiconductor Pinout T ables EXT_AD _ 4 V11 PSC6_0 B12 EXT_AD _ 5 W 12 PSC6_2 A12 PSC6_3 C13 MEM_MBA _1 A17 PSC6_1 C11 MEM_MDQ _ 0 U20 IRQ0 P03 MEM_MDQ _ .
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-11 MEM_MA _ 10 B17 MEM_MDQS _ 0 N20 MEM_MA _ 11 E20 MEM_MDQS _ 1 H20 MEM_MA _ 12 F19 MEM_MDQS _ 2 D18 MEM_MBA _0 C18 MEM_MDQS _.
MPC5200B Users Guide, Rev . 1 2-12 F reescale Semiconductor Pinout T ables PSC2_4 A08 USB_6 G04 PSC3_0 C07 USB_7 F 01 PSC3_1 B07 USB_8 F02 PSC3_2 A07 USB_9 F03 PSC3_3 C06 VDD_C ORE D05 PSC3_4 B06 VSS_.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-13 VDD_MEM_IO P17 VDD_MEM_IO T17 VSS_IO/CORE D04 VSS_IO/CORE D16 VSS_IO/CORE J09 VSS_IO/CORE J10 VSS_IO/CORE J11 T able 2-3.
MPC5200B Users Guide, Rev . 1 2-14 F reescale Semiconductor Pinout T ables T able 2-4. LocalPlus Pin Functions Pin name BAL L LocalPlu s Non-mux LocalPlus MUL TIP LEXED BUS PCI BUS ATA MOST Large Flas.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-15 PCI_CBE_2 W06 PCI_CBE _2 A3 A19 PCI_CBE_3 Y02 PCI_CBE _3 A4 A20 PCI_TRD Y W05 PCI_TRD Y A5 A21 PCI_IRD Y Y06 PCI_IRD Y A6 A2.
MPC5200B Users Guide, Rev . 1 2-16 F reescale Semiconductor Pinout T ables 1. The PCI signals , which are not used as addre ss in Large Flash mode, are drive low during a Large Flash access. 2. F or a burst transaction LP_A CK signal indicates the b urst .
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-17 Pin EXT_AD_30 Ball R03 LocalPlus Bus multiplex ed mode Address Phase 8-Bit Data Phase 16-Bit Data Phase 32-Bit Data Phase TS.
MPC5200B Users Guide, Rev . 1 2-18 F reescale Semiconductor Pinout T ables Pin EXT_AD_27 Ball Y01 LocalPlus Bus multiplex ed mode Address Phase 8-Bit Data Phase 16-Bit Data Phase 32-Bit Data Phase log.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-19 Pin EXT_AD_24 Ball U03 LocalPlus Bus multiplex ed mode Address Phase 8-Bit Data Phase 16-Bit Data Phase 32-Bit Data Phase A2.
MPC5200B Users Guide, Rev . 1 2-20 F reescale Semiconductor Pinout T ables Pin EXT_AD_21 Ball Y03 LocalPlus Bus multiplex ed mode Address Phase 8-Bit Data Phase 16-Bit Data Phase 32-Bit Data Phase A21.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-21 Pin EXT_AD_18 Ball V04 LocalPlus Bus multiplex ed mode Address Phase 8-Bit Data Phase 16-Bit Data Phase 32-Bit Data Phase A1.
MPC5200B Users Guide, Rev . 1 2-22 F reescale Semiconductor Pinout T ables Pin EXT_AD_15 Ball U08 LocalPlus Bus multiplex ed mode Address Phase 8-Bit Data Phase 16-Bit Data Phase 32-Bit Data Phase A15.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-23 Pin EXT_AD_12 Ball Y09 LocalPlus Bus multiplex ed mode Address Phase 8-Bit Data Phase 16-Bit Data Phase 32-Bit Data Phase A1.
MPC5200B Users Guide, Rev . 1 2-24 F reescale Semiconductor Pinout T ables Pin EXT_AD_9 Ball V10 LocalPlus Bus multiplex ed mode Address Phase 8-Bit Data Phase 16-Bit Data Phase 32-Bit Data Phase A9 l.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-25 Pin EXT_AD_6 Ball U11 LocalPlus Bus multiplex ed mode Address Phase 8-Bit Data Phase 16-Bit Data Phase 32-Bit Data Phase A6 .
MPC5200B Users Guide, Rev . 1 2-26 F reescale Semiconductor Pinout T ables Pin EXT_AD_3 Ball Y12 LocalPlus Bus multiplex ed mode Address Phase 8-Bit Data Phase 16-Bit Data Phase 32-Bit Data Phase A3 l.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-27 Pin EXT_AD_0 Ball V13 LocalPlus Bus multiplex ed mode Address Phase 8-Bit Data Phase 16-Bit Data Phase 32-Bit Data Phase A0 .
MPC5200B Users Guide, Rev . 1 2-28 F reescale Semiconductor Pinout T ables Pin PCI_TRD Y Ball W05 PCI PCI_TRD Y logic 1 PCI_TRD Y PCI T arget Ready LFLASH A21 logic 1 Large Flash Address Bit A21 MOST .
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-29 Pin PCI_RESET Ball R02 PCI PCI_RESET logic 0 PCI Reset Output (open drain) MOST Graphics A15 logic 0 MOST Graphics Address Bit A15 T able 2-7.
MPC5200B Users Guide, Rev . 1 2-30 F reescale Semiconductor Pinout T ables T able 2-8. LocalPlus Dedicated Signals PIN / BALL NUMBER Function Reset Va l u e Description Pin LP_RW Ball W16 LocalPlus Re.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-31 Figure 2-4 . PSC1 P or t Map—5 Pin s T able 2-9. PSC1 Pin Functions Pin Name Dir .
MPC5200B Users Guide, Rev . 1 2-32 F reescale Semiconductor Pinout T ables T able 2-10. PSC1 Functions b y Pin PIN / BALL NUMBER Function Reset Va l u e Description Pin PSC1_0 Ball B11 GPIO hi - z GPI.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-33 Pin PSC1_3 Ball B10 GPIO hi - z GPIO Simple General Purpose I/O A C97_1 hi - z AC97_1_BITCLK AC97 Bit Cloc k U ART1 hi - z U.
MPC5200B Users Guide, Rev . 1 2-34 F reescale Semiconductor Pinout T ables Figure 2-5 . PSC2 P or t Map—5 Pin s T able 2-11. PSC2 Pin Functions Pin Name Dir .
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-35 T able 2-12. PSC2 Functions b y Pin PIN / BALL NUMBER Function Reset Va l u e Description Pin PSC2_0 Ball C09 GPIO hi - z GP.
MPC5200B Users Guide, Rev . 1 2-36 F reescale Semiconductor Pinout T ables Pin PSC2_3 Ball B08 GPIO hi - z GPIO Simple General Purpose I/O CAN1, CAN2 hi - z CAN2_RX CAN Receive Data A C97_2 hi - z AC9.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-37 Figure 2-6. PSC3 P ort Map—10 Pins T able 2-13. PSC3 Pin Functions Pin name Dir .
MPC5200B Users Guide, Rev . 1 2-38 F reescale Semiconductor Pinout T ables T able 2-14. PSC3 Pin Function s (cont.) Pin name Di r . CODEC3 w / M SPI U ART3 / SPI U AR T3e / SPI CODEC3 / SPI PSC3_0 I/O.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-39 Pin PSC3_1 Ball B07 GPIO hi - z GPIO Simple General Purpose I/O USB2 hi - z USB2_TXN USB T ransmit Negativ e U ART3 hi - z U.
MPC5200B Users Guide, Rev . 1 2-40 F reescale Semiconductor Pinout T ables Pin PSC3_3 Ball C06 GPIO hi - z GPIO Simple General Purpose I/O USB2 hi - z USB2_RXD USB Receive Data U ART3 hi - z UAR T3_CT.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-41 Pin PSC3_5 Ball A06 GPIO hi - z LP_CS_7 USB2 hi - z USB2_RXN USB Receive P ositiv e UA RT 3 h i - z L P _ CS _ 7 U ART3e hi .
MPC5200B Users Guide, Rev . 1 2-42 F reescale Semiconductor Pinout T ables Pin PSC3_7 Ball B05 GPIO hi - z GPIO Simple General Purpose I/O USB2 hi - z USB2_SPEED USB Speed UA RT 3 h i - z G P I O Simp.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-43 Figure 2-7. USB P ort Map—10 Pins Pin PSC3_9 Ball C04 GPIO hi - z GPIO_W/W AKE_UP Simple General Purpose I/O with W AKE UP.
MPC5200B Users Guide, Rev . 1 2-44 F reescale Semiconductor Pinout T ables T able 2-16. USB Pin Functions Pin Name Dir . Reset Configuration GPIO USB 2x U AR T4/5 USB_0 I/O GPIO USB1_OE GPIO USB_1 I/O.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-45 Pin USB_3 Ball G01 GPIO hi - z ---- USB1 hi - z USB1_RXD USB1 Receive Data RESET Config. hi - z ---- UA RT 4 , UA RT 5 h i - z UART 4 _ R X D Uar t Receive Data Pin USB_4 Ball G02 GPIO hi - z ---- USB1 hi - z USB1_RXP USB1 Receive P ositive RESET Config.
MPC5200B Users Guide, Rev . 1 2-46 F reescale Semiconductor Pinout T ables Figure 2-8. Ethernet Output P ort Map—8 Pins Pin USB_9 Ball F03 GPIO hi - z GPIO Simple General Purpose I /O USB1 hi - z USB1_OVRCRNT USB1 Over Current RESET Config.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-47 Figure 2-9. Ethernet In put / Control P ort Map—10 Pins T able 2-18. Ethernet Pin Functions Pin name Dir .
MPC5200B Users Guide, Rev . 1 2-48 F reescale Semiconductor Pinout T ables ETH_9 I/O GPIO GPIO ETH7_RXCLK ETH7_RXCLK ETH_10 I/O GPIO GPIO ETH7_COL ETH7_COL ETH_11 I/O GPIO GPIO ETH 7_TXCLK ETH7_TXCLK .
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-49 ETH_16 I/O ETH18_RXERR ETH18_w/ MD_RXERR U ART4e__DCD INTERR UPT UAR T4_CD INTERRUPT INTERRUPT ETH_17 I/O ETH18_CRS ETH18_w/ MD_CRS GPIO_W/W AKE- UP GPIO_W/W AKE-UP GPIO_W/W AKE-UP GPIO_W/W AKE- UP GPIO_W/W AKE- UP T able 2-20.
MPC5200B Users Guide, Rev . 1 2-50 F reescale Semiconductor Pinout T ables Pin ETH_1 Ball K02 GPIO hi - z GPIO Simple General Purpose Output USB2 hi - z GPIO Simple General Purpose Output ETH7 Wire hi.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-51 Pin ETH_2 Ball K03 GPIO hi - z GPIO Simple General Purpose Output USB2 hi - z USB2_TXP USB T ransmit P ositiv e ETH7 Wire hi.
MPC5200B Users Guide, Rev . 1 2-52 F reescale Semiconductor Pinout T ables Pin ETH_3 Ball J01 GPIO hi - z GPIO Simple General Purpose Output USB2 hi - z USB2_PrtPWR U S B Po r t Po we r ETH7 Wire hi -.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-53 Pin ETH_4 Ball J02 GPIO hi - z GPIO Simple General Purpose Output USB2 hi - z USB2_Speed USB Speed ETH7 Wire hi - z GPIO Sim.
MPC5200B Users Guide, Rev . 1 2-54 F reescale Semiconductor Pinout T ables Pin ETH_5 Ball L03 GPIO hi - z GPIO Simple General Purpose Output USB2 hi - z USB2_Suspend USB Suspend ETH7 Wire hi - z GPIO .
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-55 Pin ETH_6 Ball N02 GPIO hi - z GPIO Simple General Purpose Output USB2 hi - z USB2_OE USB Output Enable ETH7 Wire hi - z GPI.
MPC5200B Users Guide, Rev . 1 2-56 F reescale Semiconductor Pinout T ables Notes: 1. The e xter nal bus clock (pci_clk) will be 1/2 the frequency of t he inter nal bus cloc k (ipb_clk) at powerup. Theref ore, 4 IPbus wait sta tes will translate to as little as 1 external wait state (i.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-57 T able 2-21. Ethernet Input / Contr ol Functions by Pin PIN / BALL NUMBER Function Reset Va l u e Description Pin ETH_8 Ball.
MPC5200B Users Guide, Rev . 1 2-58 F reescale Semiconductor Pinout T ables Pin ETH_10 Ball J03 GPIO hi - z GPIO Simple General Purpose Output USB2 hi - z GPIO Simple General Purpose Output ETH7 Wire h.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-59 Pin ETH_12 Ball M02 GPIO hi - z USB2 hi - z ETH7 Wire hi - z ETH_RXD0 Ethernet Receive Data Input ETH7 Wire / USB2 hi - z ET.
MPC5200B Users Guide, Rev . 1 2-60 F reescale Semiconductor Pinout T ables Pin ETH_14 Ball N04 GPIO hi - z INTERR UPT USB2 hi - z USB_2_RXP USB Receive P ositiv e ETH7 Wire hi - z INTERRUPT ETH7 Wire .
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-61 Pin ETH_16 Ball L02 GPIO hi - z INTERR UPT USB2 hi - z USB_2_O VRCNT USB Over Current ETH7 Wire hi - z INTERRUPT ETH7 Wire /.
MPC5200B Users Guide, Rev . 1 2-62 F reescale Semiconductor Pinout T ables Figure 2-10. Timer P or t Map—8 Pins T able 2-22. Timer Pin Functions Pin Name Dir .
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-63 T able 2-23. Timer F unctions by Pin PIN / BALL NUMBER Function Reset Va l ue Description Pin TIMER_0 Ball Y20 TIMER hi - z .
MPC5200B Users Guide, Rev . 1 2-64 F reescale Semiconductor Pinout T ables Pin TIMER_3 Ball D02 TIMER hi - z TIMER_3 GPIO hi - z GPIO Simple General Pur pose I/O A T A CHIP SELECTS hi - z GPIO Simple .
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-65 Figure 2-11. PSC6 P ort Map—4 Pins Pin TIMER_6 Ball E02 TIMER hi - z TIMER_6 GPIO hi - z GPIO Simple General Pur pose I/O .
MPC5200B Users Guide, Rev . 1 2-66 F reescale Semiconductor Pinout T ables T able 2-24. PSC6 Pin Functions Pin name Dir . GPIO UA R T 6 / I r D A CODEC6 / IrD A PSC6_0 I/O WA KE_UP U ART6_RXD IrD A_RX.
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-67 Figure 2-12. I 2 C P ort Map—4 Pins ( two pins e ach, for tw o I 2 Cs ) T able 2-26.
MPC5200B Users Guide, Rev . 1 2-68 F reescale Semiconductor Pinout T ables T able 2-27. SDRAM Bus Pin Functions PIN B ALL NUMBER Function Reset Va l u e Description Pin MEM_RAS Ball A18 logic 0 SDRAM .
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-69 Pin MEM_MA_11 Ball E20 logic 0 SDRAM Bus Memor y Address 11 Pin MEM_MA_10 Ball B17 logic 0 SDRAM Bus Memor y Address 10 Pin .
MPC5200B Users Guide, Rev . 1 2-70 F reescale Semiconductor Pinout T ables Pin MEM_MDQ_24 Ball M18 hi - z SDRAM Bus Data 24 Pin MEM_MDQ_23 Ball K18 hi - z SDRAM Bus Data 23 Pin MEM_MDQ_22 Ball J17 hi .
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-71 Pin MEM_MDQ_5 Ball R19 hi - z SDRAM Bus Data 5 Pin MEM_MDQ_4 Ball R20 hi - z SDRAM Bus Data 4 Pin MEM_MDQ_3 Ball T19 hi - z .
MPC5200B Users Guide, Rev . 1 2-72 F reescale Semiconductor Pinout T ables T able 2-29. CLOCK / RESET Pin Functions CLOCK / RESET Func tions Reset Va l u e Description Pin PORRESET Ball A13 logic 1 P .
Pinout T ables MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 2-73 Pin LP_OE Ball D08 logic 1 LocalPlus Bus Output Enable Pin IRQ0 Ball P03 External Interr upt 0 Pin IRQ1 Ball P01 External In.
Signal De scriptions Notes MPC5200B Users Guide, Rev . 1 2-74 F reescale Semiconductor.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 3-1 Chapter 3 Memory Map 3.1 Overview The following sections are contained in this document: • MPC5200B Internal Register Memory Map .
MPC5200B Users Guide, Rev . 1 3-2 F reescale Semiconductor Internal Register Memory Map 3.2 Internal Register Memory Map T able 3-1. Internal Regi ster Memory Map Address Name Description Reference MBAR + 0x0000 MM Memory Map Registers Section 3.3.3 MBAR + 0x0100 SDRAM SDRAM Memor y Controller registers.
MPC5200B Memory Map MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 3-3 3.3 MPC5200B Memory Map The MPC5200B memory map has the following main regions: • MPC5200B Internal Register Space •.
MPC5200B Users Guide, Rev . 1 3-4 F reescale Semiconductor MPC5200B Memor y Map 3.3.2.2 LocalPlus Bus The LocalPlus Bus is designed to connect to ROM, FLASH, static RAM and other peripheral devi ces. It is not de signed to accommod ate DRAM’ s. Program execution begins from the Loca lPlus Bus memory device connected to LP_CS0 .
MPC5200B Memory Map MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 3-5 3.3.3 Memory Map Space R egister Description These registers exist in the Memory Map registe r spac e relative to Memory Base Address Register (MBAR). 3.3.3.1 Memory Address Base Re gister —MBAR + 0x0000 3.
MPC5200B Users Guide, Rev . 1 3-6 F reescale Semiconductor MPC5200B Memor y Map All of these Base Address Reg isters work the same 3.3.3.3 SDRAM Chip Select Configuration Registers 0x002C CS5 Star t Address Chip Select 5 through th e LocalPlus Bus. Any access on an address between the Star t and Stop Addresses enabl es this chip select.
MPC5200B Memory Map MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 3-7 msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Base XLB Address Reser v ed W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18.
MPC5200B Users Guide, Rev . 1 3-8 F reescale Semiconductor MPC5200B Memor y Map 3.3.3.4 IPBI Contr ol Register and W ait State Enable —MB AR+0x0054 The IPBI Control Register consists of the Enable s.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 4-1 Chapter 4 Resets and Reset Configuration 4.1 Overview The following sections are contained in this document: • Hard and Soft Reset Pins • Reset Sequence • Reset Operation • Other Resets • Reset Configuration 4.
MPC5200B Users Guide, Rev . 1 4-2 F reescale Semiconductor Reset Sequen ce 4.2.3 Soft Reset—SRESET External SRESET is an open drain signal. SRESET requires an external pull-up. Assertion of SRESET causes a ssertion of the internal soft reset. Internal soft reset is ac tually an interrupt that takes the same exception vector as HRESET .
Other Resets MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 4-3 Figure 4-2. PORRESET Asser tion When external HRESET is asserted, internal reset logic catches the reset signal held low and a sserts internal hard and soft resets for 4096 reference clock cy cles.
MPC5200B Users Guide, Rev . 1 4-4 F reescale Semiconductor Reset Configu ration 4.6 Reset Configuration The MPC5200B is init ialized by sampling values found on specific device pins dur ing power-on reset (PORRESET ) or hard-reset (HRESET ). These pins are outputs in normal operation, but are sampled as inputs during power-on re set or hard-reset.
Reset Configuration MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 4-5 L03 RST_CFG13 ETH5 PORCFG[18] boot_rom_size F or non-muxed boot R OMs: 2,3 bit = 0 : 8 bit boot ROM data b us, 24 bit ma.
Resets and Reset Configuration Notes MPC5200B Users Guide, Rev . 1 4-6 F reescale Semiconductor.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 5-1 Chapter 5 Cloc ks and P ower Mana gement 5.1 Overview The following sections are contained in this document: • Clock Distribution Module (CDM) • MPC5200B Clock Domains • Power Management • CDM Registers 5.
MPC5200B Users Guide, Rev . 1 5-2 F reescale Semiconductor MPC5200B Clock Domains — When generated externally , th e frequency can be different NO TE Only one pin is allocated to s upply the USB and PSC6/IrDA clock. If both modules require exter nal clock generation, the fre quency must b e 48MHz.
MPC5200B Clock Domains MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 5-3 5.3.1 MPC5200B T op Level Cloc k Relations Figure 5-2 shows the CDM clock divide circuitry . Th is picture shows only the functional clocks. The clock network regarding the scan and bypass modes is not included.
MPC5200B Users Guide, Rev . 1 5-4 F reescale Semiconductor MPC5200B Clock Domains Ta b l e 5 - 2 shows the System PLL configuration and the corresponding fsystem frequencies for a 27.0 MH z and 33.0 MHz input clock. Ta b l e 5 - 3 shows all possible clock ratios.
MPC5200B Clock Domains MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 5-5 Ta b l e 5 - 4 shows the typical clock r ati os with a 33.0 MHz clock input on the SYS_XT AL_IN pin and a System PLL divide value 16 (sys_pll_cfg[0] = 0). NO TE Frequency ranges in Ta b l e 5 - 3 and Ta b l e 5 - 4 represen t possib le ranges of operation.
MPC5200B Users Guide, Rev . 1 5-6 F reescale Semiconductor MPC5200B Clock Domains Ta b l e 5 - 6 gives the e300 Core APLL and operating frequency opti ons compared to the xlb_clk reference input (shown in Figure 5-2 ). The selection of an e300 Core frequency is made at Power-On Reset (POR) vi a the reset configuration input s.
MPC5200B Clock Domains MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 5-7 NO TE The XLB CLOCK frequency and the ppc_pll_cfg[0:4] must be chosen such that resulting CORE CLOCK frequency and PLL (f VCOco re ) frequency do n ot exceed thei r respective maximium or minimum operating freque ncies.
MPC5200B Users Guide, Rev . 1 5-8 F reescale Semiconductor MPC5200B Clock Domains Figure 5-3 shows the clock relationships for the SDRAM Controller . Figure 5-3. Timing Dia gram—Clock W a veforms f or SDRAM and DDR Memories The XLB is 64bits a nd the SDRAM external bus is 32bits.
P ower Management MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 5-9 5.4 P ower Management Power Management modes are listed below . Details are give n in the sections that follow .
MPC5200B Users Guide, Rev . 1 5-10 F reescale Semiconductor P ower Manag ement 5.4.3.1 Dynamic P ower Mode This is the default power state mode. The core is fully powered and internal functi onal units are operating at the full process or clock speed.
CDM Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 5-11 mode. The e300 Core must enable the deep sleep process in the CDM module, then put itse lf into sleep mode before the e300 Core PL L can be disabled. Since MPC5200B clocks are stopped in Deep Sleep mode, the wake-up time is longer than in the e300 Core-only power down modes.
MPC5200B Users Guide, Rev . 1 5-12 F reescale Semiconductor CDM Registers 5.5.1 CDM JT A G ID Num ber Register—MB AR + 0x0200 The CDM JT AG ID Number Register is a read -only register that contains the JT AG Identification number identifying MPC5200B.
CDM Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 5-13 15 sys_pll_b ypass bit = 0 :Nor mal mode. The SYS OSC cloc k input is multiplied up by the system PLL, then the PLL VCO is divided down to produce inter nal clocks. bit = 1 :The SYS OSC clock input is used directly , bypassing the system PLL.
MPC5200B Users Guide, Rev . 1 5-14 F reescale Semiconductor CDM Registers 5.5.3 CDM Bread Crumb Register—MB AR + 0x0208 The CDM Bread Crumb Register is a 32-bit regi ster that is not reset. It s purpose is to let firmware designers leave some status code before entering a reset condition.
CDM Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 5-15 NO TE The clock ratio should only be cha nged if no module, which is clocke d by the IPB and/or PCI clock, is currently running. Suggestion is to cha nge the clock ratio dur ing the boot time only .
MPC5200B Users Guide, Rev . 1 5-16 F reescale Semiconductor CDM Registers 5.5.6 CDM Cloc k Enable Register—MB AR + 0x0214 The CDM Clock Enable Register , or power mana gement register , contains control bits th at enable/disable pe ripheral clocks. Unuse d peripherals can have their clock st opped, reducing power consumption.
CDM Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 5-17 5.5.7 CDM System Oscillator C onfiguration Regi ster—MB AR + 0x0218 This register contains the System Oscillator disable bit. The system oscillator is disabled if an external clock so urce (not a crystal) drives the oscillator in package pin.
MPC5200B Users Guide, Rev . 1 5-18 F reescale Semiconductor CDM Registers 5.5.8 CDM Cloc k Contro l Sequencer Confi guration Regist er—MB AR + 0x021C This register contains the conf iguration that controls the CCS module. The CCS mo dule lets MPC5200B enter deep sleep power down mode (all clocks stopped).
CDM Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 5-19 16–30 — Reser ved f or future use. Wr ite 0. 31 ccs_qreq_ test CCS T est bit—Used in CCS module functional simula tion to simulate a QREQ sig nal. bit = 0 : QREQ input to CCS f orced activ e.
MPC5200B Users Guide, Rev . 1 5-20 F reescale Semiconductor CDM Registers 5.5.9 CDM Soft Reset Register—MB AR + 0x0220 This register contains 2 reset control bits. 5.5.10 CDM System PLL St atus Register—MB AR + 0x0224 This register contains cont rol and status bits of the CDM PLL lock detect module.
CDM Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 5-21 5.5.11 PSC1 Mcloc k Config Register—MB AR + 0x0228 This register controls the gene ration of the Mclk for PSC1. Before modify the register value the divi der must be disabled.
MPC5200B Users Guide, Rev . 1 5-22 F reescale Semiconductor CDM Registers 5.5.12 PSC2 Mcloc k Config Register—MB AR + 0x022C This register controls the gene ration of the Mclock for PSC2. Before modify the register value the divider must be disabled.
CDM Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 5-23 5.5.14 PSC6 (IrD A) Mcloc k C onfig Register—MB AR + 0x0234 This register controls the gene ration of the Mclock for PSC6. Before modify the r egister value the divider must be disabled.
MPC5200B Users Guide, Rev . 1 5-24 F reescale Semiconductor CDM Registers.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 6-1 Chapter 6 e300 Pr ocessor Core 6.1 Overview The following sections are contained in this document: • MPC5200B e300 Processor Core Fu nctional Overview • e300 Core Reference Manual • Not supported e300 Core Features 6.
MPC5200B Users Guide, Rev . 1 6-2 F reescale Semiconductor e300 Core Reference Manual 6.3 e300 Core Reference Man ual A complete specification for the e300 core implementation used on the MPC5200B is obtained through a coll ection of documentatio n. • PowerPC MicroprocessorFamily: The Programming Envir onments for 32-bit Mi croprocessors, Rev .
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-1 Chapter 7 System Integration Unit ( SIU ) 7.1 Overview The following sections are contained in this document: • Interrupt Control.
MPC5200B Users Guide, Rev . 1 7-2 F reescale Semiconductor Interrupt Controller Ta b l e 7 - 1 does not include machin e-check bus errors or transac tion handshaking. e300 core interrupt pins given in Section 7.2.1.1, Machine Check Pin—core_mcp through Section 7.
Interrupt Controller MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-3 Figure 7-1. Interr upt Sources and e300 core In terrupt Pins IRQ [ 0 : 3 ] Interrupt Requests IRQ [ 0 : 3 ] provides in.
MPC5200B Users Guide, Rev . 1 7-4 F reescale Semiconductor Interrupt Controller 7.2.2 Interface Description Figure 7-2. Interrupt Contr oller Routing Scheme 7.2.3 Programming Note Under specific conditions, the Interrupt C ontroller may not support nested interrupts.
Interrupt Controller MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-5 correct behavior , the e300 core always completes the core_int be fore treating the core _smi. In this case, the CPU does not auth orize nested interrupt at the exception if the ISR set the 603e’ s MSR[ EE] to support nested interrupt (core_smi a nd core_int).
MPC5200B Users Guide, Rev . 1 7-6 F reescale Semiconductor Interrupt Controller Bit s Name Description — P er_mask Bits 0 : 23—T o mask/a ccept individual per ipheral interrup t sources. This masking is in addition to interrupt en ab les, which may exist in each source module.
Interrupt Controller MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-7 7.2.4.2 ICTL P eripheral Priority and HI / LO Select 1 Re gister —MBAR + 0x0504 T able 7-5.
MPC5200B Users Guide, Rev . 1 7-8 F reescale Semiconductor Interrupt Controller 7.2.4.3 ICTL P eripheral Priority and HI / LO Select 2 Re gister —MBAR + 0x0508 7.2.4.4 ICTL P eripheral Priority and HI / LO Select 3 Re gister —MBAR + 0x050C T able 7-6.
Interrupt Controller MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-9 7.2.4.5 ICTL External Enabl e and External T ypes Register —MB AR + 0x0510 8 : 1 1 P er1 8_pri P eriph eral 18 = CAN2.
MPC5200B Users Guide, Rev . 1 7-10 F reescale Semiconductor Interrupt Controller 7.2.4.6 ICTL Critical Priority and Main Interrupt Ma sk Register—MBAR + 0x0514 — EENA [ x ] Individual e nab le bits f or each IRQ input pin. Setting the associated bit lets th e related IRQ pin generate interr upts.
Interrupt Controller MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-11 — Main_Mask [ x ] T o mask / accept ind ividual main interrupt sources (as opposed to peripheral or critical interrupt sources). This masking is in addition to interrupt e nab les, which may e xist in each source module.
MPC5200B Users Guide, Rev . 1 7-12 F reescale Semiconductor Interrupt Controller 7.2.4.7 ICTL Main Interrupt Priority and INT / SMI Select 1 Register —MB AR + 0x0518 T able 7-10.
Interrupt Controller MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-13 7.2.4.8 ICTL Main Interrupt Priority and INT / SMI Select 2 Register—MB AR + 0x051 C T able 7-11.
MPC5200B Users Guide, Rev . 1 7-14 F reescale Semiconductor Interrupt Controller 7.2.4.9 ICTL P erstat, MainStat, MainStat, CritSta t Encoded Register—MBAR + 0x0524 T able 7-12.
Interrupt Controller MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-15 7.2.4.10 ICTL Critical Interrupt Stat us All Register—MBAR + 0x0528 21:23 CSe Critical Status Encoded—makes a singular i ndication of the current critical interr upt ( 3 bits indicating 1 of 4 possible interrupts ).
MPC5200B Users Guide, Rev . 1 7-16 F reescale Semiconductor Interrupt Controller 7.2.4.11 ICTL Main Interrupt Status All Register—MB A R + 0x052C Bit s Name Description 0:3 — R e s e r v e d — CSa [ x ] Critical Interrupt Status All—Indicates all pendi ng interrupts, including the currently activ e interrupt ( if any ).
Interrupt Controller MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-17 7.2.4.12 ICTL P eripheral Interrupt Status All Register—MB AR + 0x0530 23 MSa8 GPIO Wak eUp in terrupt 24 MSa9 TMR0 .
MPC5200B Users Guide, Rev . 1 7-18 F reescale Semiconductor Interrupt Controller 7.2.4.13 ICTL P eripheral Interrupt Status All Register—MB AR + 0x0538 16 PSa6 USB 17 PSa7 A T A 18 PSa8 PCI Control .
Interrupt Controller MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-19 7.2.4.14 ICTL Main Interrupt Em ulation All Register—MB AR + 0x0540 T able 7-17.
MPC5200B Users Guide, Rev . 1 7-20 F reescale Semiconductor Interrupt Controller 7.2.4.15 ICTL P eripheral Interrupt Em ulation All Register—MB AR + 0x0544 T able 7-18.
Interrupt Controller MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-21 7.2.4.16 ICTL IRQ Interrupt Em ulation All Register—MB AR + 0x0548 27 PEa17 CAN1 28 PEa18 CAN2 29:30 — Reser v ed 31 PEa21 XLB Arbiter T able 7-19.
MPC5200B Users Guide, Rev . 1 7-22 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) 7.3 General Purpose I / O ( GPIO ) There are a total of 56 possible GPIO pins on the MPC5200B. V irtua lly all of these pins are shared with alternate hardware func tions.
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-23 PSC1_0 UAR T1 / A C971 / CODEC1 No No PSC1_1 UAR T1 / A C971 / CODEC1 No No PSC1_2 U ART1 / AC971 N o N o PS.
MPC5200B Users Guide, Rev . 1 7-24 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) GPIO_ETHI_2 Ethernet No No GPIO_ETHI_3 Ethernet No No GPIO_SINT_4 ( ETH ) Ether net / USB2/J1850 Y.
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-25 7.3.1 GPIO Pin Multiplexing Figure 7-3 shows the GPIO / Generic MUX cell.
MPC5200B Users Guide, Rev . 1 7-26 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) 7.3.1.1 PSC1 ( U ART1 / A C97 / CODEC1 ) The PSC1 port has 5 pins with hardware support for: • C.
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-27 Full Ethernet consumes a ll 18 pins, unless the optional MDIO a nd MDC pins are specified as unused . In this case, 2 Output Only GPIO are available. Meanwhile, there are other cases becasue many pins can be used for UAR T , J1850.
MPC5200B Users Guide, Rev . 1 7-28 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) • T imer pins 6 and 7 are de dicated as T imer GPIO and have no alternate function. Although the T imer as GPIO only operates to the Simple GPIO lev el, Inte rrupt capability can be achi eved by configuring the Time r for Input Capture mode.
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-29 7.3.2.1.1 G PS P ort C onfiguration Register — MBAR + 0x0B00 T able 7-21.
MPC5200B Users Guide, Rev . 1 7-30 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) 9 : 1 1 IR D A Infrared Data Associati on 000 = Al l IrD A pins are GPIOs 001 = Reserved 010 = Res.
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-31 7.3.2.1.2 G PS Simple GPIO Enab les Register — MBAR + 0x0B04 20 : 23 PSC3 Programmab le Ser ial Controller.
MPC5200B Users Guide, Rev . 1 7-32 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) R Reserve d IRDA ETHR Rese rved USB W 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb R Reser .
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-33 7.3.2.1.3 G PS Simple GPIO Open Dr ain T ype Register —MBAR + 0x0B08 24 : 27 PSC2 Individual enable bits f or the 4 Simple GPIO on PSC2 por t.
MPC5200B Users Guide, Rev . 1 7-34 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) 7.3.2.1.4 G PS Simple GPIO Data Direction Regist er—MBAR + 0x0B0C 12 : 1 5 USB Indivi dual bits to cause open drain em ulation f or pins configured as GPIO outpu t.
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-35 Bit Name Description 0:1 — R e s e r v e d 2 : 3 IRD A Individual bits to control directionality of the pin as GPIO .
MPC5200B Users Guide, Rev . 1 7-36 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) 24 : 27 PSC2 Individual bits to control directionali ty of the pin as GPIO .
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-37 7.3.2.1.5 G PS Simple GPIO Data Ou tput V alues Register —MB AR + 0x0B10 T able 7-25.
MPC5200B Users Guide, Rev . 1 7-38 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) 7.3.2.1.6 G PS Simple GPIO Data I nput V alues Register —MB AR + 0x0B14 24 : 2 7 PSC2 Individual bits to control the st ate of pins config ur ed as GPIO output.
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-39 7.3.2.1.7 G PS GPIO Output-Onl y Enables Register —MB AR + 0x0B18 12 : 15 USB Indivi dual status bits reflecting the state of correspond ing GPIO pins.
MPC5200B Users Guide, Rev . 1 7-40 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) 7.3.2.1.8 G PS GPIO Output -Onl y Da ta V alue Out R egister —MB AR + 0x0B1C Bit Name Description 0 : 7 ETHR Individual bits to enable each Output On ly GPIO pin—all re side on the Ether net por t.
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-41 7.3.2.1.9 G PS GPIO Simple Interrupt Enable Register—MB AR + 0x0B20 Bit Name Description 0 : 7 ETH R Individual bits to control the st ate of enabled Output Only GPIO pins .
MPC5200B Users Guide, Rev . 1 7-42 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) 7.3.2.1.10 GPS GPIO Simple Interrupt Open-Drain Em ulatio n Register —MBAR + 0x0B24 Bit Name Description 0 : 7 SIGPIOE Individual bits to enable each Interrupt GPIO pin (pins are scattered).
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-43 7.3.2.1.11 GPS GPIO Simple Interrupt Da ta Direction Register —MBAR + 0x0B28 7.3.2.1.12 GPS GPIO Simple Interrupt Data V alue Out Register —MBAR + 0x0B2C T able 7-3 1.
MPC5200B Users Guide, Rev . 1 7-44 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) 7.3.2.1.13 GPS GPIO Simple Interrupt In terrupt Enable Regi ster —MB AR + 0x0B30 Bit Name Description 0 : 7 SID V O Individual bits to control the st ate of pins configur ed as GPIO output.
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-45 7.3.2.1.14 GPS GPIO Simple Interrupt Interrupt T ypes Regist er —MB AR + 0x0B34 7.3.2.1.15 GPS GPIO Simple Interrupt Ma ster Enable Register —MB AR + 0x0B38 T able 7-34.
MPC5200B Users Guide, Rev . 1 7-46 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) 7.3.2.1.16 GPS GPIO Simple Interr upt Status Register—MB AR + 0x0B3C Bit Name Description 0:2 — R e s e r v e d 3 ME GPIO Simple Interrupt Master Enable pin—This pin must be high befo re any Simple Interrupt pin can generate an interr upt.
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-47 7.3.2.2 W akeUp GPIO Register s—MBAR + 0x0C00 The W akeUp GPIO Register Set provides GPIO control for the 8 W akeUp GPIO pins. Thes e pins are scattered throughout the pin grou ps, but are all controlled in thi s module.
MPC5200B Users Guide, Rev . 1 7-48 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) 7.3.2.2.2 G PW W akeUp GPIO Open Drain Em ulation Register —MB AR + 0x0C04 7.3.2.2.3 G PW W akeUp GPIO Data Direction Regist er—MB AR + 0x0C08 T able 7-38.
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-49 7.3.2.2.4 G PW W akeUp GP IO Data V alue Out Register —MBAR + 0x0C0C Bit Name Description 0 : 7 WDDR [ 7 : 0 ] Individual bits to co ntrol directionality of the pin as GPIO .
MPC5200B Users Guide, Rev . 1 7-50 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) 7.3.2.2.5 G PW W akeUp GPIO Interr upt Enab le Register—MBAR + 0x0C10 7.3.2.2.6 G PW W akeUp GPIO Individual Interrupt Enable Register —MB AR + 0x0C14 T able 7-41.
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-51 7.3.2.2.7 G PW W akeUp GPIO Inte rrupt T ypes Register—MBAR + 0x0C18 Bit Name Description 0 : 7 WINe Individual bits to enable generation of Simple interru pt f or W akeUp GPIO configured as input.
MPC5200B Users Guide, Rev . 1 7-52 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) 7.3.2.2.8 G PW W akeUp GPIO Master Enab les Register —MB AR + 0x0C1C Bit Name Description 0 : 1 .
General Purpose I / O ( GPIO ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-53 7.3.2.2.9 G PW W akeUp GP IO Data Input V alues Register —MB AR + 0x0C20 Bit Name Description 0:6 — R e s e r v e d 7 ME W akeUp GPIO Master Enab le p in. This pin must be high before any W ak eUp GPIO pi n can generate an interr upt.
MPC5200B Users Guide, Rev . 1 7-54 F reescale Semiconductor G e n e r a l P u r p o s e I/O (G P I O) 7.3.2.2.10 GPW W akeUp GPIO Status Register—MB AR + 0x0C24 T able 7-46 .
General Purpose Timers ( GPT ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-55 7.4 General Purpose Timers ( GPT ) Eight ( 8 ) General-Purpose Timer ( G P T ) pins are configurable for: .
MPC5200B Users Guide, Rev . 1 7-56 F reescale Semiconductor General Purpose Timer s ( GPT ) 7.4.4 GPT Registers—MB AR + 0x0600 Each GP T uses 4 32-bit registers. These re gisters are located at an offset from MBAR of 0x0600. Register addresses are relative to this offset.
General Purpose Timers ( GPT ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-57 Bit Name Description 0 : 7 OC PW Output Compa re Pulse Width—Applies to OC Pulse types only . Th is field specifies the number of IP b us clocks ( non-prescaled ) to create a short ou tput pulse at each Output Event.
MPC5200B Users Guide, Rev . 1 7-58 F reescale Semiconductor General Purpose Timer s ( GPT ) 21 Stop_Cont Stop Continuous—Applies to multiple modes, as f ollows: 0 = Stop 1 = Continuous •I C m o d e Stop operation—At each IC e vent, counter is reset.
General Purpose Timers ( GPT ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-59 7.4.4.2 GPT 0 Counter Input Register—MB AR + 0x0604 GPT 1 Counter Input Register—MB AR + 0x0614 GPT 2 Co.
MPC5200B Users Guide, Rev . 1 7-60 F reescale Semiconductor General Purpose Timer s ( GPT ) 7.4.4.3 GPT 0 PWM Configuration Register—MB AR + 0x0608 GPT 1 PWM Configuration Register—MB AR + 0x0618 .
General Purpose Timers ( GPT ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-61 7.4.4.4 GPT 0 Status Register—MB AR + 0x060C GPT 1 Status Register—MB AR + 0x061C GPT 2 Status Register.
MPC5200B Users Guide, Rev . 1 7-62 F reescale Semiconductor Slice Timers 7.5 Slice Timers T wo Slice T imers are included to provide shorter term periodic interrupts. Each timer consists of a 24-bit counter with no prescale. Running off the IP bus clock, each timer can g enera te interrupts from 7.
Slice Timers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-63 7.5.1.1 SL T 0 T erminal Count Register—MB AR + 0x0700 SL T 1 T erminal Count Register—MB AR + 0x0710 7.5.1.2 SL T 0 Contr ol Register—MB AR + 0x0704 SL T 1 Contr ol Register—MB AR + 0x0714 T able 7-51.
MPC5200B Users Guide, Rev . 1 7-64 F reescale Semiconductor Slice Timers 7.5.1.3 SL T 0 Count V alue Register—MB AR + 0x0708 SL T 1 Count V alue Register—MB AR + 0x0718 Bit Name Description 0:4 — Reserved 5 Run_ W ait A high indicates the Time r should run co ntinuously while en ab led.
Real-Time Clock MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-65 7.5.1.4 SL T 0 Timer Status Register—MB AR + 0x070C SL T 1 Timer Status Reg ister—MBAR + 0x071C 7.
MPC5200B Users Guide, Rev . 1 7-66 F reescale Semiconductor Real-Tim e Clock Periodic interrupts are separately enabled by control bits, and a global enable must be asserted to allow any of the periodic s ources to generate a CPU interrupt. Clearing Pe riodic interrupts is ac complished by writ ing 1 to the appropriate status bit.
Real-Time Clock MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-67 7.6.3.1 RTC Time Set Registe r—MBAR + 0x0800 • R TC New Y ear and Stopwatch Register (0x0808) • R TC Periodic Interru.
MPC5200B Users Guide, Rev . 1 7-68 F reescale Semiconductor Real-Tim e Clock 7.6.3.2 RTC Date Set Register—MB AR + 0x0804 18 : 23 Minute_set Minute written in R TC after successful state machine transition by set_time and pause_ti me bits.
Real-Time Clock MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-69 7.6.3.3 RTC Ne w Y ear and Stopwatch Register—MB AR + 0x0808 7.6.3.4 RTC Alarm and Interrupt Enable Register—MB AR + 0x080C T able 7-58.
MPC5200B Users Guide, Rev . 1 7-70 F reescale Semiconductor Real-Tim e Clock 7.6.3.5 RTC Curre nt Time Register—MB AR + 0x0810 This is a read-only register . 8:10 — Reser v ed 11:15 Alm_24Hset Hour setting (in 24 hour f or mat) to be co mpared to time of day f or the pur pose of generating Alar m Status/Interrupt.
Real-Time Clock MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-71 7.6.3.6 RTC Current Date Regis ter—MBAR + 0x0814 This is a read-only register . 7.6.3.7 RTC Alarm and Stopwa tch Interrupt Register—MB AR + 0x0818 This is a read-only register .
MPC5200B Users Guide, Rev . 1 7-72 F reescale Semiconductor Real-Tim e Clock 7.6.3.8 RTC P eriodic Interrupt and Bus Err or Register—MB AR + 0x081C This is a read-only register . Bit s Name Description 0:6 — R e s e r v e d 7 Int_alm Status bit in dicating that enab le d once-a-da y Alar m has occurred (activ e high).
Real-Time Clock MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 7-73 7.6.3.9 RTC T est Register/Divides Register—MB AR + 0x0820 This register is used during manufactu ring test to expedite R TC testing and is not in tended to be a user register .
MPC5200B Users Guide, Rev . 1 7-74 F reescale Semiconductor Real-Tim e Clock.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-1 Chapter 8 SDRAM Memory Controller 8.1 Overview The following sections are contained in this document: • Section 8.2, T erminology and Notation • Section 8.3, Featur es — Section 8.
MPC5200B Users Guide, Rev . 1 8-2 F reescale Semiconductor Features stripped along the way). Nor is the transpor tation of data an executio n context. W ithout knowledge of atom boundaries and signi f.
Features MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-3 — 2 bits of bank address (BA[1:0]) NO TE In this document the Auto Precharge control si gnal (A10 usually), conveye d on the memory address bus along with column address, is never included in the stated CA width; it is always in addition to the CA width.
MPC5200B Users Guide, Rev . 1 8-4 F reescale Semiconductor Features T able 8-1. 32-Bit External Data Wid th Legal Memory Configurations Row Bits Column Bits Ba nk Bits Spaces (CS ) Physical Address Ra.
Features MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-5 12 13 12 11 2 2 1 4 x 512Mb 16M x 4bank x 8bit 256MB 2 x 1Gb 16M x 4bank x 16bit 1 x 2Gb 16M x 4bank x 32bit 2 4 x 1Gb 16M x 4bank .
MPC5200B Users Guide, Rev . 1 8-6 F reescale Semiconductor Features 12 8 2 1 2 x 64Mb 1M x 4bank x 16bit 144MB + 12 13 11 10 2 1 2 x 512Mb 8M x 4bank x 16bit 12 8 2 1 2 x 64Mb 1M x 4bank x 16bit 272MB.
Features MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-7 13 8 2 1 2 x 128Mb 2M x 4bank x 16bit 160MB + 13 10 2 1 2 x 512Mb 8M x 4bank x 16bit 12 9 2 1 2 x 128Mb 2M x 4bank x 16bit 288MB + .
MPC5200B Users Guide, Rev . 1 8-8 F reescale Semiconductor Features 12 10 2 1 2 x256Mb 4M x 4bank x 16bit 192MB + 12 11 2 1 2 x 512Mb 8M x 4bank x 16bit 13 9 2 1 2 x256Mb 4M x 4bank x 16bit 192MB + 13.
Features MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-9 13 9 2 1 2 x 512Mb 8M x 4bank x 32bit 384MB + 13 11 2 1 2 x 1Gb 16M x 4bank x 32bit 12 11 2 1 1 x 1Gb 8M x 4bank x 32bit 384MB + 12 12 2 1 1 x 2Gb 16M x 4bank x 32bit 13 10 2 1 1 x 1Gb 8M x 4bank x 32bit 384MB + 13 11 2 1 1 x 2Gb 16M x 4bank x 32bit T able 8-2.
MPC5200B Users Guide, Rev . 1 8-10 F reescale Semiconductor Features 13 10 2 1 2 x 256Mb 8M x 4bank x 8bit 64MB 1 x 512Mb 8M x 4bank x 16bit 2 4 x 256Mb 8M x 4bank x 8bit 128MB 2 x 512Mb 8M x 4bank x .
Features MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-11 12 9 2 1 2 x 64Mb 2M x 4bank x 8bit 144MB + 13 11 2 1 1 x 1Gb 16M x 4bank x 16bit 12 9 2 1 1 x 128Mb 2M x 4bank x 16bit 48MB + 13 .
MPC5200B Users Guide, Rev . 1 8-12 F reescale Semiconductor Features 12 10 2 1 2 x 128Mb 4M x 4bank x 8bit 160MB + 13 11 2 1 2 x 256Mb 16M x 4bank x 8bit 12 10 2 1 2 x 128Mb 4M x 4bank x 8bit 160MB + .
Features MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-13 13 11 2 1 2 x 512Mb 16M x 4bank x 8bit 256MB + 13 11 2 1 1 x 1Gb 16M x 4bank x 16bit T able 8-2.
MPC5200B Users Guide, Rev . 1 8-14 F reescale Semiconductor Features Figure 8-1 shows an example memory co nfiguration of 1 space (CS) of 4 devices of 128Mbit (4M x 4 ba nks x 8bit) DDR SDRAM, for a total memory size of 64MB. Figure 8-1. Bloc k Diagram—SDRAM Subsyste m Example Both chip select s contribute together to access the whole m emory .
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-15 8.4 Functional Description 8.4.1 External Si gnals (SDRAM Side) T able 8-3. SDRAM External Signals Signal Name Description Outputs MEM_CLK Memory Clo c k (frequency is the same as the internal XL bus clock).
MPC5200B Users Guide, Rev . 1 8-16 F reescale Semiconductor Functional Des cription 8.4.2 Bloc k Diagram Figure 8-2 shows the SDRAM MC block diagra m. It is important to notice: • the internal XL bu.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-17 modulo 8 boundary within the modulo 32 range; the address “wraps” from the highest addres s to the lowest address of the range i f the startin g address is not aligned at the beginning of the range.
MPC5200B Users Guide, Rev . 1 8-18 F reescale Semiconductor Functional Des cription Some of the configuration parameters requi red by the memory are also needed by the Me mory Contro ller for command generation.
Operation MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-19 W ith both SDR and DDR memory , a Read comman d can be issued overlapping the masked beat s at the end of a previous Single W rite o f the same CS ; the Read command aborts the rema ining (unnecessary) Write beats.
MPC5200B Users Guide, Rev . 1 8-20 F reescale Semiconductor Programming the SDRAM Controller If all the memory and controller regi ster values have been precalculate d and stored in ROM, skip step 3 and go directly to step 4 . Otherwise, continue with step 3 .
Memory Controller Registers (MB AR+0x0100:0x010C) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-21 T able 8-5. Memory Controller Mode Register m s b 0 1 23456789 1 0 1 1 1 2 1 3 1 41 5 R R.
MPC5200B Users Guide, Rev . 1 8-22 F reescale Semiconductor Memory Controller Registers (MB AR+0x0100:0 x010C) 8.7.2 Control Regi ster—MB AR + 0x0104 The 32-bit read/write Contr ol register controls specific operatio ns and generates some SDRAM comm ands.
Memory Controller Registers (MB AR+0x0100:0x010C) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-23 The Ta b l e 8 - 7 indicates how the internal address bits XLA[4:7] are mult iplexed internally to s upport higher column or row address bits.
MPC5200B Users Guide, Rev . 1 8-24 F reescale Semiconductor Memory Controller Registers (MB AR+0x0100:0 x010C) T able 8-8. 32-B it SDRAM Address Multiplexing De vice Structure Row bits × Col bits × .
Memory Controller Registers (MB AR+0x0100:0x010C) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-25 8.7.3 Configuration R egister 1—MB AR + 0x0108 The 32-bit read/write Configuration register 1 stores delay valu es necessary between specific SDRAM commands.
MPC5200B Users Guide, Rev . 1 8-26 F reescale Semiconductor Memory Controller Registers (MB AR+0x0100:0 x010C) MEM_CLK2—double frequency of MEM_CLK—DDR uses both edges of the bus-frequenc y clock (MEM_CLK) to read/write data.
Memory Controller Registers (MB AR+0x0100:0x010C) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-27 8.7.4 Configuration R egister 2—MB AR + 0x010C The 32-bit read/write Configuration register 2 stores delay valu es necessary between specific SDRAM commands.
MPC5200B Users Guide, Rev . 1 8-28 F reescale Semiconductor Memory Controller Registers (MB AR+0x0100:0 x010C) Bit Name Description 0:3 brd2rp Burst Read to Read/Precharge delay .
Memory Controller Registers (MB AR+0x0100:0x010C) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-29 The Figure 8-3. Programmable Command T imings shows the timings which can be program med by the two Controller Configuration Register . The timing diagra m uses the suggested valu es for a DDR memory and a 132 MHz memory clock.
MPC5200B Users Guide, Rev . 1 8-30 F reescale Semiconductor Address Bus Mapping 8.8 Address Bus Mapping Figure 8-4. Addres s Bus Mapping (3 2-Bit Exter nal Data Width) The Memory Controller extracts the Column Address from t he XL bus address. The Column Address is p resented on the MPC5200B MEM_MA[12:0] pins during SDRAM Read and Write commands.
Address Bus Mapping MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 8-31 Figure 8-5. Addres s Bus Mapping (1 6-Bit Exter nal Data Width) 8.8.1 Example—Ph ysical Address Multiplexing The mapping of XL address bus to memory address bus is shown in Figure 8-4 .
MPC5200B Users Guide, Rev . 1 8-32 F reescale Semiconductor Address Bus Mapping By default, the Memor y Controller onl y provides 12 row address bits and 12 co lumn address bits. T o enab le the 13 th row address bit, the hi_addr bit of the Control regist er must be set to 1 (MBAR+0x0104, Control[7]).
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-1 Chapter 9 LocalPlus Bus (External Bus Interface) 9.1 Overview The LocalPlus Bus is the external bus inte rface of the MPC5200B. This multi-function bus system supports in terfacing to externa l Boot ROM or Flash memories, e xternal SRAM memori es or other memory mapped devices.
MPC5200B Users Guide, Rev . 1 9-2 F reescale Semiconductor Interface – (Address 8, 16, 24 or 25 bits, Da ta 8,16 or 32 bi ts, 2 Bank Select s) • 8 Chip Select (CS) signals — Programmable W ait S.
Interface MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-3 9.3.2 Bloc k Diagram The block diagram of the LocalPlus Controller (LPC) is shown in Figure 9-1. This diagram shows the non-mu ltiplexed implementation of address and data lines. The LPC is driven by the internal IP bus cl ock and the PCI_CLOCK.
MPC5200B Users Guide, Rev . 1 9-4 F reescale Semiconductor Modes of Operation Figure 9-2. Muxed Mode Ad dress Latching 9.4 Modes of Operation There are 2 primary modes of operation: • MUXed • non-MUXed (Legacy , Lar ge Flash, Most /Graphic modes, Burst and Non-Burst) W ithin each mode, there is considerable flexibility to control the operation.
Modes of Operation MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-5 NO TE The 24-bit data width is not supported. The total pin number requires also the addition of the control signals CS, R/W , ACK , OE , TS (MOST/Graphis and Large Flash mode) and TS IZ (MOST/ Graphics mode) where avail able.
MPC5200B Users Guide, Rev . 1 9-6 F reescale Semiconductor Modes of Operation Figure 9-4. Timing Diagr am—Non-MUXed Mode Figure 9-5. Timing Diagram—Bu rst Mode ADDR DATA ( rd ) CS [x ] R/W D A T A (w r) OE TS TSIZ[1:2] ACK Valid Address Valid write Dat a Valid read Da ta NOTE: 1.
Modes of Operation MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-7 In this mode, the per ipheral address and data lines are li mited to a total of 32 in Legacy Modes, to 40 or 48 in Lar ge Flash or to 56 in MOST Graphics mode. They are driven/read simult aneous ly on the external AD bus.
MPC5200B Users Guide, Rev . 1 9-8 F reescale Semiconductor Modes of Operation The MUXed mode requires exter nal logic to latch the address during the address tenure and to decode bank selects if they are en coded. This mode is slower than the non-MUXed mode be cause data and address are multiplexed in time.
Configuration MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-9 Figure 9-6 shows a MUXed transact ion type timing diagram. Figure 9-6. Timing Diagram—MUXed Mode 9.5 Configuration The LPC supports several opt ions in terms of modes, address and data sizes, speed, and confi guration which are described below .
MPC5200B Users Guide, Rev . 1 9-10 F reescale Semiconductor Configuration • The boot address/exception table ca n be located at 0x0000 0100 or 0xfff0 0100.
DMA (BestComm) Interface (SCLPC) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-11 • BootSwap Ta b l e 9 - 1 describes possible boot settings. 9.6 DMA (BestComm) Interface (SCLPC) The SCLPC interface provides a sepa rate path from BestComm directly (on CommBus) to any peripheral.
MPC5200B Users Guide, Rev . 1 9-12 F reescale Semiconductor Programmer’ s Model • Section 9-10, Chip Select Status Register (0x031C) • Section 9-1 1, Chip Select Burst Contr ol Re gister (0x0328.
Prog rammer’ s Mode l MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-13 9.7.1.1 Chip Select 0/Boot Configuration Register—MB AR + 0x0300 T able 9-7.
MPC5200B Users Guide, Rev . 1 9-14 F reescale Semiconductor Programmer’ s Model 20 : 21 AS Address Size field—defines size of peripheral Address bus (in b ytes) and must be consistent with physical connections . 00 = 8 bi ts 01 = 16 bits 10 = 24 bits 11 = > 25 bits See documentation for Ph ysical Connection requireme nts.
Prog rammer’ s Mode l MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-15 9.7.1.2 Chip Select 1 Configuration Register—MB AR + 0x0304 Chip Select 2 Configuration Register—MB AR + 0x0308.
MPC5200B Users Guide, Rev . 1 9-16 F reescale Semiconductor Programmer’ s Model 16 MX MX bit specifies whether transaction operates as multiplex ed or non-multiple xed. A multiple xed transaction presents address an d data in different tenures . Du ring the address tenure, ALE is a sser ted.
Prog rammer’ s Mode l MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-17 9.7.1.3 Chip Select Contr ol Register—MBAR + 0x0318 28 WS Wri te Sw ap bit—If high, Endian b yte swapping occurs during writes to a per ipheral. • F or 8-bit per ipherals, this bit has no eff ect.
MPC5200B Users Guide, Rev . 1 9-18 F reescale Semiconductor Programmer’ s Model 9.7.1.4 Chip Select Status Register—MBAR + 0x031C 9.7.1.5 Chip Select Burst Control Register—MBAR + 0x0328 Bit s Name Description 0:6 — R e s e r v e d 7 ME Maste r Enab le bit—a gl obal module enable bit.
Prog rammer’ s Mode l MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-19 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb R CW3 SLB3 Rsvd BRE3 CW2 SLB2 Rsvd BRE2 CW1 SLB1 Rsvd BRE1 CW0 .
MPC5200B Users Guide, Rev . 1 9-20 F reescale Semiconductor Programmer’ s Model 13 SLB4 Chi p Select 4 Shor t/Long Burst, 0 for Shor t Burst only , 1 for Long Burst capable. Short burst is 8-bytes , used for Instruction f etche s , and CDWF cache line b ursts on XLB if cache wrap not capable.
Prog rammer’ s Mode l MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-21 9.7.1.6 Chip Select Deadcyc le Control Register—MB AR + 0x032C 28 CW0 Chip Sel ect 0 Cache Wrap capable , set i f peripheral burst can perform PPC cache wrap. This bit setting only applies in Large Flash or MOST Graphics Mode.
MPC5200B Users Guide, Rev . 1 9-22 F reescale Semiconductor Programmer’ s Model NO TE Deadcycle counter is only used, if no arbitration to an other module (A T A or PCI) of the shared local bus happens. If an arbitration happ ens the bus can be dirven within 4 IPB clocks by an other module.
Prog rammer’ s Mode l MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-23 9.7.2 SCLPC Registers—MB AR + 0x3C00 There are 6 32-bit BestComm Registers for the LocalPlus (SCLPC). These registers are lo cated at an offset from MBAR of 0x3C00.
MPC5200B Users Guide, Rev . 1 9-24 F reescale Semiconductor Programmer’ s Model 9.7.2.2 SCLPC Star t Address Register—MB A R + 0x3C04 9.7.2.3 SCLPC Control Register—MB AR + 0x3C08 T able 9-14.
Prog rammer’ s Mode l MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-25 9.7.2.4 SCLPC Enable Register—MB AR + 0x3C0C 16:22 — Reser v ed 23 DAI Disable A uto Increment. Nor mally , SCLPC and LPC will present seque ntial incrementing addresses to the p eripheral as the Pac ket proceeds.
LocalPlus Bus (External Bus Interface) Notes MPC5200B Users Guide, Rev . 1 9-26 F reescale Semiconductor 9.7.2.5 SCLPC Bytes Done Status Register—MB AR + 0x3C14 Note: X: Bit does not reset to a defined value . 22 AIE Abor t Interrupt Enable. If set, and a fifo error occurs during pac ket transmission, a cpu interrupt from SCLPC will be generated.
Prog rammer’ s Mode l MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-27 7 NT Nor mal T er mination. This bit is set to 1 whene ver a complete P ack et has been transf erred successfully . Note: This bit is ANDed with the NIE bit above to generate a single CPU interrupt signal to the core.
MPC5200B Users Guide, Rev . 1 9-28 F reescale Semiconductor Programmer’ s Model 9.7.3 SCLPC FIFO Registers—MB AR + 0x3C40 LPC uses a single FIFO that changes direc tio n based on the Rx / Tx mode. Software contro ls direction change and flushes FIFO befo re changing directions.
Prog rammer’ s Mode l MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-29 9.7.3.2 LPC Rx / Tx FIFO Status Register—MB AR + 0x3C44 Bit s Name Description 0 : 31 FIFO_Data_Word The FIFO data por t. Reading from this location “pops” data from the FIFO , wr iting “pushes” data into the FIFO.
MPC5200B Users Guide, Rev . 1 9-30 F reescale Semiconductor Programmer’ s Model 9.7.3.3 LPC Rx / Tx FIFO Contr ol Register—MBAR + 0x3 C48 9.7.3.4 LPC Rx / Tx FIFO Alarm Register—MB AR + 0x3C4C T able 9-20.
Prog rammer’ s Mode l MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 9-31 9.7.3.5 LPC Rx / Tx FIFO Read P ointer Register—MB AR + 0x3C50 9.
LocalPlus Bus (External Bus Interface) Notes MPC5200B Users Guide, Rev . 1 9-32 F reescale Semiconductor.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-1 Chapter 10 PCI Contr oller 10.1 Overview The Peripheral Component Interface ( P CI ) Bus is a high-performance bus with multiplexed address and data lines. It is especiall y suitable for high data-rate applications.
MPC5200B Users Guide, Rev . 1 10-2 F reescale Semiconductor PCI External Signals 10.1.2 Bloc k Diagram Figure 10- 1. PCI Block Diagram 10.2 PCI External Sig nals T able 10-1. PCI External Signals Signal I/O Definition AD[31:0] I / O Multipl e xed Address and Data Bus ( Shared with A T A and LPC ).
PCI External Signals MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-3 For detailed description of the PCI bus signals, see the PCI Local Bus Specification, Revision 2.2 . 10.2.1 PCI_AD[31:0] - Address/Data Bus The PCI_AD[31:0] lines are a tim e multiplexe d address data bus.
MPC5200B Users Guide, Rev . 1 10-4 F reescale Semiconductor Registers 10.3 Registers MPC5200B has several sets of registers that control and report status for the differ ent interfac es to the PCI controller: PCI T ype 0 Configuration Space Registers, Ge neral Status/Control Registers, and C ommunication Sub-System Inte rface Registers.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-5 0x74 PCIIW1BT AR Initiator Window 1 Base/T ranslation Address Register 0x78 PCIIW2BT AR Initiator Window 2 Base/T ranslation Add.
MPC5200B Users Guide, Rev . 1 10-6 F reescale Semiconductor Registers 10.3.1 PCI Controller T y pe 0 Configuration Space MPC5200B supplies a type 0 PCI Configura tion Space header . These register s are accessible as an offset from MBAR ( Sec tion 3.2, Internal Register Memor y Map ) or through externally mastered PCI Configuration Cycles.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-7 PCI Dword Reserved space (0x10 - 0x3F) can be accessed only from an ex ternal PCI Con fi guration access. NO TE A PCI Double W ord (DWORD) is a 32 bit long word . A Po werPC Double W ord is instead a 64 bit word (according to the EABI rule) while a W ord is a 32 bit value.
MPC5200B Users Guide, Rev . 1 10-8 F reescale Semiconductor Registers 10.3.1.2 Status/Command Registers PCISCR(R/R W/R WC) —MB AR + 0x0D04 Bits 31-27 and 24 are read -write-clear (R WC).
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-9 9 Reser v ed (R) Fixed to 0. Prior to the 2.2 PCI Spec, this was the UDF (User Defined Features) Suppor ted bit. 1 = Suppo r ted User Defined F eature s 0 = Does not suppor t UDF 10 66 MHz Capable (66M) Fixed to 1.
MPC5200B Users Guide, Rev . 1 10-10 F reescale Semiconductor Registers 10.3.1.3 Revision ID/ Class Code Re gisters PCICCRIR(R ) —MB AR + 0x0D08 10.3.1.4 Configuration 1 Register PCICR1 (R/R W) —MBAR + 0x0D0C 30 Memory Access Control (M) This bit controls the PCI controller’ s response to Memor y Space accesses.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-11 10.3.1.5 Base Address Regi ster 0 PCIBAR0(R W) —MB AR + 0x0D10 Bit s Name Description 0:7 Built-In Self Te s t (BIST) Fixed to 0x00. The PCI controller does not im plement the Built-In Self T est register .
MPC5200B Users Guide, Rev . 1 10-12 F reescale Semiconductor Registers 10.3.1.6 Base Address Regi ster 1 PCIBAR1(R W) —MB AR + 0x0D14 10.3.1.7 CardBus CIS P ointer Register PCICCPR(R W) —MB AR + 0x0D28 This optional register contains the pointer to the Card Inform ation S tructure (CIS) for the CardBus card.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-13 10.3.1.10 Capabilities P ointer (Cap_Ptr) PCICPR(R)—MBAR + 0x0D34 Not implemented. Fixed to 0x00000000. 10.3.1.11 Configuration 2 Register PCICR2 (R/R W) —MB AR + 0x0D3C 10.3.
MPC5200B Users Guide, Rev . 1 10-14 F reescale Semiconductor Registers 16 1 7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb R Rsvd BME PEE SEE Reserv ed PR W RESET 0 00000000000000 1 Bit s Name Description 0 Reserved Unused bit. Software should write zero to this register .
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-15 20:30 Re served Unused bits. Software should write zero to this re gister . 31 PCI Reset (PR) This bit controls the external PCI RST . When this bit is cleared, the external PCI RST deasser ts.
MPC5200B Users Guide, Rev . 1 10-16 F reescale Semiconductor Registers 10.3.2.2 T arget Base Address T ranslation Register 0 PCITB A TR0(R W) —MBAR + 0x 0D64 10.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-17 10.3.2.4 T arget Control Register PCITCR(R W) —MB AR + 0x0D6C Bit s Name Description 0:1 Base Address T ranslati on 1 This base address regi ster corresponds to a hit on the BAR1 in MPC5200B PCI T ype 0 Configuration space register (PCI space) .
MPC5200B Users Guide, Rev . 1 10-18 F reescale Semiconductor Registers 10.3.2.5 Initiator Window 0 Base/T ranslation Address Register PCIIW0BT AR(R W)—MB AR + 0x0D70 23 Write Combine Disable (WCD) This control bit applies only when MPC5200 is T arget.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-19 10.3.2.6 Initiator Window 1 Base/T ranslation Address Register PCIIW1BT AR(R W) —MB AR + 0x0D74 16:23 Window 0 T ranslation A.
MPC5200B Users Guide, Rev . 1 10-20 F reescale Semiconductor Registers 10.3.2.7 Initiator Window 2 Base/T ranslation Address Register PCIIW2BT AR(R W) —MB AR + 0x0D78 10.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-21 10.3.2.9 Initiator Contr ol Register PCIICR(R W) —MBAR + 0x0D84 8:11 Reser ved Reser ved register . Write a zero to this register . 12:15 Window 1Control [3:0] Bit[3] - IO/M#. Bit[2:1] - PRC.
MPC5200B Users Guide, Rev . 1 10-22 F reescale Semiconductor Registers 10.3.2.10 Initiator Status Register PCIISR(R WC) —MB AR + 0x0D88 10.3.2.11 PCI Arbiter Register PCIARB(R W) —MB AR + 0x0D8C m.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-23 10.3.2.12 Configuration Address Regi ster PCICAR (R W) —MB AR + 0x0DF8 10.3.
MPC5200B Users Guide, Rev . 1 10-24 F reescale Semiconductor Registers 10.3.3.1.1 Tx P acket Size PCITPSR(R W) —MB AR + 0x3800 10.3.3.1.2 Tx Star t Address PCITSAR(R W) —MB AR + 0x3804 10.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-25 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb R Reser ved Max_Beats Rese rved W Reser v ed DI W RESET 0 00000000 0 0 0 00 0 0 Bit s Name Description 0:3 Reser v ed Unused. Software should wr ite zero to these bits.
MPC5200B Users Guide, Rev . 1 10-26 F reescale Semiconductor Registers 10.3.3.1.4 Tx Enables PCITER(R W)—MB AR + 0x380C m s b 0 12345678 9 1 0 1 1 1 2 1 3 1 4 1 5 RR C R F Rsvd CM BE Reserv ed ME Re.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-27 10.3.3.1.5 Tx Next Address PCITNAR(R) —MB AR + 0x3810 12 Retr y abor t Enable (RE) User writes this bit high to enable CPU Interr upt generation in the case of retry abo rt termin ation of a pack et transmission.
MPC5200B Users Guide, Rev . 1 10-28 F reescale Semiconductor Registers 10.3.3.1.6 Tx Last W ord PC ITL WR(R) —MB AR + 0x3814 10.3.3.1.7 Tx Bytes Done C ounts PCITDCR(R) —MB AR + 0x3818 10.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-29 10.3.3.1.9 Tx Status PCITS R(R WC) —MB AR + 0x381C 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb R P ackets_Done W RESE.
MPC5200B Users Guide, Rev . 1 10-30 F reescale Semiconductor Registers 10.3.3.1.10 Tx FIFO Data Regi ster PCITFDR(R W ) —MB AR + 0x3840 10 Bus Error type 1 (BE1) This flag is set whenev er a Slav e bus transaction attempts to read a Reserved register (an entire 32-bit register , not just a Re ser ved bit or byte).
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-31 10.3.3.1.11 Tx FIFO St atus Register PCITFSR( R/R WC) —MBAR + 0x3844 Bit s Name Description 0:31 FIFO_Data_Word This is the data por t to the FIFO. Reading from this l ocation will “pop” data from the FIFO , writing da ta will “push” data into the FIFO .
MPC5200B Users Guide, Rev . 1 10-32 F reescale Semiconductor Registers 10.3.3.1.12 Tx FIFO Contr ol R egister PCITFCR(RW ) —MBAR + 0x3848 10.3.3.1.13 Tx FIFO Alarm Regi ster PCITF AR(R W) —MB AR +.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb R Reser v ed Alar m A larm W RESET 0 00000000 0 0 0 00 0 0 Bit s Name Description 0:19 Reser v ed Unused. Software should wr ite zero to these bits.
MPC5200B Users Guide, Rev . 1 10-34 F reescale Semiconductor Registers 10.3.3.1.14 Tx FIFO Read P ointer Register PCITFRPR(R W) —MB AR + 0x3850 10.3.3.1.15 Tx FIFO Write P ointer Register PCI TFWPR(R W) —MB AR + 0x3854 This marks the end of the PCI Multi-Ch annel DMA T ransmit Interface description.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-35 10.3.3.2.1 Rx Pac ket Size PCIRPSR(R W) —MB AR + 0x3880 10.3.3.2.2 Rx Star t Address PCIRSAR (R W) —MB AR + 0x3884 10.
MPC5200B Users Guide, Rev . 1 10-36 F reescale Semiconductor Registers 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb R Reserve d FB R Max_Beats Reser v ed W Reser v ed DI W RESET 0 00000000 0 0 0 00 0 0 Bit s Name Description 0:3 Reser ve d Unused.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-37 10.3.3.2.4 Rx Enables PCI RER (R W) —MB AR + 0x388C m s b 0 12345678 9 1 0 1 1 1 2 1 3 1 4 1 5 RR C R F F E C M B E Reserve d.
MPC5200B Users Guide, Rev . 1 10-38 F reescale Semiconductor Registers 10.3.3.2.5 Rx Next Address PCIRNAR(R) —MBAR + 0x3890 10.3.3.2.6 Rx Last W or d PCIRL WR(R) —MB AR + 0x3 894 11 System error Enable (SE) User write s this bit high to enable CPU In terrupt generation in t he case of system error ter mination of a pack et transmission.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-39 10.3.3.2.7 Rx Bytes Done Count s PCIRDCR(R) —MB AR + 0x3898 10.3.3.2.8 Rx Pac kets Done Coun ts PCIRPDCR(R) —MB AR + 0x38A0.
MPC5200B Users Guide, Rev . 1 10-40 F reescale Semiconductor Registers 10.3.3.2.9 Rx Status PCIRS R (R/sw1) —MB AR + 0x389C Bit s Name Description 0:31 Pa ckets_Done This status registe r indicates the number of pack ets received. It is active on ly if continuous mode is in eff ect.
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-41 10.3.3.2.10 Rx FIFO Data Regi ster PCIRFDR(R W) —MB AR + 0x38C0 10.3.3.2.11 Rx FIFO Status Register PCIRFSR(R/sw1) —MB AR + 0x38C4 12 System Erro r (SE) This flag is set in response to the T ransmit Controller enter ing an illegal state.
MPC5200B Users Guide, Rev . 1 10-42 F reescale Semiconductor Registers 10.3.3.2.12 Rx FIFO Contro l Regi ster PCIRFCR(R W) —MB AR + 0x38C8 R Reser v ed RXW UF OF FR Full Alar m Empty W rwc rwc rwc 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb R Reser v ed W RESET 0 00000000 0 0 0 00 0 0 Bit s Name Description 0:8 Reser ved Unused byte .
Regist ers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-43 10.3.3.2.13 Rx FIFO Alarm Regi ster PCIRF AR(R W) —MB AR + 0x38CC Bit s Name Description 0:4 Reser v ed Unused.
MPC5200B Users Guide, Rev . 1 10-44 F reescale Semiconductor Functional Des cription 10.3.3.2.14 Rx FIFO Read P ointer R egister PCIRFRPR(R W) —MB AR + 0x38D0 10.3.3.2.15 Rx FIFO Write P ointer R egister PCIRFWPR (R W) —MB AR + 0x38D4 This marks the end of the PCI Multi-Channel DMA Rec eive Interface description.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-45 NO TE Only the internal PCI arbiter of the MPC5200B can be used as PCI ar biter for the PCI bus. An external PCI arbiter cannot be used. The registers, described in Section 10.
MPC5200B Users Guide, Rev . 1 10-46 F reescale Semiconductor Functional Des cription or more data phases. Data is tr ansferred between initiat or and target in each cycl e that both IRDY and TRDY are ass erted. W ai t cycles may be inserted in a data phase by the initiator (by negating IRDY ) or by the target (by negating TRDY ).
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-47 Figure 10-3. PCI Write T erminated by T arget 10.4.1.4 PCI Bus Commands PCI supports a number of different co mmands. These commands are presente d by the initiator on the C/BE[3:0] lines during the address phase of a PCI transact ion.
MPC5200B Users Guide, Rev . 1 10-48 F reescale Semiconductor Functional Des cription Though MPC5200B supports many PCI co mmands as an initiator , the Communicatio n Sub-System Initiator inte rface is intended to use PCI Memory Read, and Me mory W rite commands.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-49 For linear in crementing mode, the memor y address is encoded/dec oded using AD[31:2].
MPC5200B Users Guide, Rev . 1 10-50 F reescale Semiconductor Functional Des cription Figure 10-4. Contents of t he AD Bus During Address Phase of a T ype 0 Configuration T ransaction Address bits [10:8] identify th e target function and bits AD[7:2] select one of the 64 configurat ion dwords within the target f unction’ s configuration space.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-51 10.4.2 Initiator Arbitration There are three possible internal initiator sources - CommBus Transmit, Co mmBus Receive, or the XL bus (from Internal System Ar biter).
MPC5200B Users Guide, Rev . 1 10-52 F reescale Semiconductor Functional Des cription In addition to the configurable address wi ndow mapping logic, the register interface provides a Configuration Address Register , which provides the ability to genera te Configura tion, Interrupt Acknowledge a nd Specia l Cycl es.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-53 101 001 -- -- -- -- -- OP7 -- -- 100 1101 -- -- OP7 -- 110 001 -- -- -- -- -- -- OP7 -- 100 1011 -- OP7 -- -- 111 .
MPC5200B Users Guide, Rev . 1 10-54 F reescale Semiconductor Functional Des cription 10.4.4.2 Configuration Mechanism In order to support both T ype 0 and T ype 1 configuration transac tions, MPC5200B provides the 32 bit C onfiguration Address Regis ter (CAR), located at module address 0x1F8.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-55 Figure 10-7. T ype 0 Configurat ion T ra nslation For T ype 0 configuration cy cles, MPC5200B translates the device number field of the Configurati on Address Register into a uniqu e IDSEL line shown in T able 10-8 .
MPC5200B Users Guide, Rev . 1 10-56 F reescale Semiconductor Functional Des cription NOTE: Device numbers 0b0_0000 to 0b0_1001 are reserved. Programming to these values and issuing a co nfiguration transaction will result in a PCI configuration cy cle with AD31-A D1 1 driven low .
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-57 During the data phase, AD[31:0] c ontain the S pecial Cycle message and an optional data field. The Special Cycle message is e nco ded on the 16 least significan t bits (AD[15:0]) and the optional data field is enc oded on the most significant bits (AD[31:16]).
MPC5200B Users Guide, Rev . 1 10-58 F reescale Semiconductor Functional Des cription 10.4.5.1 Reads from Local Memory MPC5200B can provide continuous data to a PCI master using two 32-b yte buffers . The PCI controller bursts reads internally at e ach 32-byte PCI address boundary .
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-59 10.4.5.4 T arget Abort A target abort will occur if the PCI addres s falls within a base address window (BAR 0 or BAR1) that has not been enabled. Section 10.3 .2.2, T a rget Base Address T ranslation Regi ster 0 PCITBA TR0(R W) —MBAR + 0x0D64 and Section 10.
MPC5200B Users Guide, Rev . 1 10-60 F reescale Semiconductor Functional Des cription The Communication Sub-System Initiat or Interface consists of Receiv e and Transmit FIFOs, integrated as separate Multi-Cha nnel D MA peripherals. Therefore, it is generally controlled by the Multi-Channel DMA controller through a pre-described program loop.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-61 2. Set the PCI command, Max_Retries, and Max_Beats 3. Set mode, Continuous or Non-continuous 4.
MPC5200B Users Guide, Rev . 1 10-62 F reescale Semiconductor PCI Arbiter 10.4.6.8 Alarms The FIFO alarm registe rs allow software to control when the DMA fill s or empties the appropriate FIFO.
Application Inf ormation MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-63 The PCI Arbiter implements a Round-Robin fa irness algorithm, which avoids the domination of th e bus by high-priority masters an d exclusion of low-priority masters.
MPC5200B Users Guide, Rev . 1 10-64 F reescale Semiconductor Application Information 10.6.2 Address Maps The address mapping in MPC5200B system is setup by soft ware through a number of ba se address registers. ( Section 3.2, Internal Register Memory Map for more detail).
Application Inf ormation MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-65 Figure 10-8. Inbo und Address Map 10.6.2.1.2 Outbound Ad dress T ranslation Figure 10-9 shows example XL Bus Initiator W indow configurations .
MPC5200B Users Guide, Rev . 1 10-66 F reescale Semiconductor Application Information Figure 10-9. Out bound Address Map 10.6.2.1.3 Base Address Register Overview T able 10-1 5 shows the available accessibility for all PCI associated base ad dress and translation address registers in MPC5200B.
Application Inf ormation MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 10-67 10.6.3 XL b us Arbitration Priority When the XL Bus Arbiter Master Priority Regi ster ( Section 16.
MPC5200B Users Guide, Rev . 1 10-68 F reescale Semiconductor Application Information.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-1 Chapter 11 A T A Controller 11.1 Overview The following sections are contained in this document: • Section 1 1.2, BestComm Key Featur es — Section 1 1.3, A T A Register Interface , includes: — Section 1 1.
MPC5200B Users Guide, Rev . 1 11-2 F reescale Semiconductor A T A Register Interface 4. As FIFO fills, BestComm is in terrupted and moves data from FIFO to an internal destination. 11.2.2 BestComm Write 1. microprocessor sets up descriptors in BestComm RAM and initi ates a transfer .
A T A Register Interface MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-3 11.3.1.2 A T A Host Status Registe r—MBAR + 0x3A04 11.3.1.3 A T A PIO Timing 1 Register—MB AR + 0x3A08 6 IE Enables driv e interr upt to pass to CPU in PIO modes.
MPC5200B Users Guide, Rev . 1 11-4 F reescale Semiconductor A T A Register Interface 11.3.1.4 A T A PIO Timing 2 Register—MB AR + 0x3A0C 11.3.1.5 A T A Multiw ord DMA Timing 1 Register—MB AR + 0x3A10 Bit s Name Description 0 : 7 pio_t0 PIO cycle time count v alue is based on system clock operating frequency .
A T A Register Interface MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-5 11.3.1.6 A T A Multiw ord DMA Timing 2 Register—MB AR + 0x3A14 11.3.1.7 A T A Ultra DMA Timing 1 Re gister—MBAR + 0x3A18 Bit s Name Description 0 : 7 dma_t0 Multiword DMA cycle time.
MPC5200B Users Guide, Rev . 1 11-6 F reescale Semiconductor A T A Register Interface 11.3.1.8 A T A Ultra DMA Timing 2 Re gister—MBAR + 0x3A1C 11.3.1.9 A T A Ultra DMA Timing 3 Re gister—MBAR + 0x 3A20 Bit s Name Description 0 : 7 ud ma_t2cyc Ultr a DMA sustained av erage two cycle time.
A T A Register Interface MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-7 11.3.1.10 A T A Ultra DMA Timing 4 Register—MB AR + 0x3A24 Bit s Name Description 0 : 7 u dma_tmli Limited interlock time with a defined min imum, when drive or host are waiting f or response from each other .
MPC5200B Users Guide, Rev . 1 11-8 F reescale Semiconductor A T A Register Interface 11.3.1.11 A T A Ultra DMA Timing 5 Register—MB AR + 0x3A28 11.3.1.12 A T A Share Count Register—MB AR + 0x3A2C 11.3.2 A T A FIFO Regi sters—MB AR + 0x3A00 A T A uses a single FIFO that changes direct ion based on the Rx / Tx mode.
A T A Register Interface MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-9 A T A FIFO is controlled by 32-bit registers. These registers are located at an of fset from MBAR of 0x3a00.
MPC5200B Users Guide, Rev . 1 11-10 F reescale Semiconductor A T A Register Interface 11.3.2.3 A T A Rx / Tx FIFO Contr ol Register—MBAR + 0x3A44 11.3.2.4 A T A Rx / Tx FIFO Alarm Register—MB AR + 0x3A48 10 UF Und erFlow—flag indicates read pointer has sur passed the write pointer.
A T A Register Interface MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-11 11.3.2.5 A T A Rx / Tx FIFO Read P ointer Register—MB AR + 0x3A4C 11.
MPC5200B Users Guide, Rev . 1 11-12 F reescale Semiconductor A T A Register Interface 11.3.3 A T A Drive Registers—MB AR + 0x3A00 The A T A drive registers are physically located inside the drive c ontroller on the A T A disk drive. The MPC5200B A T A Host Control ler provides acces s to these registers using the chip select s and address bits.
A T A Register Interface MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-13 11.3.3.2 A T A Drive Alternate Status Reg ister—MBAR + 0x3A5C 11.
MPC5200B Users Guide, Rev . 1 11-14 F reescale Semiconductor A T A Register Interface 11.3.3.4 A T A Drive Features Register—MB AR + 0x3A64 11.3.3.5 A T A Drive Err or Register—MB AR + 0x3A64 T able 11-22.
A T A Register Interface MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-15 11.3.3.6 A T A Drive Sector Count Registe r —MB AR + 0x3A68 11.
MPC5200B Users Guide, Rev . 1 11-16 F reescale Semiconductor A T A Register Interface 11.3.3.8 A T A Drive Cylinder Lo w Register—MB AR + 0x3A70 11.3.
A T A Register Interface MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-17 11.3.3.10 A T A Drive Device / Head Register—MB AR + 0x3A78 11.
MPC5200B Users Guide, Rev . 1 11-18 F reescale Semiconductor A T A Register Interface Bit s Name Description 0 : 7 Data Register cont ains the command co de sent to the driv e. When this register is written, command ex ecution begins immediately . Writing this register clears any pending interrup t condition.
A T A Register Interface MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-19 11.3.3.12 A T A Drive Device Status Register—MB AR + 0x3A7C T able 11-30.
MPC5200B Users Guide, Rev . 1 11-20 F reescale Semiconductor A T A Host Contr oller Operation 11.4 A T A Host Controller Operation W ith the asynchronous A T A interface, an interf ace must be implemented that meets the timing specifications, given an input cloc k from the processor that is not fixed among all applic ations.
A T A Host Contr oller Operation MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-21 udma_t2cyc is another special ca se. Unlike the name i mplies, this regist er does not control 2 UDMA ti min g cycles. Rather , it controls how long the host continue s to accept data after it ha s de-asserted HDMARDY–.
MPC5200B Users Guide, Rev . 1 11-22 F reescale Semiconductor A T A Host Contr oller Operation If A T A drive address space is accessed by CPU, the A T A IPBI module generates: • a signal to en able .
Signals and Connections MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-23 11.5 Signals and Connections NO TE The A T A_ISOLA TION output is an active high signal to control external A T A transceiver devices and to isolate the A T A bus from the Local Plus (share d) bus.
MPC5200B Users Guide, Rev . 1 11-24 F reescale Semiconductor A T A Interface Description Figure 11-2. Connections—Contr oller Cable, System Boa rd, MPC5200B 11.
A T A Inter face Description MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-25 NO TE MPC5200B provides the A T A_ISOLA TION output signal. This signal is shared with the A22 output of the LocalPlus Most/Graphic s mode. The A T A_ISOLA TION is not a signal defined by the A T A Standard.
MPC5200B Users Guide, Rev . 1 11-26 F reescale Semiconductor A T A Bus Background Figure 11-3. Pi n Description—A T A Interface 11.7 A T A Bus Backgr ound 11.
A T A Bus Bac kground MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-27 11.7.2 A T A Modes 11.7.3 A T A Addressing In the A T A interface, there are two aspe cts of addressing that are present: register addressing and secto r addressing. These are discussed in the next sections.
MPC5200B Users Guide, Rev . 1 11-28 F reescale Semiconductor A T A Bus Background 11.7.3.1 A T A Register Ad dressing The address used to reference an A T A drive r egister . This is the a ctual address ( CS [1]F X , CS [3]F X , DA [ 2 : 0 ] ) present on the physical A T A interface.
A T A Bus Bac kground MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-29 Notes 1. LBA mode is on ly available in A T A-2 or later specifications. 2. A block mode exists ( not to be confused with logical block addressing ), in which sectors are grouped into a unit, called a bl ock, for purposes of data transfer .
MPC5200B Users Guide, Rev . 1 11-30 F reescale Semiconductor A T A Bus Background 11.7.4 A T A T ransactions A T A Transactions ar e di vided into three types: • PIO Mode • Multiword DMA •U l t r a D M A 11.7.4.1 PIO Mode T ransactions PIO mode transactions are the simp lest transaction available on the A T A interface.
A T A Bus Bac kground MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-31 Figure 11-5. Timing Diagram— PIO Read Command ( Cl ass 1 ) 11.7.4.1.2 Class 2—PIO Write The PIO single sector wr ite command [ format, write buf fer , write sector ( s ) ] is as follows: 1.
MPC5200B Users Guide, Rev . 1 11-32 F reescale Semiconductor A T A Bus Background Figure 11-6. Timing Diagram—PIO Write Command ( C lass 2 ) 11.7.4.1.3 Class 3— Non-Data Command The Non-Data Command is as follows: 1. HOST : W rite to A T A control / command bl ock registers to setup for data read.
A T A Bus Bac kground MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-33 3. W rite command code 0xEF to comm and register to execute SET FEA TURES command. This sets the data transfer pro tocol to multiword DMA with desired mode. Data transfers into DMA di ffer from a PIO transfe r in that: • Data is transf erred using the DMA channel.
MPC5200B Users Guide, Rev . 1 11-34 F reescale Semiconductor A T A Bus Background Figure 11-8. Flo w Diagram—DMA Command Pr otocol Host: BSY = 0 & DRQ = 0 No Host: BSY = 0 & DRQ = 0 No Yes Y.
A T A Bus Bac kground MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-35 11.7.4.3 Multiwor d DMA T ransactions Multiword DMA transactions dif fer from PIO mode transactions in three ways: 1. Data transfers are done using a drive DMA and a host DMA (optional).
MPC5200B Users Guide, Rev . 1 11-36 F reescale Semiconductor A T A RESET / P ower -Up NO TE Ultra DMA mode 2 (UDMA2) requires that th e ip bus clock speed is at least 66 MHz. T able 1 1-39 lists the redefined ultra DMA protocol signal lines. These lines provide new functions during th e ultra DMA mode.
A T A I/O Cable Specifications MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 11-37 Figure 11-10. Timing Dia gram—Reset Timing 11.9 A T A I/O Cable Specifications For reference, the standard A T A cable specifications affects st em integrity and should not exceed 18 inches or 0 .
ATA C o n t r o l l e r Notes MPC5200B Users Guide, Rev . 1 11-38 F reescale Semiconductor.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 12-1 Chapter 12 Univer sal Serial Bus ( U SB ) 12.1 Overview The following sections are contained in this document: • Section 12.2, Data T ransfer T ypes • Section 12.4, Host Contr ol ( HC ) Operational Registers , includes: — Section 12.
MPC5200B Users Guide, Rev . 1 12-2 F reescale Semiconductor Host Controller Interface • Bulk T ransfers —Non-periodic data transfers used to communicate large amo unts of informat ion between clien t software and the USB device. In OpenHCI the data tra nsfer types are classified into two ca tegories: period ic a nd nonperiodic.
Host Controller Interface MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 12-3 The HCCA includes the “virtual” regist ers HccaFrameNumber and Hcc aPad1. The offse ts shall be 0x80 (for HccaFrameNumbe r) and 0x82 (for HccaPad1). In the USB module of the MPC5200B these tw o “virtual” registers are swap ped.
MPC5200B Users Guide, Rev . 1 12-4 F reescale Semiconductor Host Controller Interface Figure 12-4. Interru pt ED Structure Figure 12-5 shows a sample interrupt endpoi nt schedule.
Host Contr ol ( HC ) Operational Register s MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 12-5 Figure 12-5. Sample Interrupt Endpo int Schedule 12.4 Host Control ( HC ) Operational Registers Host Control contains a set of on-chip operational registers which are mapped into a non-cacheable portion of the system addres sab le space.
MPC5200B Users Guide, Rev . 1 12-6 F reescale Semiconductor Host Control ( HC ) Oper ational Registers 12.4.2 Control and Status P artition—MB AR + 0x1000 This HC partition uses 6 32-bit registers. These registers are located at an offs et from MBAR of 0x1000.
Host Contr ol ( HC ) Operational Register s MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 12-7 Bit s Name Description 0 : 20 — Reser v ed 21 RW E Remote W akeUp E n ab le—HCD uses bit to enable or disable the remote Wak eUp feature on detection of upstream resume signaling.
MPC5200B Users Guide, Rev . 1 12-8 F reescale Semiconductor Host Control ( HC ) Oper ational Registers 12.4.2.3 USB HC Command Status Register—MB AR + 0x1008 HC uses the HC Command Sta tus register to receive ( Rx ) commands issued by HCD. It reflects the current HC status.
Host Contr ol ( HC ) Operational Register s MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 12-9 12.4.2.4 USB HC Interrupt Status Register —MB AR + 0x 100C This register provides status on various events that cause hardwa re interrupts. When an event oc curs, HC sets the corresponding register bit.
MPC5200B Users Guide, Rev . 1 12-10 F reescale Semiconductor Host Control ( HC ) Oper ational Registers 12.4.2.5 USB HC Interrupt Enable Register—MB AR + 0x 1010 Each enable bit in the HC Interrupt Enable register corresponds to an associated interrupt bit in the HcIn terruptStatus registe r.
Host Contr ol ( HC ) Operational Register s MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 12-11 12.4.2.6 USB HC Interrupt Disable Re gister—MBAR + 0x 1014 Each disable bit in the HC Interrupt Disabl e register corresponds to an associated in terrupt bit in the Hc InterruptStatus regis ter .
MPC5200B Users Guide, Rev . 1 12-12 F reescale Semiconductor Host Control ( HC ) Oper ational Registers 12.4.3 Memory P ointer P ar tition—MBAR + 0x1018 This HC partition uses 7 32-bit registers. These registers are located at an offs et from MBAR of 0x1018.
Host Contr ol ( HC ) Operational Register s MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 12-13 • USB HC Bulk Current Endpi nt Descriptor Register (0x102C) • USB HC Done Head Register (0x1030) 12.4.3.1 USB HC HCCA Register—MB AR + 0x1018 The HC HCCA register contains the physical address of the Host Controller Communication Area.
MPC5200B Users Guide, Rev . 1 12-14 F reescale Semiconductor Host Control ( HC ) Oper ational Registers 12.4.3.3 USB HC Control Head Endpoint Descriptor Register —MB AR + 0x1020 The HC Control Head Endpoint Desc riptor register contains the phys ical address of the first endpoi nt descriptor of the Control list.
Host Contr ol ( HC ) Operational Register s MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 12-15 12.4.3.6 USB HC Bulk Current Endpoint Descriptor Register—MB AR + 0x102C The HC Bulk Current Endpoint Descriptor re gister contains the physical address of the current endpoint of the bulk list.
MPC5200B Users Guide, Rev . 1 12-16 F reescale Semiconductor Host Control ( HC ) Oper ational Registers 12.4.4 Frame Counter P ar tition—MB AR + 0x1034 This HC partition uses 5 32-bit registers. These registers are located at an offs et from MBAR of 0x1034.
Host Contr ol ( HC ) Operational Register s MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 12-17 12.4.4.2 USB HC Frame Remaining Register—MB AR + 0x1038 This register is a 14-bit coun t-down counter containi ng the remaining cu rrent Frame bit-time.
MPC5200B Users Guide, Rev . 1 12-18 F reescale Semiconductor Host Control ( HC ) Oper ational Registers 12.4.4.4 USB HC P eriodic Star t Register—MB AR + 0x1040 This register has a 14-bit programmable valu e that determines when is the earliest time HC should start processing the periodic list .
Host Contr ol ( HC ) Operational Register s MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 12-19 12.4.5 Root Hub P ar tition—MB AR + 0x1048 This HC partition uses 5 32-bit registers. These registers are located at an offs et from MBAR of 0x1048.
MPC5200B Users Guide, Rev . 1 12-20 F reescale Semiconductor Host Control ( HC ) Oper ational Registers 12.4.5.2 USB HC Rh Descriptor B Register—MB AR + 0x104C This register is the second of two regist ers describing the Root Hub characteristics. These fields are written during initializ ation to correspond with the system implem entation.
Host Contr ol ( HC ) Operational Register s MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 12-21 12.4.5.3 USB HC Rh Status Register—MB AR + 0x1050 This register is divided into two parts. The lower 16 bits of a 32-bit word represen ts the hub status field; the upper word rep resen ts the hub status change field.
MPC5200B Users Guide, Rev . 1 12-22 F reescale Semiconductor Host Control ( HC ) Oper ational Registers 12.4.5.4 USB HC Rh P ort1 Status Register—MBAR + 0x10 54 This register is controls and reports port events on a per-port basis.
Host Contr ol ( HC ) Operational Register s MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 12-23 T able 12-22. USB HC Rh P ort 1 Status Register m s b 0 123456789 1 0 1 1 1 2 1 3 1 4 1 5 R Re.
MPC5200B Users Guide, Rev . 1 12-24 F reescale Semiconductor Host Control ( HC ) Oper ational Registers 15 CSC Connect Status Change—bit is set whene ver a connect or disconnect ev ent occurs. • Writing 1 causes HC to clear th is bit. • Writing 0 has no effect.
Host Contr ol ( HC ) Operational Register s MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 12-25 28 POCI Port Over Curren t Indicator ( r ead )—bit is only v alid when root hub is configured in such a wa y that ov ercurrent conditio ns are repor ted on a per-por t basis.
MPC5200B Users Guide, Rev . 1 12-26 F reescale Semiconductor Host Control ( HC ) Oper ational Registers 12.4.5.5 USB HC Rh P ort2 Status Register—MBAR + 0x10 58 This register is controls and reports port events on a per-port basis.
Host Contr ol ( HC ) Operational Register s MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 12-27 Bit s Name Description 0 : 10 — Reserved 11 PRSC P or t Reset Status Ch ange—bit is set at the end of the 10 ms port rese t signal. • Writing 1 clears this bit.
MPC5200B Users Guide, Rev . 1 12-28 F reescale Semiconductor Host Control ( HC ) Oper ational Registers 23 PPS P or t P ower Status ( read )—bit reflects the por t po wer status , regardless of the type of power s witch ing implemented. If an ov ercurrent condition is dete cted, this bit is cleared.
Host Contr ol ( HC ) Operational Register s MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 12-29 29 PSS P or t Suspend Status ( read )—bit indi cates por t is suspended or in resume sequence. It is set by a Set Suspe nd State write and cleared when P or t Suspend Status Change is set at the end of the resume interval.
Universal Serial Bus ( USB ) Notes MPC5200B Users Guide, Rev . 1 12-30 F reescale Semiconductor.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-1 Chapter 13 BestComm 13.1 Overview The following sections are contained in this document: • Section 13.2, BestComm Functional Description • Section 13.15, BestComm DMA Registers—MBAR + 0x1200 • Section 13.
MPC5200B Users Guide, Rev . 1 13-2 F reescale Semiconductor Features summary NO TE It is possible for the BESTComm DMA to produce misaligned word addresses on its Slave and Comm bus. These accesses occur due to incorrect progr am code executed by the BestComm unit.
T ask T able (Entry T able) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-3 Each task has an entry (8 long words) that contains informa tion about the microcode’ s location (start addre.
MPC5200B Users Guide, Rev . 1 13-4 F reescale Semiconductor BestComm XLB Ad dress Snooping 13.14 BestComm XLB Address Snooping BestComm prefetches dat a from the XLB into 4 32-Byte wide Read Line Buffers.
BestComm DMA Registers—MBAR + 0x1200 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-5 13.15.2 SDMA Current P oin ter Register—MBAR + 0x1204 13.15.3 SDMA End P ointer Register—MB AR + 0x1208 13.15.4 SDMA V ariab le P ointer Register—MBAR + 0x120C T able 13-2.
MPC5200B Users Guide, Rev . 1 13-6 F reescale Semiconductor BestComm DMA Registers—MB AR + 0x1200 13.15.5 SDMA Interrupt V ector , PTD Contr ol Register —MB AR + 0x1210 16 17 18 19 20 21 22 23 24 .
BestComm DMA Registers—MBAR + 0x1200 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-7 13.15.6 SDMA Interrupt Pendi ng Register—MB AR + 0x1214 Bit Name Description 0 : 7 IntV ect1 The Interrupt V ector register is used during interr upt ackno wledge read cycl es .
MPC5200B Users Guide, Rev . 1 13-8 F reescale Semiconductor BestComm DMA Registers—MB AR + 0x1200 13.15.7 SDMA Interrupt M ask Register—MBAR + 0x1218 Bit Name Description 0D B G D e b u g 1:2 — Reser ved 3 TEA A TEA has been receiv ed b y the currently running task.
BestComm DMA Registers—MBAR + 0x1200 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-9 13.15.8 SDMA T ask Control 0 Register—MB AR + 0x121C SDMA T ask Contr ol 1 Re gister—MBAR + 0x121E T able 13-8 .
MPC5200B Users Guide, Rev . 1 13-10 F reescale Semiconductor BestComm DMA Registers—MB AR + 0x1200 13.15.9 SDMA T ask Control 2 Register—MB AR + 0x1220 SDMA T ask Contr ol 3 Re gister—MBAR + 0x1.
BestComm DMA Registers—MBAR + 0x1200 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-11 13.15.10 SDMA T ask Control 4 Register—MB AR + 0x1224 SDMA T ask Contr ol 5 Re gister—MBAR + 0x1226 13.15.11 SDMA T ask Control 6 Register—MB AR + 0x1228 SDMA T ask Contr ol 7 Re gister—MBAR + 0x122A T able 13-10.
MPC5200B Users Guide, Rev . 1 13-12 F reescale Semiconductor BestComm DMA Registers—MB AR + 0x1200 13.15.12 SDMA T ask Control 8 Register—MB AR + 0x122C SDMA T ask Contr ol 9 Re gister—MBAR + 0x122E 13.15.13 SDMA T ask Control A Register—MB AR + 0x1230 SDMA T ask Contr ol B Re gister—MBAR + 0x1232 T able 13-12.
BestComm DMA Registers—MBAR + 0x1200 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-13 13.15.14 SDMA T ask Control C Register—MB AR + 0x1234 SDMA T ask Contr ol D Re gister—MBAR + 0x1236 13.15.15 SDMA T ask Control E Register—MB AR + 0x1238 SDMA T ask Contr ol F Re gister—MBAR + 0x123C T able 13- 14.
MPC5200B Users Guide, Rev . 1 13-14 F reescale Semiconductor BestComm DMA Registers—MB AR + 0x1200 13.15.16 SDMA Initiator Priori ty 0 Register—MBAR + 0x123C SDMA Initiator Priority 1 Register—MB AR + 0x123D SDMA Initiator Priority 2 Register—MB AR + 0x123E SDMA Initiator Priority 3 Register—MB AR + 0x123F T able 13-16.
BestComm DMA Registers—MBAR + 0x1200 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-15 13.15.17 SDMA Initiator Priori ty 4 Register—MBAR + 0x1240 SDMA Initiator Priority 5 Register—MB AR + 0x1241 SDMA Initiator Priority 6 Register—MB AR + 0x1242 SDMA Initiator Priority 7 Register—MB AR + 0x1243 13.
MPC5200B Users Guide, Rev . 1 13-16 F reescale Semiconductor BestComm DMA Registers—MB AR + 0x1200 13.15.19 SDMA Initiator Priori ty 12 Register—MBAR + 0x1248 SDMA Initiator Priority 13 Register.
BestComm DMA Registers—MBAR + 0x1200 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-17 13.15.20 SDMA Initiator Priori ty 16 Register—MBAR + 0x124C SDMA Initiator Priority 17 Register.
MPC5200B Users Guide, Rev . 1 13-18 F reescale Semiconductor BestComm DMA Registers—MB AR + 0x1200 13.15.21 SDMA Initiator Priori ty 20 Register—MBAR + 0x1250 SDMA Initiator Priority 21 Register—MB AR + 0x1251 SDMA Initiator Priority 22 Register—MB AR + 0x1252 SDMA Initiator Priority 23 Register—MB AR + 0x1253 13.
BestComm DMA Registers—MBAR + 0x1200 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-19 13.15.23 SDMA Initiator Priori ty 28 Register—MBAR + 0x1258 SDMA Initiator Priority 29 Register.
MPC5200B Users Guide, Rev . 1 13-20 F reescale Semiconductor BestComm DMA Registers—MB AR + 0x1200 13.15.24 SDMA Requestor MuxControl—MB AR + 0x125C 16 : 23 IPR30 Initiator Prior ity register fo r ini tiator 30. Same bit la yout as IPR0 24 : 31 IPR31 Initiator Prior ity register fo r ini tiator 31.
BestComm DMA Registers—MBAR + 0x1200 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-21 The remaining 16 Requestors are fixed as follows: 12:13 Req25 00: Requestor IrD A RX (PSC_6) 01: GP.
MPC5200B Users Guide, Rev . 1 13-22 F reescale Semiconductor BestComm DMA Registers—MB AR + 0x1200 13.15.25 SDMA task Si z e0—MB AR + 0x1260 SDMA task Size 1—MB AR + 0x1264 T able 13-25.
BestComm DMA Registers—MBAR + 0x1200 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-23 13.15.26 SDMA task 0 & task Size 1 map 13.15.27 SDMA Reser ved R egister 1—MB AR + 0x1268 Bit.
MPC5200B Users Guide, Rev . 1 13-24 F reescale Semiconductor BestComm DMA Registers—MB AR + 0x1200 13.15.28 SDMA Reser ved R egister 2—MB AR + 0x126C 13.15.29 SDMA Debug Module Comparator 1, V alue 1 Register—MB AR + 0x1270 13.15.30 SDMA Debug Module Comparator 2, V alue 2 Register—MB AR + 0x1274 T able 13-29.
BestComm DMA Registers—MBAR + 0x1200 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-25 13.15.31 SDMA Deb ug Module Control Register —MB AR + 0x1278 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb RV a l u e 2 W R E S E T : 0 00000000 0 0 0 00 0 0 Bit Name Description 0 : 31 V alue2 Debug Module Comparator 2 V alu e.
MPC5200B Users Guide, Rev . 1 13-26 F reescale Semiconductor BestComm DMA Registers—MB AR + 0x1200 The reserved encodi ngs are set to 0 indicating an uninitialized st ate. 25:28 EU breakpoints euBreakpoint: Th ese bits indicate that a breakpoint has occurred in one of the f o ur ex ecution units.
BestComm DMA Registers—MBAR + 0x1200 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-27 It must be noted that even if a breakpoint is issue d at a spec ific address the SDM A engine will .
MPC5200B Users Guide, Rev . 1 13-28 F reescale Semiconductor On-Chip SRAM 13.16 On-Chip SRAM MPC5200B contains 16 KBytes of on-chip SRAM. This memory is dire ctly accessible by the BestComm DM A un it.
Programming Model MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-29 04 5 1 4 1 5 1 9 2 0 3 1 T ask 0 T ask Descriptor Star t P ointer T ask Descr iptor End P ointer V ariab le T able Po in.
BestComm Notes MPC5200B Users Guide, Rev . 1 13-30 F reescale Semiconductor 13.17.1.1 Integ er Mode This input signal is only valid if the pack signal is negated (s et to ‘0’). This signal indicate s if the SDMA engine should ope rate in integer mode or fractional mode.
Programming Model MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 13-31 task’ s V ariable T able is desired. In addi tion, if a task does not use the last 16 variables, anothe r V ariable T able could start immediately after that task ’ s increment values , so as to not waste memory .
MPC5200B Users Guide, Rev . 1 13-32 F reescale Semiconductor Programming Model.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-1 Chapter 14 F ast Ethernet Controller ( FEC ) 14.1 Overview The fast Ethernet controller (FEC ) is an Ethernet MAC plus two 1 Kbyte FIFOs that work under the control of the processor and B estComm DMA engine to support 10/100 M bps Ethernet/802.
MPC5200B Users Guide, Rev . 1 14-2 F reescale Semiconductor Overview Figure 14-1. Block Dia gram—FEC 14.1.1 Features The FEC incorporates se veral features/d esign goals that are key to its use: • Support for different Ethernet physical interfaces: — 100 Mbps IEEE 802.
Modes of Operation MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-3 • Automatic internal flus hing of the Rx FIFO for runts (collision fragments ) and address recognition re jects (no processor bus utilization).
MPC5200B Users Guide, Rev . 1 14-4 F reescale Semiconductor I / O Signal Overview 14.3.1 Detailed Si gnal Descriptions 14.3.1.1 MII Ethernet MA C-PHY Interface This section gives a detailed de scription of the Media-Independe nt Interface (MII). An overview of the MII is presented followe d by a description of the MII signals.
I / O Signal Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-5 Tx_EN . . . . . . . . . . . . . Assertion of this signal in dicates va lid nibbles are bein g presented on the MII. This signal is asse rted with the first nibble of preamble and is nega ted prior to the first Tx_CLK foll owing the final nibble of the frame.
MPC5200B Users Guide, Rev . 1 14-6 F reescale Semiconductor FEC Memory Map and Regis ters 14.3.1.2.1 MII Manage ment Register Set The MII management register set loc ated in the PHY may consist of a basic register set and an ex tended register set as defined in T able 14-5 .
FEC Memory Map and Regis ters MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-7 14.4.1 Control and Status (CSR) Memory Map T able 14-6. Module Memor y Map Address Function 000–1FF Con trol / Status Registers 200–3FF MIB Block Counters, see Ta b l e 1 4 - 8 400–7FF Reser ved T able 14-7.
MPC5200B Users Guide, Rev . 1 14-8 F reescale Semiconductor FEC Memory Map and Regis ters 14.4.2 MIB Bloc k Counters Memory Map T able 14-8 defines the MIB Counters memory map which defines the MIB RAM space locations wh ere hardware-maintai ned counters reside.
FEC Memory Map and Regis ters MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-9 T able 14- 8. MIB Counters Address Mnemonic Description 200 RMON_T_DROP Count of Fr ames Not Correctly Counte.
MPC5200B Users Guide, Rev . 1 14-10 F reescale Semiconductor FEC Registers—MB AR + 0x3000 14.5 FEC Reg ister s—MBAR + 0x3000 The FEC uses 37 32-bit registers. These registers are located at an offset fro m MBAR of 0x3000. Register addresses are relative to th is offset.
FEC Registers—MB AR + 0x3000 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-11 14.5.1 FEC ID Register—MB AR + 0x3000 The read-only FEC ID Regist er (FEC_I D) identifies the FEC block and revision.
MPC5200B Users Guide, Rev . 1 14-12 F reescale Semiconductor FEC Registers—MB AR + 0x3000 14.5.2 FEC Interrupt E vent Register—MB AR + 0x3004 When an event occurs that sets a bit in the IEVENT register , an interrupt is gene rated if the corresponding bit in the interrup t enable register (IMASK) is also set.
FEC Registers—MB AR + 0x3000 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-13 R Reser v ed W Bit s Name Description 0 HBERR Hear tbe at Error— interrupt bit indicates HBC is set in the X_CNTRL register and COL input was not assert ed within the hear tbeat window f ollowing a transmission.
MPC5200B Users Guide, Rev . 1 14-14 F reescale Semiconductor FEC Registers—MB AR + 0x3000 14.5.3 FEC Interrupt Enab le Register—MB AR + 0x3008 The IMASK register provides control over the interrupt events allowed to gene rate an interrupt. All implemented bits in this CS R are R / W .
FEC Registers—MB AR + 0x3000 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-15 The R_DES_ACTIVE bit is cleared at reset and by the clearing of ETHER_EN.
MPC5200B Users Guide, Rev . 1 14-16 F reescale Semiconductor FEC Registers—MB AR + 0x3000 14.5.6 FEC Ethernet Contr o l Register—MBAR + 0x3024 The ECNTRL regist er is a read / write user register that can en able / di sable the FEC. S ome fiel ds may be altered by hardware.
FEC Registers—MB AR + 0x3000 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-17 14.5.7 FEC MII Management Frame Register—MBAR + 0x3040 This MII_DA T A register does not reset to a defined value.
MPC5200B Users Guide, Rev . 1 14-18 F reescale Semiconductor FEC Registers—MB AR + 0x3000 user . When the write management frame opera tion is complete, the M II_DA T AIO_COMPL interrupt is generate d. At this time the MII_ DA T A register contents match th e original value written.
FEC Registers—MB AR + 0x3000 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-19 14.5.9 FEC MIB Contr ol Register—MBAR + 0x3064 The MIB_CONTROL register is a read/write re gister used to provide control of and to observe the state of the MIB block.
MPC5200B Users Guide, Rev . 1 14-20 F reescale Semiconductor FEC Registers—MB AR + 0x3000 14.5.10 FEC Receive Contro l Register—MBAR + 0x3084 The R_CNTRL register is user pr ogrammable. It controls the operatio nal mode of the receive block and shoul d be written on ly whe n ETHER_EN = 0 (ini tialization tim e).
FEC Registers—MB AR + 0x3000 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-21 14.5.11 FEC Hash Register—MB AR + 0x3088 The read-only R_HASH register provides addr ess recognition information from the Rx bloc k about the frame currently being receiv ed.
MPC5200B Users Guide, Rev . 1 14-22 F reescale Semiconductor FEC Registers—MB AR + 0x3000 14.5.13 FEC Physical Ad dress Low Register—MB AR + 0x30E4 The P ADDR1 register is written by the user .
FEC Registers—MB AR + 0x3000 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-23 Note: X: Bit is not reset and must be initialized. 14.5.14 FEC Physical Ad dress High Register—MB AR + 0x30E8 The P ADDR2 register is written by the user .
MPC5200B Users Guide, Rev . 1 14-24 F reescale Semiconductor FEC Registers—MB AR + 0x3000 Note: X: Bit is not reset and must be initialized. 14.5.16 FEC Descriptor Individual Address 1 Registe—MB AR + 0x3118 The IADDR1 register is written by th e us er .
FEC Registers—MB AR + 0x3000 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-25 Note: X: Bit is not reset and must be initialized. 14.5.18 FEC Descriptor Group Addr ess 1 Register —MBAR + 0x3120 The GADDR1 register is written by the user .
MPC5200B Users Guide, Rev . 1 14-26 F reescale Semiconductor FEC Registers—MB AR + 0x3000 Note: X: Bit is not reset and must be initialized. 14.5.20 FEC Tx FIFO W atermark Register—MB AR + 0x3144 .
FIFO Interface MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-27 14.6 FIFO Interface The programming inte rface to the FIFO allows access to Data, S tatus, Control, Last W rite Pointer , Last Read Pointer , Alarm, Rea d and W rite Pointers for T ransmit and Receiv e configurations.
MPC5200B Users Guide, Rev . 1 14-28 F reescale Semiconductor FEC Tx FIFO Data Register—MB AR + 0x31A4 14.6.1 FEC Rx FIFO Data Register—MB AR + 0x3184 14.7 FEC Tx FIFO Data Register—MBAR + 0x31A4 The RFIFO_DA T A and TFIFO_DA T A registers are the main interface port for the transm it and receive FIFO.
FEC Tx FIFO Status Register—MB AR + 0x31A8 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-29 14.8.1 FEC Rx FIFO Cont rol Register—MB AR + 0x318C FEC Tx FIFO Control R egister—MBAR + .
MPC5200B Users Guide, Rev . 1 14-30 F reescale Semiconductor FEC Tx FIFO Status Register—MB AR + 0x31A8 14.8.2 FEC Rx FIFO Las t Read Frame P ointer Register—MB A R + 0x3190 FEC Tx FIFO Last Read .
FEC Tx FIFO Status Register—MB AR + 0x31A8 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-31 14.8.3 FEC Rx FIFO Las t Write Frame P ointer Register—MBAR + 0x3194 FEC Tx FIFO Last Write.
MPC5200B Users Guide, Rev . 1 14-32 F reescale Semiconductor FEC Tx FIFO Status Register—MB AR + 0x31A8 14.8.5 FEC Rx FIFO Read P o inter Register—MB AR + 0x319C FEC Tx FIFO Read P ointe r Register—MB AR + 0x31BC The RFIFO_RDP TR and TFIFO_RDP TR are a FIFO-m aintained pointer which point to the nex t FIFO location to be read.
FEC Tx FIFO Status Register—MB AR + 0x31A8 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-33 14.8.6 FEC Rx FIFO Write P o inter Register—MBAR + 0x31A0 FEC Tx FIFO Writer P ointe r Register—MB AR + 0x31C0 The RFIFO_WRP TR and TFIFO_WRP TR ar e a FIFO-maintained pointe r whic h point to the next FIFO loca tion to be written.
MPC5200B Users Guide, Rev . 1 14-34 F reescale Semiconductor Initialization Sequen ce 14.8.8 FEC T ransmit FSM Register—MB AR + 0x31C8 The transmit finite state machin e register (XMIT_FSM) controls operation of a ppending CRC. T ypical use is en abled and CRC is ap pended.
Initializati on Sequence MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-35 14.9.2 User Initialization (P rior to Asserting ETHER_EN) The user needs to initialize por tions of the FEC prior to setting the ETHER_EN bi t. The exact values depend on the particular a pplication; the sequence of writing the registers is not important.
MPC5200B Users Guide, Rev . 1 14-36 F reescale Semiconductor Initialization Sequen ce 14.9.3.2 T ransmit Frame Control W ord The only requirement for this cont rol word is to have the TC and ABC bits valid. The TC bit defines whet her the transmit block should append the CRC (TC = 1) or not (TC = 0) for the current frame.
Initializati on Sequence MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-37 Bits 31-27, 24-0—Reserved 14.9.4 Netw ork Interface Options The FEC supports both an MII inte rface for 10/100 Mbps Eth ernet and a 7-wire se rial interface for 10 M bps Ethernet.
MPC5200B Users Guide, Rev . 1 14-38 F reescale Semiconductor Initialization Sequen ce In MII mode the receiver checks for at le ast one byte matching the SFD. Zero or more P A bytes may occur , but if a 00 bit sequen ce is detect ed prior to the SFD byte, the frame is ignored.
Initializati on Sequence MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-39 Figure 14-2. Ethernet Ad dress R ecognition - receive bloc k decisions Accept/Reject Broadcast Addr ? ? PROM = 1 ? Receive Address Tru e NOTES: BC_REJ - field in R_CNTRL register (BroadCast REJect) False Tr u e False BC_REJ = 1 ? AR_EM_B - bit in RECV .
MPC5200B Users Guide, Rev . 1 14-40 F reescale Semiconductor Initialization Sequen ce The hash table algorithm used in the group and individual hash filtering operates as follows.
Initializati on Sequence MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-41 T able 14- 45. Destination Address to 6-Bit Has h 48-bit D A 6-bit hash (in hex) hash decimal v alue 65:ff:ff:ff:.
MPC5200B Users Guide, Rev . 1 14-42 F reescale Semiconductor Initialization Sequen ce 14.9.7 Full-Duplex Flo w Control Full-duplex flow control allows the user to transmit pause frames and to detect received pause fr ames. Upon detection of a paus e frame, MAC data frame transm is sion stops for a given pause duration.
Initializati on Sequence MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-43 Pause frame detection is performed by the re ceiver and microcontroller modules.
MPC5200B Users Guide, Rev . 1 14-44 F reescale Semiconductor Initialization Sequen ce If a collision occurs within 64 byte times the retry process is initiated.
Initializati on Sequence MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 14-45 Non-Octet Error (Dribbling Bi ts) — The Ethernet controller handles up to se ven dribbling bits when the receive frame terminates nonoc tet aligned and it checks the CRC of the frame on the last octet b oundary .
Fast Ethernet Contr oller ( FEC ) Notes MPC5200B Users Guide, Rev . 1 14-46 F reescale Semiconductor.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-1 Chapter 15 Pr ogrammable Serial Contr oller ( PSC) 15.1 Overview The following sections are contained in this document: • Section 15.2, PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x26 00, 0x2800, 0x2C00 • Section 15.
MPC5200B Users Guide, Rev . 1 15-2 F reescale Semiconductor Overview 15.1.1 PSC Functions Overview The PSC module of the MPC5200 provide different groups of interfaces to connect the MPC5200 to other devices. Figure 15-1. shows the groups of interfaces: Figure 15-1.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-3 PSC detect a “codec not re ady” status the PSC will stop se nding and receiving data. In the e nhanced AC97 mode, only the data slots must be in the FIFO. The PSC genera te the slot0,1 and slot2 values depend on data to send.
MPC5200B Users Guide, Rev . 1 15-4 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 • Selectable pulse wi dth: either 3/16 bit duration or 1.6 µ s IrDA MIR mode: • Baud rate: 0.576 Mbps to 1.152 Mbps IrDA FIR mode: • Baud rate: 4 Mbps 15.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-5 PSC module operation is controlled by writing c ontrol bytes into the appropriate registers. 15.2.1 Mode Regi ster 1 (0x00) — MR1 The Mode registers control configuration.
MPC5200B Users Guide, Rev . 1 15-6 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 T able 15-4. Mo de Register 1 (0x00) f or SIR Mode m s b 0 123456 7 l s b R RxR TS RxIRQ/FFUL L Reser v ed W R E S E T : 00110011 T able 15-5.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-7 15.2.2 Mode Regi ster 2 (0x00) — MR2 MR2 can be read or written when th e Mode register pointe r points to it, which occurs after any a ccess to MR1 .
MPC5200B Users Guide, Rev . 1 15-8 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 15.2.3 Status Register (0x04) — SR The read-only SR register shows status of the transmitter , the receiver , and the FI FO.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-9 T able 15-12. Sta tus Register (0x04) f or MIR / FIR Mode m s b 0 .
MPC5200B Users Guide, Rev . 1 15-10 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 3 ORERR Overrun Error Indicates whet her an ov errun occurs. F or pur poses of o verrun, FIFO full means all FIFO space is occupied; the Rx FIFO threshold is irrelev ant to overrun.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-11 NO TE The FIFO related status bits ORERR, URERR, Rx RDY , FFUL and TxRDY will be changed only if the peripheral (transmi tter or receiver) access the FIFO.
MPC5200B Users Guide, Rev . 1 15-12 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 15.2.4 Cloc k Select Register (0x04) — CSR The MPC5200B supports only the internal clock as source for th e UAR T / SIR clock generation.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-13 T able 15-16. Command Re gister (0x08) f or all Modes msb 0 1 2 3.
MPC5200B Users Guide, Rev . 1 15-14 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 4 : 5 00 no acti on taken Causes Tx to sta y in current mode. • I f Tx is enabled, it remains enabled. • I f Tx is disabled, it re mains disabled.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-15 15.2.6 Rx Buffer Register (0x0C) — RB Data are read from the Rx FIFO by reading from this read-only regi ster. The Rx FIFO s ize i s 512 bytes.
MPC5200B Users Guide, Rev . 1 15-16 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 15.2.7 Tx Buffer Register (0x0C) — TB Data is written to the Tx FIFO by writing to this write-only register . The Tx FIFO size is 512 bytes.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-17 15.2.8 Input P ort C hang e Register (0x10) — IPCR The read-only IPCR register shows the current state and change-of-state for th e Modem control input port.
MPC5200B Users Guide, Rev . 1 15-18 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 15.2.9 A uxiliary Control Register (0x10) — AC R The write-only ACR register controls Tx / Rx handshaking. Bit Name Description 0 SYNC Codec —Sy nc detected .
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-19 15.2.10 Interrupt Stat us Register (0x14) — ISR The read-only ISR register provides stat us for all potential interrupt sources.
MPC5200B Users Guide, Rev . 1 15-20 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 15.2.11 Interrupt M ask Register (0x14) — IMR The write-only IMR register se lects corresponding bits in the ISR that cause an interrupt.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-21 T able 15-28. Inte rrupt Mask Register (0x14) f or U AR T / SIR M.
MPC5200B Users Guide, Rev . 1 15-22 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 15.2.12 Counter Timer Upper Register (0x18) — CTUR This write-only register holds the upper byt es of the preload value used by the time r to provide a given Baud rate.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-23 15.2.13 Counter Timer Lower Register (0x1C) — CTLR This write-only register hold the lower byte s of the preload value used by the timer to provide a given Baud rate.
MPC5200B Users Guide, Rev . 1 15-24 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 R F rameSyncDiv[0:7] BitClkDiv[8:15] W msb 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb R BitClkDiv[0:7] Reser ved W R E S E T : 000000000 0 0 0 00 0 0 T able 15-33.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-25 The Mclk frequency is generated in the Clock Di stribution Module.
MPC5200B Users Guide, Rev . 1 15-26 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 15.2.15 A C97 Slots Regi ster (0x24)—A C97Slots This write only register defines which slot s are expected in a receive AC97 frame and which slots will be send in a AC97 TX fra me.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-27 15.2.17 A C97 Status Data Register (0x2C)—A C97Data This read-only register contains the rece ived response of a AC97 read command.
MPC5200B Users Guide, Rev . 1 15-28 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 15.2.19 Input P or t Register (0x34) — IP This read-only IP register shows th e current state of the input ports. T able 15-38.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-29 15.2.20 Output P or t 1 Bit Set (0x38) — OP1 This is a write-on ly regist er . Output ports are asserted by writing to this register .
MPC5200B Users Guide, Rev . 1 15-30 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 15.2.22 Serial Interface Control Register (0x40) — SICR This register sets the main operation mode. 6 RES Asser t RES output.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-31 3 SHDIR Codec —Shift Direction. 0 = msb first 1 = lsb first other Modes —Reserved 4: 7 SIM [3 : 0 ] PSC o peration mode.
MPC5200B Users Guide, Rev . 1 15-32 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 13 Cell2xClk Codec —Cell Slave 2x Clo c k F requency - takes eff.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-33 15.2.23 Infrared Cont rol 1 (0x44)—IRCR1 This register controls the configurati on in one of the IrDA modes (SIR/MIR/FIR).
MPC5200B Users Guide, Rev . 1 15-34 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 15.2.25 Infrared SIR Divide Register (0x4C)—IRSDR This register set the SIR p ulse width. T o set the SIR mode Baud rate see Section 15.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-35 15.2.26 Infrared MIR Divide Register (0x50)—IRMDR This register set the MIR mode Baud rate. This register is reserved in other modes.
MPC5200B Users Guide, Rev . 1 15-36 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 15.2.27 Infrared FIR Divi de Register (0x54)—IRFDR This register set the FIR mode Baud rate. Th is register is rese rved in other modes.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-37 Bit Name Description 0:3 — Reserved 4:7 F _ F D I V FIR —Clock divide ratio in FIR mode. The bit frequency is derived by: This bit frequency should be 8 MHz.
MPC5200B Users Guide, Rev . 1 15-38 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 15.2.28 Rx FIFO Number of Data (0x58) — RFNUM 15.2.29 Tx FIFO Number of Data (0x5C) — TFNUM 15.2.30 Rx FIFO Data (0x60) — RFD A T A Read - write registe r to access the internal RX FIFO Data register .
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-39 15.2.32 Rx FIFO Control (0x68)—RFCNTL 15.2.33 Rx FIFO Alarm (0x6E)—RF ALARM Bit Name Description 0:3 — R e s e r v e d 4 : 7 F rame [ 3 : 0 ] Fr ame indicator.
MPC5200B Users Guide, Rev . 1 15-40 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 15.2.34 Rx FIFO Read P ointer (0x72)—RFRPTR 15.
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-41 15.2.37 Rx FIFO Last Write Frame PTR (0x7C)—RFL WFPTR 15.2.38 Tx FIFO Data (0x80)—TFD A T A Read - write register to acce ss the internal TX FIFO Data regist er .
MPC5200B Users Guide, Rev . 1 15-42 F reescale Semiconductor PSC Registers—MB AR + 0x200 0, 0x2200, 0x2400, 0x260 0, 0x2800, 0x2C00 15.2.40 Tx FIFO Control (0x88)—TFCNTL 15.2.41 Tx FIFO Alarm (0x8E)—TF ALARM 15.2.42 Tx FIFO Read P ointer (0x92)—TFRPTR 14 ALARM The FIFO is requesting ser vice from either BestComm or CPU .
PSC Registers—MB AR + 0x2000, 0x22 00, 0x2400, 0 x2600, 0x2800, 0x2C00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-43 15.2.43 Tx FIFO Write P ointer (0x96)—TFWPTR 15.
MPC5200B Users Guide, Rev . 1 15-44 F reescale Semiconductor PSC Operation Modes 15.3 PSC Operat ion Modes This section describes the different PSC operation modes including the pin muxing, the module config uration, sign al definition and some programming examples.
PSC Operation Modes MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-45 Figure 1-1 PSC UART Block Diagram An internal interrupt request signal (IRQ ) is provided to notify the Interrupt Controller of an interrupt condition. The output is the logical NOR of unmasked ISR bits.
MPC5200B Users Guide, Rev . 1 15-46 F reescale Semiconductor PSC Operation Modes Figure 15-2. Sign al configuration f or a PSC / RS-232 interface 15.3.
PSC Operation Modes MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-47 After the stop bits are sent, if no new character is in the Tx holding register , the TxD output remains high ( mark condition ) a nd t he Tx empty bit, SR [ TxEMP ], is set.
MPC5200B Users Guide, Rev . 1 15-48 F reescale Semiconductor PSC Operation Modes Figure 15-5. Timing Dia gram—Receiver When the receiver detects a high-to-lo w ( mark-to-space ) transition of the sta rt bit on RxD, the state of RxD is sampled.
PSC Operation Modes MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-49 15.3.2 PSC in Codec Mode After reset all PSCs ar e in UAR T mode. PSC1 ,2,3 and 6 can be put to one of the Code c modes by writing the appropriate value to the SICR register .
MPC5200B Users Guide, Rev . 1 15-50 F reescale Semiconductor PSC Operation Modes 15.3.2.1 Bloc k Diagram and Signal Definition f or Codec Mode Figure 15-6.
PSC Operation Modes MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-51 15.3.2.2 Codec Cloc k and FrameSync Generation The serial BitClk and the Fram eSync can either be inputs that com e fr.
MPC5200B Users Guide, Rev . 1 15-52 F reescale Semiconductor PSC Operation Modes The source for the internal clock generatio n is the MclkDiv clock divider in CDM modul e. The CDM provides for each Codec PSC (1 , 2, 3 and 6) a separate Mclk and MclkDiv clock divider .
PSC Operation Modes MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-53 • Data shift direction SICR [SHDIR], data shifted out LSB first if SICR [SHDIR] = 1 otherwise data shi fted out MSB first if SICR [SHDIR] = 0 In the Codec “Soft Modem” mode the PSC send only one data word per frame.
MPC5200B Users Guide, Rev . 1 15-54 F reescale Semiconductor PSC Operation Modes • FrameSync is low true • lsb first, transfer starts one cycle after the leading ed ge of FrameSync • set Mclk fr.
PSC Operation Modes MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-55 Figure 15-10. ESAI Dat a T ransmiss ion T able 15-8 0 shows an example how to configure the PSC1 as ESAI master . For t he slave mode the bit SICR [GenClk] must be cleared and the configuration of the CCR register can be ignored.
MPC5200B Users Guide, Rev . 1 15-56 F reescale Semiconductor PSC Operation Modes 15.3.2.5 T ransmitting and Receiving in “Cell Phone” Mode The transmission protocol for the “Cell Phone ” mode is the same like in the “Soft M odem” mode.
PSC Operation Modes MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-57 15.3.2.6 T ransmitting and Receiving in I2S Maste r Mode The next support mode is the I2S mode. Th e I2S tra nsmission is similar to the “Soft Modem” mode. Therefore the configuration is the sa me like described in Section 15.
MPC5200B Users Guide, Rev . 1 15-58 F reescale Semiconductor PSC Operation Modes Figure 15-1 2. I2S-Data T ransmission T able 15-8 4 shows an example how to configure the PSC1 as I2S master . Fo r the slave mode the bit SICR [GenClk] must be cleared and the configuration of the CCR register can be ignored.
PSC Operation Modes MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-59 15.3.2.7 T ransmitting and Receiving in SPI Mode An other available Codec mode is the SPI mode.
MPC5200B Users Guide, Rev . 1 15-60 F reescale Semiconductor PSC Operation Modes Figure 15-13. SPI P arameter T able 15-8 5 shows an exampl e how to configure the PSC3 as SPI master .
PSC Operation Modes MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-61 T able 15-8 6 shows an exampl e how to configure the PSC2 as SPI slave.
MPC5200B Users Guide, Rev . 1 15-62 F reescale Semiconductor PSC Operation Modes 15.3.3.1 Bloc k Diagram and Signal Definition f or A C97 Mode Figure 15-14. PSC A C97 Bloc k Diagram Figure 15-14 shows the simplified PSC Block Diagram for AC97 mode. The BitClk is an input from the exte rnal Codec.
PSC Operation Modes MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-63 Figure 15-15 . PSC - A C97 Interface Figure 15-16 shows the T iming diagram for the AC 97 interface. For more AC97 Controlle r interface inf ormation, see the Audio Codec’97 Component Specification.
MPC5200B Users Guide, Rev . 1 15-64 F reescale Semiconductor PSC Operation Modes Low-power mode can be left through either a warm or cold reset. The CPU doe s a warm reset by setting SICR [ A WR ] for at least 1 µs. This asserts the FRAME frame sync output in AC97 mo de.
PSC Operation Modes MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-65 the slot request for the specif ied slots was active (slot request bit was z ero in the previous frame).
MPC5200B Users Guide, Rev . 1 15-66 F reescale Semiconductor PSC Operation Modes T able 15-90. Signa l Description for IrDa Mode Figure 15-17. PSC SIR Bloc k Diagram 15.3.4.1.2 T ransmitting a nd Receiving in SIR Mode This data format is si milar to the UAR T .
PSC Operation Modes MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-67 15.3.4.1.3 Configuration Se quence Example for SIR Mode The T able 15-91 shows the configuration sequenc es. This list includes the SIR mode rel ated regi sters only , not the othe r configure values like interrupt and FIFO configurations.
MPC5200B Users Guide, Rev . 1 15-68 F reescale Semiconductor PSC Operation Modes Figure 15-19. PSC MIR and FIR Blo ck Diagram For MIR and FIR mode the clock for the transmitter and receiver is generated by dividing down from the internal Mclk or from an external clock.
PSC Operation Modes MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-69 The ST A represents the start of the frame and the STO represents the end of th e frame. Both of ST A and STO are defined as 01 1 11 1 10 in binary format. Like the UAR T mode , the MIR mode sends the lsb firs t.
Programmable Serial C ontr oller ( PSC) Notes MPC5200B Users Guide, Rev . 1 15-70 F reescale Semiconductor 15.3.4.3 PSC in FIR Mode The FIR mode is also a supported IrDA mode.
PSC FIFO System MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-71 NO TE The FIR module doesn’t support the CRC generation. If the transfer r equire a CRC Field use the CRC generation from the Best Comm module. See also Chapter 13, BestComm .
MPC5200B Users Guide, Rev . 1 15-72 F reescale Semiconductor PSC FIFO System Depending on whether the FIFO is set for Tx or Rx, “Alarm” and “Granularity” are m easured differently , either: .
PSC FIFO System MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-73 Figure 15-22. PSC FIFO System 15.4.1 RX FIFO The RX FI FO space is 512 Byte. For an Rx FIFO, the “Alarm” value is not the amount of “data” in the Rx FI FO. Instead, an interrupt occurs as a result of the amount of em pty space remaining in the Rx FIFO.
MPC5200B Users Guide, Rev . 1 15-74 F reescale Semiconductor PSC FIFO System When using BestComm you must specify a non- zero “Granularity” to get FIFO underrun errors. This is due to its internal pipelini ng. BestComm does not imme diately stop accessing the FIFO when the FIFO interrupt goes away .
PSC FIFO System MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 15-75 Figure 15- 24. Local Loop -Back Features of this local loop-back mode are: • T ransmitter and CPU-to-receiver communications continue normally . • RxD input data is ignored.
MPC5200B Users Guide, Rev . 1 15-76 F reescale Semiconductor PSC FIFO System Figure 15-26. Timing Diag ram—Multidrop Mode A character sent from the master stat ion consists of: • a start bit • a.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 16-1 Chapter 16 XLB Arbiter 16.1 Overview This document contains the following section: • Section 16.
MPC5200B Users Guide, Rev . 1 16-2 F reescale Semiconductor Overview Multiple masters at level 0 will only be able to per form one tenure before the bus is passed to the next master at level 0 usin g the LRU algorithm. The priority level of each master may be changed while the arb iter is running.
XLB Arbiter Registers—MBAR + 0x1F00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 16-3 16.1.1.4.2 Other T en ure Ending Conditions In addition to the watchdog timers, this function will te.
MPC5200B Users Guide, Rev . 1 16-4 F reescale Semiconductor XLB Arbiter Registers—MB AR + 0x1F00 T able 16-1. Arbiter Configuration Regist er msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RP L D I S Rsv.
XLB Arbiter Registers—MBAR + 0x1F00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 16-5 NO TE The PLDIS reset value is 1, which means the XLB Arbiter will prohibit tran saction pipelining.
MPC5200B Users Guide, Rev . 1 16-6 F reescale Semiconductor XLB Arbiter Registers—MB AR + 0x1F00 16.2.4 Arbiter Interrupt Enable Register (R/W)—MB AR + 0x1F4C The Arbiter Interru pt Enable Register is used to en able a status bit to cause a n interrupt.
XLB Arbiter Registers—MBAR + 0x1F00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 16-7 16.2.5 Arbiter Address Capture Register (R)—MB AR + 0x1F50 The Arbiter Address Capture Register cap.
MPC5200B Users Guide, Rev . 1 16-8 F reescale Semiconductor XLB Arbiter Registers—MB AR + 0x1F00 16.2.6 Arbiter Bus Signal Capt ure Register (R)—MB AR + 0x1F54 The Arbiter Bus Signal Capture Regis.
XLB Arbiter Registers—MBAR + 0x1F00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 16-9 16.2.8 Arbiter Data T enure Time -Out Register (R/W)—MB AR + 0x1F5C The Arbiter Data T enure Time-out Register p rovides an expiration value to the arbiter watchdog for da ta tenures.
MPC5200B Users Guide, Rev . 1 16-10 F reescale Semiconductor XLB Arbiter Registers—MB AR + 0x1F00 16.2.10 Arbiter Master Priority En able Register (R/W)—MB AR + 0x1F64 The Arbiter Master Priority Enabl e Register determines whether the arbiter uses the hard-wired or software programmable priorit y f or a master .
XLB Arbiter Registers—MBAR + 0x1F00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 16-11 16.2.11 Arbiter Master Priority Register (R/W)—MB AR + 0x1F68 The Arbiter Ma ster N Priority Register is used t o set the softwa re-programmable prior ity of each master .
MPC5200B Users Guide, Rev . 1 16-12 F reescale Semiconductor XLB Arbiter Registers—MB AR + 0x1F00 16.2.12 Arbiter Snoop Windo w Register (R W)—MB AR + 0x1F70 The Arbiter Snoop W indow Register is used by the PCI, BestComm, and USB Ho st interfaces to the XLB.
XLB Arbiter Registers—MBAR + 0x1F00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 16-13 16.2.13 Arbiter Reserved Registers— MB AR + 0x1F00-1F3C, 0x1F74-1FFF These are reserved register s and should not be accessed. 25:26 — Reser ved 27:31 WINSIZE Window Siz e - Defines the size of window .
XLB Arbiter Notes MPC5200B Users Guide, Rev . 1 16-14 F reescale Semiconductor.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 17-1 Chapter 17 Serial P eripheral Interface ( SPI ) 17.1 Overview The following sections are contained in this document: • Section 17.2, SPI Signal Description • Section 17.3, SPI Registers—MBAR + 0x0F00 • Section 17.
MPC5200B Users Guide, Rev . 1 17-2 F reescale Semiconductor SPI Signal Description 17.1.2 Modes of Operation The SPI functions in the followi ng three modes: • Run Mode —The normal mode of operation. • Wa i t M o d e —The SPI can be configured to operate in low-power mode.
SPI Registers—MB AR + 0x 0F00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 17-3 The SS pin is the mode fault inpu t when the SPI is in master mode and the asso ciated data di rection bit is clear . When the data direc tion bit is clear and SSOE = 1, the SS pin is a general-purpose input.
MPC5200B Users Guide, Rev . 1 17-4 F reescale Semiconductor SPI Registers—MB AR + 0x0F00 17.3.2 SPI Control R egister 2—MB AR + 0x0F01 6 SSOE Slav e Select ( SS ) Output Enable—bit is enab led only in ma ster mode by asser ting SSOE and SPIDDR bit 3 as sho wn in T able 17-3 .
SPI Registers—MB AR + 0x 0F00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 17-5 17.3.3 SPI Baud Rate Register—MB AR + 0x0F04 The SPI baud rate is derived from the IPB clock.
MPC5200B Users Guide, Rev . 1 17-6 F reescale Semiconductor SPI Registers—MB AR + 0x0F00 17.3.4 SPI Status Re gister —MB AR + 0x0F05 T able 17-7. SPI Baud Rat e Selection SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 SPI Module Clock Divisor Baud Rate IPB 33.0 MHz Baud Rate IPB 66.
SPI Registers—MB AR + 0x 0F00 MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 17-7 17.3.5 SPI Data Register—MB AR + 0x0F09 17.3.6 SPI P ort Data Register—MBAR + 0x0F0D 17.
MPC5200B Users Guide, Rev . 1 17-8 F reescale Semiconductor Functional Des cription 17.4 Function al Description 17.4.1 General The SPI module allows full-duplex, synchronous , serial communication between the MCU a nd peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 17-9 The SS pin is normally an input which should remain in the inacti ve high state.
MPC5200B Users Guide, Rev . 1 17-10 F reescale Semiconductor Functional Des cription Figure 17-2. Ma ster/Slave T ransfer Blo ck Diagram 17.4.4.1 Cloc k Phase and P olarity Controls Using two bits in the SPI control register 1, software selects one of four combinat ions o f serial clock phase and polarity .
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 17-11 Figure 17-3. SPI Cloc k Format 0 (CPHA = 0) In slave mode, if the SS line is not deas serted between the successive transmissions then the conten t of the SPI Data Register is not tra nsmitted, instead the last recei ved byte is transmitted.
MPC5200B Users Guide, Rev . 1 17-12 F reescale Semiconductor Functional Des cription signal is the output from the master . The SS li ne is the slave select input to the slav e. The SS pin of the master must be eith er high or reconfigured as a general-purpos e outpu t not affecting the SPI.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 17-13 Figure 17-5. Baud Rate Divisor Equation 17.4.6 Special Features 17.4.6.1 SS Output The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high dur ing idle to deselect external devices.
MPC5200B Users Guide, Rev . 1 17-14 F reescale Semiconductor Functional Des cription 17.4.7 Error Conditions The SPI has two error conditions: • Write collision error • Mode fault error 17.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 17-15 NO TE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Eve n though the shift register will continue to operate, the rest of the SPI is shut down (i.
MPC5200B Users Guide, Rev . 1 17-16 F reescale Semiconductor Functional Des cription.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 18-1 Chapter 18 Inter -Integrated Circuit ( I 2 C) 18.1 Overview The following sections are contained in this document: • Section 18.2, I 2 C Contr oller • Section 18.3, I 2 C Interface Registers • Section 18.
MPC5200B Users Guide, Rev . 1 18-2 F reescale Semiconductor I 2 C Controller Figure 18-1. Bloc k Diagram—I 2 C M odule 18.2 I 2 C Contr oller The I 2 C has simple bidirectional two-wire bus for efficient in ter-IC c ontrol.
I 2 C Controller MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 18-3 The master termi nates communicati on by generating a STOP signal, which frees the bus. The master can gener ate a STOP even if th e slave has generated an acknowledg e, at which point the sl ave must release the bus.
MPC5200B Users Guide, Rev . 1 18-4 F reescale Semiconductor I 2 C Controller Figure 18-4. Timing Diagram—Receiv er Acknowledgement 18.2.2.4 Repeated Start A repeated ST AR T signal is a ST AR T signal generated without first generating a STOP signal to terminate the communication.
I 2 C Interface Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 18-5 Figure 18-6. Timing Dia gram—Clock Synchr onization A data arbitration procedure det ermines the relative priority of contending masters. A bus master lose s arbitrati on if it trans mits logic “1” while another master transmit s logic “0”.
MPC5200B Users Guide, Rev . 1 18-6 F reescale Semiconductor I 2 C Interface Registers 18.3.1 I 2 C Address Register (MAD R)—MB AR + 0x3D00 / 0x3D40 18.3.2 I 2 C Frequency Divider Register (MFDR)—MB AR + 0x3D04 / 0x3D44 The Frequency Divide register de termines the SCL or serial bit-clock frequency .
I 2 C Interface Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 18-7 Timing Diagram—SCL Period and SDA Hold Time Figure 18-8. Timing Dia gram of I2C Signal Relationships For standard mode I2C, the I2C specification st ates that (SCL <= 100 kHz) AND (0.
MPC5200B Users Guide, Rev . 1 18-8 F reescale Semiconductor I 2 C Interface Registers 1. Identify all rows of T able 18-4 where SCL Period satisfie s criteria (5). This set of rows limit s the choices of SCL allowe d for this particular sy stem clock.
I 2 C Interface Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 18-9 00 000 011 144 25 70 73 00 000 100 288 49 142 145 00 000 101 576 97 286 289 00 000 110 1152 193 574 577 00 000 11.
MPC5200B Users Guide, Rev . 1 18-10 F reescale Semiconductor I 2 C Interface Registers 00 101 110 768 65 382 385 00 101 111 1536 129 766 769 00 110 000 24 8 8 13 00 110 001 36 9 14 19 00 110 010 64 13.
I 2 C Interface Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 18-11 01 011 001 136 26 60 70 01 011 010 256 42 116 130 01 011 011 480 66 236 242 01 011 100 960 1 30 476 482 01 011 1.
MPC5200B Users Guide, Rev . 1 18-12 F reescale Semiconductor I 2 C Interface Registers 10 or 11 000 100 1152 196 568 580 10 or 11 000 101 2304 388 1144 115 6 10 or 11 000 110 4608 772 2296 230 8 10 or.
I 2 C Interface Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 18-13 18.3.3 I 2 C Contr ol Register (MCR )—MBAR + 0x3D08 / 0x3D48 10 or 11 101 111 6144 516 3064 307 6 10 or 11 110.
MPC5200B Users Guide, Rev . 1 18-14 F reescale Semiconductor I 2 C Interface Registers Bit Name Description 0E N I 2 C Enable—bit controls softw a re reset of entire I 2 C module.
I 2 C Interface Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 18-15 18.3.4 I 2 C Status Register (MSR )—MB AR + 0x3D0C / 0x3D4C T able 18-6.
MPC5200B Users Guide, Rev . 1 18-16 F reescale Semiconductor I 2 C Interface Registers 18.3.5 I 2 C Data I / O Register (M DR)—MBAR+ x3D10 / 0x3D50 5 SRW Sla ve Read / Write—when set, bit indicates the R / W command bit value of the calling address sent from the master .
I 2 C Interface Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 18-17 18.3.6 I 2 C Interrupt Contr ol Register—MBAR + 0x3D20 The Interrupt Control register is common to both MPC5200B I 2 C modules. Each module generates an intern al interrupt that can be routed as follows: • T o the CPU interrupt, if IE is set to 1.
MPC5200B Users Guide, Rev . 1 18-18 F reescale Semiconductor I 2 C Interface Registers • T o the RX requestor at SDMA, if RE is set to 1. T ypically , only one (or none) of the above des tinations would be specified. Althou gh, it may be useful to send an interrupt to both the CPU and SDMA.
Initializati on Sequence MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 18-19 An I2C glitch filter has been added outside the I2C legacy modules (but within the I2C package). This filter can absorb (or “ea t”) glitches on both the I2C clock and da ta lines for each I 2 C module.
MPC5200B Users Guide, Rev . 1 18-20 F reescale Semiconductor T ransfer Initiation and In terrupt 18.5.3 Special Note on AKF A new status bit has been added to MSR[4] fo r the MPC5200B release of this chip.
T ransfer Initiation and Interrupt MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 18-21 Figure 18-9. Software Flo wchart of T ypical I2C Interrupt Routine Clear Master Mode ? Tx/Rx ? Last Byt.
MPC5200B Users Guide, Rev . 1 18-22 F reescale Semiconductor T ransfer Initiation and In terrupt.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-1 Chapter 19 Contr oller Area Network ( MSCAN ) 19.1 Overview The following sections are contained in this document: • Section 19.1, Overview • Section 19.2, Featur es • Section 19.
MPC5200B Users Guide, Rev . 1 19-2 F reescale Semiconductor Features 19.2 Features The basic features of the MSCAN are as follows: • Implementation of the CAN protocol - V ersion 2.
Memory Map / Register Definition MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-3 Figure 19-2. The CAN System 19.5 Memor y Map / Register Definition The MPC5200B contains 2 inde pendent MSCAN Controller : • MSCAN1 = MBAR + 0x0900 • MSCAN2 = MBAR + 0x0980 19.
MPC5200B Users Guide, Rev . 1 19-4 F reescale Semiconductor Memory Map / Regi ster Definition T able 19-1 shows the individual regist ers associ ated with the MSCAN and their relative of fset from the base address. The detailed reg iste r descriptions follow in the order they app ear in the register map (see T able 19-2 ).
Memory Map / Register Definition MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-5 19.5.2 Register Descriptions This section describes in detail all the re gisters and register bits in the MSCAN module. Each desc ription includes a standard register diagram with an associated figure number .
MPC5200B Users Guide, Rev . 1 19-6 F reescale Semiconductor Memory Map / Regi ster Definition Bit Name Description 0 RXFRM Received F rame—flag bit is rea d and clear only . It is set when a receiver has received a valid message correctly , independently of the filter c onfiguration.
Memory Map / Register Definition MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-7 19.5.4 MSCAN Contr ol Register 1 (CANCTL1)—MBA R + 0x0901 / 0x981 The MSCAN Control Register 1 provides for various control and ha ndshake status information of the MSCAN mod ule.
MPC5200B Users Guide, Rev . 1 19-8 F reescale Semiconductor Memory Map / Regi ster Definition 19.5.5 MSCAN Bus Timing Register 0 (CANBTR0)—MB AR + 0x0904 / 0x984 The MSCAN Bus T iming Register 0 provides for va rious bus timing control of the MSCAN module.
Memory Map / Register Definition MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-9 19.5.6 MSCAN Bus Timing Register 1 (CANBTR1)—MB AR + 0x0905 / 0x985 The MSCAN Bus T iming Register 1 provides for va rious bus timing control of the MSCAN module.
MPC5200B Users Guide, Rev . 1 19-10 F reescale Semiconductor Memory Map / Regi ster Definition 19.5.7 MSCAN Receiver Flag Register (CAN RFLG)—MB AR+0x0908 / 0x988 Note: This register is held in th e reset state when the initialization mode is acti v e (INI TR Q = 1 and INIT AK = 1).
Memory Map / Register Definition MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-11 Bit Name Description 0 WUPIF W akeUp Interrupt Flag—If MSCAN dete cts bu s activity whi le in sleep mode and WUPE=1 in CANTCTL0, it sets the WUPIF flag. If not masked, a W akeUp interrupt is pendin g while this flag is set.
MPC5200B Users Guide, Rev . 1 19-12 F reescale Semiconductor Memory Map / Regi ster Definition 19.5.8 MSCAN Receiver Interr upt Enable Register (C ANRIER)—MB AR + 0x0909 / 0x989 7 RXF Receive Buff er Full—fl ag is set b y MSCAN when a new message is shifted into RX FIFO.
Memory Map / Register Definition MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-13 Note: The MSCAN Receive Interrupt Enable Register is held in reset state when the initi alization mode is activ e (INITRQ = 1 and INIT AK = 1). This register is wr itable again as soon as the initialization mode is e xited (INITRQ = 0 and INIT AK = 0).
MPC5200B Users Guide, Rev . 1 19-14 F reescale Semiconductor Memory Map / Regi ster Definition 19.5.10 MSCAN T ransmitter In terrupt Enable Register (CANTIER)—MB AR+0x090D / 0x098D Note: This register is held in th e reset state when the initialization mode is acti v e (INI TR Q = 1 and INIT AK = 1).
Memory Map / Register Definition MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-15 19.5.12 MSCAN T ransmitter Message Abor t Ack (CAN T AAK)—MBAR +0x0911 / 0x0991 Note: This register is held in the reset state when the init ialization mode is active (INITRQ = 1 and INIT AK = 1).
MPC5200B Users Guide, Rev . 1 19-16 F reescale Semiconductor Memory Map / Regi ster Definition 19.5.14 MSCAN ID Acceptanc e Control Register (CANI D A C)—MB AR + 0x0915 / 0x0995 READ: Anytime WRITE: Anytime in Initialization Mode (INITRQ = 1 and INIT AK =1) T able 19-17.
Memory Map / Register Definition MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-17 19.5.15 MSCAN Receive Error Counter Re gister (CANRXERR)-M B AR + 0x091C / 0x099C READ: Only when in Sleep Mode (SLPRQ = 1 and SLP AK = 1) or Initializa tion Mode (INITRQ = 1 and INIT AK =1).
MPC5200B Users Guide, Rev . 1 19-18 F reescale Semiconductor Memory Map / Regi ster Definition 19.5.17 MSCAN ID Accept ance Registers (CANID AR0 -7)—MB AR + 0x0920 / 0x09A0 T able 19-22.
Memory Map / Register Definition MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-19 READ: Anytime WRITE: Anytime in initialization m ode (INITRQ + 1 and INIT AK = 1). On reception, each messag e is written into the background receive buffer .
MPC5200B Users Guide, Rev . 1 19-20 F reescale Semiconductor Memory Map / Regi ster Definition 19.5.18 MSCAN ID Mask Register (CANIDMR0-7)—MB AR + 0x0928 / 0x09A8 T able 19-24.
Memory Map / Register Definition MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-21 READ: Anytime WRITE: Anytime in initialization m ode (INITRQ + 1 and INIT AK = 1). The identifier mask register sp ecifies which of the corresponding bits in the iden tifier acceptance register are relevant for a cc eptance filtering.
MPC5200B Users Guide, Rev . 1 19-22 F reescale Semiconductor Programmer’ s Model of Messa g e Storage — CANIDMR7 19.6 Programmer’ s Model o f Messa g e Storage The following sec tion details th e organization of the receive and transmit message buf fers and the associated control registers .
Programmer’ s Model of Message Storage MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-23 Read: anytime for transmit buf fers; only when RXF flag is set for receive buffers (see Section 1 9.5.7, MSCAN Receiver Flag Register (CANRFLG)—MBAR+0x0908 / 0x988 ).
MPC5200B Users Guide, Rev . 1 19-24 F reescale Semiconductor Programmer’ s Model of Messa g e Storage 19.6.1 Identifier R egister s (IDR0-3) The identifier registers for an extended form at identifier consist of a total of 32 b its; ID28 - ID0, SRR, IDE, and R TR bits.
Programmer’ s Model of Message Storage MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-25 19.6.3 Data Length R egister (DLR) This register keeps the data length field of the CAN frame. DLC3 - DLC0 — Data Length Code bits The data length code contains the number of bytes (data byte count) of the respectiv e message.
MPC5200B Users Guide, Rev . 1 19-26 F reescale Semiconductor Functional Des cription 19.6.5 MSCAN Time Stam p Register High (TSRH)— MBAR + 0x097C / 0x09FC READ: Anytime WRITE: Unimplemented 19.6.6 MSCAN Time Stamp Regist er Low (TSRL)—MB AR + 0x097D / 0x09FD READ: Anytime WRITE: Unimplemented 19.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-27 19.7.2 Message Storage Figure 19-3. User Model f or Message Buffer Or ganization MSCAN facilitates a sophist icated message storage system whic h addresses the requirements of a broad range of network applicati ons.
MPC5200B Users Guide, Rev . 1 19-28 F reescale Semiconductor Functional Des cription A double buffer scheme de-couples the reloading of the transmit buf fer from the actual message se nding and, as such, reduces th e reactiveness requirements on the CPU.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-29 flag, and generates a receive interrupt Section 19.7.9.2, Rece ive Interrupt to the CPU 1 .
MPC5200B Users Guide, Rev . 1 19-30 F reescale Semiconductor Functional Des cription Figure 19-4. 3 2-bit Maskable Id entifier Acceptance Filter Figure 19-5.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-31 Figure 19-6. 8- bit Maskable Identi fier Acceptance Filte rs 19.7.4 Protocol Viol ation Pr otection The MSCAN protects the user from accidentally violating the C AN protocol through programming errors.
MPC5200B Users Guide, Rev . 1 19-32 F reescale Semiconductor Functional Des cription • All registers which control the configura tion of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode. The corre sponding INITRQ/INIT AK handshake bits in th e CANCTL0/CANCTL1 registers Section 19.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-33 • Time Segment 2: T his segment represents the PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long. Figure 19-8.
MPC5200B Users Guide, Rev . 1 19-34 F reescale Semiconductor Functional Des cription 19.7.6 Timer Link The MSCAN generates an internal tim e stamp whenever a valid frame is received or transm itted and the TIME bit is enabled.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-35 19.7.8.1 CPU Run Mode As can be seen in T able 19-35 , only MSCAN Sleep Mode is available as lo w power option, when CPU is in run mode.
MPC5200B Users Guide, Rev . 1 19-36 F reescale Semiconductor Functional Des cription NO TE The MCU cannot clear the SLPRQ bit before Sleep Mode (SLPRQ =1 and SLP AK=1) is active. After wake-up, the MSCAN wa its for 11 consecutive recessive bits to synchroniz e to the bus.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-37 Figure 19-11. Initialization Request /Acknowle dg e Cycl e Due to independent clock domains within th e MSCAN the INITRQ has to be synchronized to all domains by using a special handshake mechanism.
Controller Area Network ( MSCAN ) Notes MPC5200B Users Guide, Rev . 1 19-38 F reescale Semiconductor 19.7.9.1 T ransmit Interrupt At least one of the three transmit buf fers is empty (not scheduled) an d can be loaded to schedule a message for transmission.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 19-39 19.7.9.4 Error Interrupt An overrun of the receiver FIFO, error, warning or Bus-Off cond ition occurred.
MPC5200B Users Guide, Rev . 1 19-40 F reescale Semiconductor Functional Des cription.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-1 Chapter 20 Byte Data Link Contr oller (BDLC) 20.1 Overview The BDLC module is a serial communicati on module which allows the user to send and receive messages across a Society of Automot ive Engineers (SAE) J1850 serial communication network .
MPC5200B Users Guide, Rev . 1 20-2 F reescale Semiconductor Modes of Operation Figure 20-1. BDLC Operating Mode s State Diagram • Power Off This mode is entered from the Reset mo de whenever the BDLC module supply voltage V dd drops below its minimum specified value for the BDLC module to gua rantee operation.
Modes of Operation MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-3 •R u n This mode is entered from the BDLC Disabl ed mode when the BDLCE bit in the BDLC Control Re gister is set. It is entered from the BDLC W ait mode whenever activity is sensed on the J1850 bus or some other MCU sou rce wa kes the CPU out of W ait mode.
MPC5200B Users Guide, Rev . 1 20-4 F reescale Semiconductor Block Diagram • Low Power Options The BDLC module can save power in Disabled, W ait, and S top m odes. A complete desc ription of what the BDLC module does while in a low power mode can be found in Section 20.
Signal De scription MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-5 and reception. The MUX Interface provides the link between the BD LC digital section and the anal og Physical Inte rface. Th e wave shaping, driving and digitizing of data is performed by the Physical Interface.
MPC5200B Users Guide, Rev . 1 20-6 F reescale Semiconductor Memory Map and Registers READ: any time WRITE: IMSG , IE, and WCM any time. CLKS write once in normal and emulation modes. CLKS bit has modified functiona lity in spec ial test mode. W rites to unimplemented bits 5-2 are ignored.
Memory Map and Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-7 1 = S top BDLC internal clocks dur ing CPU wait mode (BDLC_STOP) 0 = Run BDLC internal clocks dur ing CPU wait mode (BDLC_W AIT) 20.
MPC5200B Users Guide, Rev . 1 20-8 F reescale Semiconductor Memory Map and Registers If the CPU executes a STOP all cloc ks to the BDLC as well as th e clocks in the MCU are turned off including clocks to the BDLC. The message which generates a W ake-up interrupt of th e BDLC and the CPU will not be received correctly .
Memory Map and Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-9 0 = When cleared, digital filter input is connected to receive pin (RXB) and the transm itter output is conne cted to the transmi t pin (TXB). The BDLC module is taken out of Digital Loopback Mode and can now drive and receive from the J1850 bus normally .
MPC5200B Users Guide, Rev . 1 20-10 F reescale Semiconductor Memory Map and Registers The BDLC supports the In-frame Re sponse (IFR) feature of J1850 by setting these bits co rrectly .
Memory Map and Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-11 After the byte in the BDLC Data Register has been loaded into the transmit shift register , the TDRE flag will be set in t he BDL C State V ector Register register , similar to th e main message transmit sequence.
MPC5200B Users Guide, Rev . 1 20-12 F reescale Semiconductor Memory Map and Registers NO TE The extra logic 1s are an enhancement to the J 1850 protocol which forces a byte boundary condition fault. This is helpful in preventing noise on the J1850 bus from corrupting a message.
Memory Map and Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-13 READ: any time WRITE: write once in normal and emulation modes. Register functionality modifi ed in special test mode. W rites to unimplemented bits 7, 5 are ignored.
MPC5200B Users Guide, Rev . 1 20-14 F reescale Semiconductor Memory Map and Registers 20.7.3.6 BDLC Rate Select Regi ster (DLCBRSR) - MB AR + 0x1309 This register deter mines the divider prescaler value for the mux interface clock (f bdlc ). Only integer multiple of the 1 MHz or 1.
Memory Map and Registers MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-15 20.7.3.7 BDLC Contr ol Register (DLCSCR) - MBAR + 0 x130C The following register enables the BLDC module. READ: any time WRITE: any time BDLCE — BDLC Enabl e (Bit 4) This bit serves as a mux int erface clock (f bdlc ) enable/disable for power savings.
MPC5200B Users Guide, Rev . 1 20-16 F reescale Semiconductor Functional Des cription READ: any time WRITE: ignored in normal and emulation modes Register functionality is modi fied in spec ial test mode. IDLE Idle (Bit 0) This bit indicates when the BDLC module is idle.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-17 Messages transmitted by th e BDLC module onto the J1850 bus must contain at least one data by te, and therefore can be as short a s one data byte and one CRC by te. Each data byte in the me ssage is 8 bits in length, transmitted MSB to LSB.
MPC5200B Users Guide, Rev . 1 20-18 F reescale Semiconductor Functional Des cription Figure 20-5. J 1850 VPW Symbols Each message will begin with an SOF symbol, an active symbol, and therefore each data byte (including the CRC byte) will begin with a passive bit, regardless of whether it is a logic one or a logic zero.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-19 The SOF symbol is defined as passive to active transition followed by an active period 200 µ s in length ( Figure 20-5 (c)) .
MPC5200B Users Guide, Rev . 1 20-20 F reescale Semiconductor Functional Des cription 5 Star t of Fr ame (SOF) T tva3 198 200 20 2 t bdlc 6 End of D ata (EOD) 1 T tvp3 162 16 4 16 6 t bdlc 7 End of F rame (EOF) 1 T tv4 238 240 242 t bdlc 8 Inte r-F rame Separator (IFS) 1 T tv5 298 300 302 t bdlc Note: 1.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-21 T able 20-16. BDLC Receiv er VPW Symbol Timing for Binary Frequenc ies Number Characteristic Symbol Min T yp Max U.
MPC5200B Users Guide, Rev . 1 20-22 F reescale Semiconductor Functional Des cription The min and max symbol lim its shown in the following secti ons (Invalid Passive Bit - V ali d BREAK Symbol) and figures ( Figure 20-6 - Figure 20-9 ) refer to the values list ed in T able 20-13 through T able 20-18 .
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-23 Figure 20-7. J1850 VPW EOF and IFS Symbols • V alid EOF & IFS Symbol In Figure 20-7 (1), if the passive to a.
MPC5200B Users Guide, Rev . 1 20-24 F reescale Semiconductor Functional Des cription Figure 20-8. J185 0 VPW Active Symbols • Invalid Active Bit If the active to passive transition beginning the nex.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-25 • V alid BREAK Symbol If the next active to passive tr an sition does not oc cur until after T rv6(Min) , the current symbol will be considered a valid BREAK symbol.
MPC5200B Users Guide, Rev . 1 20-26 F reescale Semiconductor Functional Des cription 20.8.1.4 J1850 Bus Err ors The BDLC module detects several types of transmit and receive er rors which can occur during the transmission of a message onto the J1850 bus.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-27 If a BREAK symbol is received wh ile the BDLC module is transmitti ng or receiving, the symbol invalid or out of range flag (in BDLC State V ector Register) is set.
MPC5200B Users Guide, Rev . 1 20-28 F reescale Semiconductor Functional Des cription Figure 20-11. BDLC Mo dule Rx Di gital Filter Block Dia gram • Operation The clock for the digital filter is provide d by the MUX Interface clock.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-29 20.8.3.1 Protocol Architect ure The Protocol Handler contains th e S tate Machine, Rx Shadow Register , Tx Shadow Register , R x Shift Register , Tx Shif t Register , and Loopback Multiplexer as shown in Figure 20-12 .
MPC5200B Users Guide, Rev . 1 20-30 F reescale Semiconductor Functional Des cription • Digital Loopback Multiplexer The Digital Loopback Multiplexer connects the input of the receive digital fi lter.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-31 NO TE Due to the byte-level architect ure of the BDLC module, the 12-byte limi t on message length as defined in SAE J1850 must be enforced by the user ’ s software.
MPC5200B Users Guide, Rev . 1 20-32 F reescale Semiconductor Functional Des cription Similar to a loss of arbitration, if any error (ex cept a CRC error) is detected on the SAE J1850 bus during a transmission, the BDLC module will stop transmitting immediately .
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-33 Figure 20-13. Basic BDLC T ransmit Flo w chart 20.8.5 Receiving A Message The design of the BDLC module makes it especi ally easy to use for receiving messages off of the SAE J1850 bus.
MPC5200B Users Guide, Rev . 1 20-34 F reescale Semiconductor Functional Des cription 20.8.5.1 BDLC Reception Contr ol Bits The only control bit which is used for message reception, the IMSG bit, is actually used to prevent message reception.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-35 Once a message byte ha s been received, the CPU must se rvice the BDLC Data Register before the next byte i s received, or the fir st byte will be lost.
MPC5200B Users Guide, Rev . 1 20-36 F reescale Semiconductor Functional Des cription Figure 20-14. Basic BDLC Receive Flo wchart 20.8.6 Transmitting An In-Frame Response (IFR) The BDLC module can be used to transmit all fo ur types of In -Frame Response (IFR) which are de fined in SAE J1850.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-37 20.8.6.1 IFR T ypes Suppor ted b y the BDLC module SAE J1850 defines four distinct t ypes of IFR.
MPC5200B Users Guide, Rev . 1 20-38 F reescale Semiconductor Functional Des cription 20.8.6.3 T ransmit Single Byte IFR The T ransmit Single Byte IFR (TSIFR) bi t in BDLC Control Register 2 is used to transmit T yp e 1 and T ype 2 IFRs onto the SAE J18 50 bus.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-39 • T ransmitting a T ype 1 IFR T o transmi t a T ype 1 IFR, the user loads the byte to b e transm itted into the BDLC Data Regist er and sets both the TSIFR bit and the TEOD bit.
MPC5200B Users Guide, Rev . 1 20-40 F reescale Semiconductor Functional Des cription — Step 1: Load the IFR Byte into the BDLC Data Register As with the T ype 1 IFR, the user begins initiation of a T ype 2 IFR by loading the desired IFR byte in to the BDLC Data Register .
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-41 byte when TEOD is set, the BDLC module will cont inue the trans mission until it is successful or it loses arbitration to another transmitter. At this point it will then discard the byte and make no more transmit attempts.
MPC5200B Users Guide, Rev . 1 20-42 F reescale Semiconductor Functional Des cription The user begins initiation of a T ype 3 IFR, as with each of the other IFR types, by loading the desired IFR byte into the BDLC Data Register .
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-43 Figure 20-1 7. T ransmi tting A T ype 3 IFR 20.8.7 Receiving An In -Frame Response (IFR) Receiving an In-Frame Response wi th the BDLC module is very s imilar to receivi ng a messag e frame.
MPC5200B Users Guide, Rev . 1 20-44 F reescale Semiconductor Functional Des cription NO TE As with a message transmission, the IMSG bit s hould never be used to ignore the BDLC module’ s own IFR transmissions.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-45 . Figure 20-18. Recei ving An IFR With the BDLC module 20.8.7.2 Receiving IFR Exceptions This basic IFR receiving flow can be inte rrupted for the same reasons as a normal message reception.
MPC5200B Users Guide, Rev . 1 20-46 F reescale Semiconductor Functional Des cription Because of the BDLC module’ s architecture , it can both transmit and re ceive messages of unlimited length.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-47 Figure 20-19. Ba sic BDLC Module T ransmit Flowc hart 20.8.9 BDLC Module Initialization This section includes sample flows for initializing the BDLC module and using it to tran smit and receive messages.
MPC5200B Users Guide, Rev . 1 20-48 F reescale Semiconductor Functional Des cription 20.8.9.2 Initializing the Configuration Bits The first step ne cessary for initializing the BDLC mod ule following an MCU reset is to write the desired values t o each of the BDLC module control registers.
Functional Descrip tion MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 20-49 time passes between the exit from loopback modes and enabling the BDLC module and the enabling of interrupts. It is a good practice to al ways clear any s ource of interrupts before enabli ng interrupts on any MCU subsystem.
MPC5200B Users Guide, Rev . 1 20-50 F reescale Semiconductor Resets 20.9 Resets 20.9.1 General The reset state of each indi vidual bit is listed within Section 20.7, Memory Map and Registers which details the regi st ers and their bit-fields. BDLC module enters Run mode from Reset mod e Write desir ed config.
Overview MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 21-1 Chapter 21 Deb ug Suppor t and JT A G Interface 21.1 Overview The following sections are contained in this document: • Section 21.2, T AP Link Module (TLM) and Slave T AP Implementation • Section 21.
MPC5200B Users Guide, Rev . 1 21-2 F reescale Semiconductor T AP Link Module (TLM) and Slave T AP Implementation Figure 21-1. Generic TLM / T AP Ar chitecture Diag ram STDO [ 0 : n ] TCK TMS TDI ENA T.
T AP Link Module (TLM) an d Slave T AP Implementation MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 21-3 Figure 21-2. Gener ic T AP Link Module ( TLM ) Diagram STDO [ 0 : n ] TLMENA ENA [ 0 .
MPC5200B Users Guide, Rev . 1 21-4 F reescale Semiconductor TLM and T AP Signal Descriptions Figure 21-3. Generi c Slave T AP 21.3 TLM and T AP Signal Descriptions 21.3.1 T est Reset ( TRST ) JT AG reset, active low . When asserted, a ny on-going JT AG operation is immediately abor ted.
Slave T est Reset ( STRST ) MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 21-5 21.3.5 T est Data Out ( TDO ) Serial test data output is routed from the active shift regist er to this pin. T o ensure setup and hold time for TDO when connec ted to TDI (of another device), TDO switches at the TCK falling edge.
MPC5200B Users Guide, Rev . 1 21-6 F reescale Semiconductor e300 Core JT A G / COP Serial Interface Figure 21-4. State Dia gram—T AP Controller Instructions are loaded by stepping the state machi ne to the Sh ift-IR state by applyi ng an appropriate sequence of values on TM S at successive rising edges of TCK.
TLM Link DR Instructions MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 21-7 Figure 21-5. e3 00 Core JT A G / COP Serial Interf ace 21.7 TLM Link DR Instructions — CAUTION — 1. For the following registers, only the inst ruction codes listed should be used.
MPC5200B Users Guide, Rev . 1 21-8 F reescale Semiconductor TLM T est Instructions 21.7.1 TLM : T LMENA The TLM:TLMENA pseudo-instructi on selects the 6-bit TLM IR. 21.7.2 TLM : P PCENA The TLM:PPCENA pseudo-instruct ion selects the 8-bit micr oprocessor CPU test IR.
e300 COP / BDM Interface MPC5200B Users Guide, Rev . 1 F reescale Semico nductor 21-9 Preload: T o shift an initial value into the boundary scan register prior to loading the EXTEST or CLAMP instructio n into the Instructio n register . Capture value may be examined or ignored.
Debug Support a nd JT A G Inte rface Notes MPC5200B Users Guide, Rev . 1 21-10 F reescale Semiconductor.
A MPC5200B Users Guide, Rev . 1 F reescale Semico nductor A-1 Appendix A Acr onyms and T erms This section contains an alphabetical list of terms, phrases, acronyms, and abbreviations used in this book. Some terms and def initions included are reprinted from IEEE S td.
MPC5200B Users Guide, Rev . 1 A-2 F reescale Semiconductor C BIP . . . . . . . . . . . . . . . . . . . . Bit Int erleaved Parity BIST . . . . . . . . . . . . . . . . . . . Buil t-In Self T est BISYNC . . . . . . . . . . . . . . . . Binary Synchronous communication Blockage .
D MPC5200B Users Guide, Rev . 1 F reescale Semico nductor A-3 Context synchronization . . . . An operation that ensures: • all instructions in execution complete pa st the point where they can produ.
MPC5200B Users Guide, Rev . 1 A-4 F reescale Semiconductor E E EA . . . . . . . . . . . . . . . . . . . . . Effectiv e Address— The 32- or 64-bit address specified for a load, st ore, or instruction fe tch. This address is then submitted to the MMU for translat ion to either a physical memory address or an I / O ad dress.
H MPC5200B Users Guide, Rev . 1 F reescale Semico nductor A-5 H Harvard architecture . . . . . . . An architectural model featuring separate caches for instruction and data. HC, Hc . . . . . . . . . . . . . . . . . Host Controller HCD . . . . . . . . .
MPC5200B Users Guide, Rev . 1 A-6 F reescale Semiconductor J J JA V A™ . . . . . . . . . . . . . . . . . From Sun Microsystems, Inc.—a robust and versatile progr ammi ng language that enables developers to: • W rite software on one plat form and run it on another .
N MPC5200B Users Guide, Rev . 1 F reescale Semico nductor A-7 MAC / PHY . . . . . . . . . . . . . . Multiply-and-AC cumulate / Physical Layer Device Master . . . . . . . . . . . . . . . . . . Name given to a bus device grant ed control, or mastership, of the bus.
MPC5200B Users Guide, Rev . 1 A-8 F reescale Semiconductor O O OC . . . . . . . . . . . . . . . . . . . . . Output Com pare OE . . . . . . . . . . . . .
Q MPC5200B Users Guide, Rev . 1 F reescale Semico nductor A-9 P TE . . . . . . . . . . . . . . . . . . . . Page T able Entry P TI . . . . . . . . . . . . . . . . . . . . . Payload T ype Identifier P TP . . . . . . . . . . . . . . . . . . . . Port-T o-Port switching P TR .
MPC5200B Users Guide, Rev . 1 A-10 F reescale Semiconductor S Scalability . . . . . . . . . . . . . . . The capability of an architecture to ge nerate implementations specific for a wide range of purp.
T MPC5200B Users Guide, Rev . 1 F reescale Semico nductor A-11 stp . . . . . . . . . . . . . . . . . . . . . stop str . . . . . . . . . . . . . . . . . . . . . start STS . . . . . . . . . . . . . . . . . . . . Special Transfer Start Superscalar machine .
MPC5200B Users Guide, Rev . 1 A-12 F reescale Semiconductor W VBR . . . . . . . . . . . . . . . . . . . V ariable Bit-Rate VC . . . . . . . . . . . . . . . . . . . . . V irtual Channel, Circuit, Call, o r Connection VCC . . . . . . . . . . . . . . . .
MPC5200B Users Guide, Rev . 1 F reescale Semico nductor B-1 Appendix B List of Registers Section 5.5 CDM Registers .......... ...................... ....................... ....................... ...................... ........... ......... .........
MPC5200B Users Guide, Rev . 1 B-2 F reescale Semiconductor 7.3.2.1.13 GPS GPIO Simple Interrupt Int errupt Enable Register —MBAR + 0x0B 30 .......... ............ ........... ..... 8-44 7.3.2.1.14 GPS GPIO Simple Interrupt Interrupt T ypes Register —MBAR + 0x0B34 .
MPC5200B Users Guide, Rev . 1 F reescale Semico nductor B-3 Section 9.7.2 SCLPC Registers—MBAR + 0x3C00 ................ ....................... ...................... ....................... ......... .......... 9-23 9.7.2.1 SC LPC Packet Size Register—MBAR + 0x3C00 .
MPC5200B Users Guide, Rev . 1 B-4 F reescale Semiconductor 10.3.3.1.6 Tx Last W ord PCITL WR(R) —MBAR + 0x3814....... ............................ ............ ........... ........... ......... 1 0-28 10.3.3.1.7 Tx Bytes Done Counts PCITDCR(R) —MBAR + 0x38 18 .
MPC5200B Users Guide, Rev . 1 F reescale Semico nductor B-5 Section 1 1.3.3 A T A Drive Registers—MBAR + 0x3A00 .............. ....................... ...................... ....................... ...... ......... 1 1-12 1 1.3.3.1 A T A Drive Device Control Regi ster—MBAR + 0x3A5C .
MPC5200B Users Guide, Rev . 1 B-6 F reescale Semiconductor 13.15.8 SDMA T ask Control 0 Reg ister—MBAR + 0x121C ..... .................... ...................... ....................... ..... 13- 9 13.15.9 SDMA T ask Control 2 Reg ister—MBAR + 0x1220 .
MPC5200B Users Guide, Rev . 1 F reescale Semico nductor B-7 Section 14.8 FEC Tx FIFO Status Register—MBAR + 0x31A8 .................... ...................... ....................... ................. 14-2 8 14.8.1 FEC Rx FIFO Control Register—MBAR + 0x318C .
MPC5200B Users Guide, Rev . 1 B-8 F reescale Semiconductor 15.2.43 Tx FIFO W rite Pointer (0x96)—TFWP TR ............ ......................... ....................... ...................... ... ... 15-43 15.2.44 Tx FIFO Last Read Frame (0x9A)—TFLRFP TR .
MPC5200B Users Guide, Rev . 1 F reescale Semico nductor B-9 19.5.16 MSCAN T ransm it Error Counter Register (C ANTXERR)-MBAR + 0x091D/0x09 9D .............. ...... 19-17 19.5.17 MSCAN ID Acceptance Registers (CANIDA R0-7)—MBAR + 0x0920 / 0x09A0 ... .
MPC5200B Users Guide, Rev . 1 B-10 F reescale Semiconductor.
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