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FUJITSU SEMICONDUCT OR CONTROLLER MANU AL FR30 32-Bit Microcontroller MB91F109 Hardware Manual CM71-10106-1E.
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FUJITSU LIMITED FR30 32-Bit Microcontroller MB91F109 Hardware Manual.
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i PREFACE ■ Objectives and Intended Reader The MB91F109 has been de veloped as one of the " 32-bit sing le-chip mi crocontro ller FR30 series" products tha t use new RISC architec ture CPUs as their core s. It has op timal specific ations for e mbedding applicat ions that require hi gh CPU pro cessing p ower.
ii ■ Organization of This Manual This manu al consis ts of 16 c hapters and an appendi x. Chapter 1 Overv iew Chapter 1 provi des ba sic gen eral informat ion on the MB91F109, incl uding i ts char acteri stics, a block diagram, a nd functio n overvie w.
iii Chapter 14 PW M Timer Chapter 14 provides a n overview o f the PWM ti mer, explai ns the regis ter configur ation and function s, and ope rations of the PW M timer. Chapter 15 DMAC Chapter 15 provide s an ov erview of t he DMAC , explains the reg ister conf iguration a nd function s, and ope rations of the DMAC .
iv ©1999 FUJI TSU LIMITED P rinted in Japa n 1. The cont ents of this doc ument are sub ject to change witho ut notice. Custo mers a re advi sed to cons ult with F UJITSU sa les representati ves before ordering.
v How to Read This Manual ■ Description Format of this Manual Major te rms used i n this ma nual are ex plained below: Term Meaning I-BUS 16-bit wide bus used for internal ins tructions . Since the FR seri es uses an inter nal Harvard archite cture, indep endent buses are u sed for instruc tions and data.
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vii CONTEN TS CHAPTER 1 OVERVIEW ............. ................... .............. .................. .............. ................... .. 1 1.1 MB91F109 Ch aracteristics ................. .................... ................... ................... .
viii 3.9 Gear Function .............. ................... .................... ............. ................... ................... ....... ...................... 87 3.10 Standby M ode (Low Pow er Consumpti on Mechanis m) ......... ..................
ix 4.17.17 Hyper DRAM I nterface: Read ............... ................... ............. ................... .................... ....... .......... 188 4.17.18 Hyper DRAM I nterface: Write ..................... ................... ............. .....
x 10.5 Serial Sta tus Register (S SR) .... ................... .................... ............ .................... ................... ....... ....... 253 10.6 UART Operation ................ ............. ....... ...... ....... ...... ....... ....
xi 15.5 Descriptor Registe r in RAM ................ ....... ...... ....... ............ ....... ...... ....... ...... ....... ...... ....... .. ........... .... 332 15.6 DMAC Transfer M odes .... ................... ............. ................... .
xii FIGURES Figure 1.2-1 Gene ral Block Diagram of MB91F10 9 ............ ............. ................... .................... ................. ....... 6 Figure 1.3-1 Outsid e Dimensions of FPT-100P-M 06 .......... ................... .............
xiii Figure 3.15 -1 Example of PLL Clock S etting .. ............. ................... .................... ................... .................... .... 1 08 Figure 3.15 -2 Clock Syste m Reference Diag ram ........ ................... ...............
xiv Figure 4.17 -12 Example 5 of Wr ite Cycle Tim ing Chart ................. ................... ............. ................... ............. . 169 Figure 4.17 -13 Example of Read an d Write C ombinatio n Cycle Timing Chart . ............. .......
xv Figure 7.1-1 Delay ed Interrup t Module Regis te r ..................... ...... ............. ....... ...... ....... ...... ....... ...... .. ......... 220 Figure 7.1-2 Del ayed Interrup t Module Blo ck Diagram ........... ................... .....
xvi Figure 14.1 0-1 One-Shot Operation Timi ng Chart (Trigger Res tart Disabl ed) ........ .................... ................... . 318 Figure 14.1 0-2 One-Shot Operation Timi ng Chart (Trigger Res tart Ena bled) .. ............. ...................
xvii TABLES Table 1.4 -1 FBGA Pa ckage Pin Names ............. ............. ................... ................... .................... ................... 13 Table 1.5 -1 Pin Functio ns (1/5) ...... .................... ................... ........
xviii Table 8.3 -1 Correspondence s between t he Interrupt Lev el Setting B its and Interrupt Levels ............ ....... 229 Table 8.5 -1 Relationships among Inte rrupt Causes, Numbers, an d Levels (1/2) .................. ............. ....... 231 Table 8.
xix Table A-4 I/O M ap (4/6) ............... .................... ................... ............. ................... .................. ........ ........... 375 Table A-5 I/O M ap (5/6) ............... .................... ................... .....
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1 CHAPTER 1 OVERVIEW This chapter pro v ides basic g eneral inf ormation on the MB91F109, inc luding its characteristics, bloc k diagram, and fu nction overview . 1.1 MB 91F109 Cha racteristics 1.2 Gene ral Bl ock Diagr am of MB9 1F109 1.3 Outs ide Dimen sions 1.
2 CHAPTER 1 OVE RVIEW 1.1 MB91F109 Characteristi cs The MB91F109 is a standar d single-chip micr ocontroller using a 32-bit RISC CPU (FR30 se ries) as its cor e . It contai ns various I/O res ources and bus control mechanisms for embedded control applications that require high-speed CPU processing.
3 1.1 MB 91F109 Chara cterist ics • Automati c wait cy cle: An y number of cycles ( 0 to 7) can be set for each ar ea. • Unuse d data and address term inals c an be used as I/O por ts.
4 CHAPTER 1 OVE RVIEW convers ion • Starting: Selectable from software, e xternal trigger, an d internal timer ❍ Reload timer • 16- bit time r: Thre e channe ls • Internal clock: 2 -clock cy cle resoluti on.
5 1.1 MB 91F109 Chara cterist ics ■ A vailable T y pes MB91V10 6 MB91106 MB91F109 IROM - 63 Kbyte - IRAM 64 Kb yte - - CROM - 64 Kbyte 254 Kb yte CRAM 64 Kby te - 2 Kby te R A M 2 K b y t e2 K b y t.
6 CHAPTER 1 OVE RVIEW 1.2 General Block Diagram o f MB91F109 Figure 1.2.1 is a general MB91F109 bloc k diagram. ■ General Block Dia g ram of MB91F109 Figure 1.2-1 General B loc k Di agram of MB91F109 Notes: • Terminal s are rep resented by the function (some te rminals a re actua lly mult iplexed).
7 1.3 Outside Dimensions 1.3 Outsid e Dimensions Figures 1.3.1 to 1.3.3 sho w the outside dimensi ons of the MB 91F109. ■ Outside Dimensions (QFP-100) Figure 1.3-1 Outside Dimensions of FPT -100P-M06 : * QFP100-P-1420-4 (F PT -100P -M06 ) (FPT -100P-M06) 1994 FUJITSU LIMITED F100008-3C-2 "A" 0.
8 CHAPTER 1 OVE RVIEW ■ Outside Dimensions (LQFP-100) Figure 1.3-2 Outside Dimensions of FPT -100P-M05 * QFP100-P-1414-1 (FPT -100P-M05 ) (FPT -100P-M05) C 1995 FUJITSU LIMITED F100007S-2C-3 Details of "B" part 16.00 0.20(.630 .008)SQ 14.00 0.
9 1.3 Outside Dimensions ■ Outside Dimensions (FBGA -112) Figure 1.3-3 Outside Dimens ions of BGA-112P-M01 0.80 mm 11 10.00 × 10 .00 mm 1.45 mm MAX 0.45 (BGA-112P -M01) (BGA-112P-M01) C 1998 FUJITSU LIMITED B112001S-2C-2 10.00 0.10(.394 .004)SQ .049 -.
10 CHAPTER 1 OVE RVIEW 1.4 Pin Arrangement Diagram s Figures 1.4.1 to 1.4.3 show the pi n arrangements of the M B91F109. ■ Pin Arrangements (QFP-10 0) Figure 1.
11 1.4 Pin Arra ngement Diagrams ■ Pin Arrang ements (LQFP -100) Figure 1.4-2 LQFP-100 Pin Arrangements P20/D16 P85/WR1X P84/WR0X P83/RDX P82/BRQ P81/BGRNTX P80/RDY MD2 MD1 MD0 VSS RSTX VCC NMIX PA0.
12 CHAPTER 1 OVE RVIEW ■ Pin Arrang ements (FBGA-112) Figure 1.4-3 FBG A-112 Pin Arrang ements Table 1.4.1 shows the cross-re ferences o f the FBGA package pi n names.
13 1.4 Pin Arra ngement Diag rams T able 1.4-1 F BGA Pac kag e Pin Names BALL-No. PIN-NAME BALL-No. PIN-NAME BALL-No. PIN-NAM E A1 A2 A3 A4 A5 N.C RAS1 / PB4/ EOP2 CS0L/ PB1 INT1/ PE1 X1 D6 D7 D8 D9 D10 VCC DREQ0/ PE4 OCPA0/ PF 7/ ATGX AN2 AVRH H9 H10 H11 J1 J2 A14/ P 56 A13/ P 55 N.
14 CHAPTER 1 OVE RVIEW 1.5 Pin Function s T ables 1. 5.1 to 1.5.5 lists the MB91 F109 pin functions. The number s shown in the tables has nothing to do with the pack age pin number s. Since pins have diff erent pin numbers among QFP , LQFP , an d FBGA, see Section 1.
15 1.5 Pin Functions 33 34 35 36 37 38 39 40 A16/P6 0 A17/P6 1 A18/P6 2 A19/P6 3 A20/P6 4 A21/P6 5 A22/P6 6 A23/P6 7 F Bits 16 to 23 of ex ternal addr ess bus. When the se pins are not used for the ad dress bus , they ca n be u sed as general-pu rpose I /O ports ( P60 to P67) .
16 CHAPTER 1 OVE RVIEW 47 WR1X/P8 5 F Note: WR1X is Hi-Z whil e it is in res et state. When it is used as a 16-bit bu s, attach a pull-u p resistor to the outs ide. [P84 or P85] Whe n WR0X or W R1X is no t used, the pin c an be use d as a gen eral-purpos e I/O por t.
17 1.5 Pin Functions T able 1.5-3 Pin Functions (3 /5) NO. Pin name I/O c ircuit for mat Function 55 56 57 58 59 60 61 62 RAS0/PB0 CS0L/PB1 CS0H/PB2 DW0X /PB3 RAS1/ PB4/E OP2 CS1L/PB5/DREQ2 CS1H /PB6/.
18 CHAPTER 1 OVE RVIEW 73 INT2/SC1/PE2 F [INT2] In put of extern al interrupt req uest. This input is used from time to tim e while th e corresp onding ex ternal inte rrupt is e nabled. Therefore, i t is need ed to stop output by other function s excep t when suc h output i s performe d intentio nally.
19 1.5 Pin Functions 78 DACK1/PE 7 F [DACK1 ] Output of DM AC external transfer request acceptan ce (ch 1). This function is valid when the ou tput of DMAC transfer requ est acceptan ce is en abled . [PE7] G eneral-pur pose I/O po rt. This function is valid wh en the outpu t of DMA C transfe r request acceptan ce or DA CK1 output is disa bled.
20 CHAPTER 1 OVERVIEW 83 SO1/TRG3/P F4 F [SO1] UA RT1 data outp ut. This fun ction is v alid when UART1 dat a output is enabl e d. [TRG3] Exter nal trigge r input of PW M timer . This function is valid wh en PF4 a nd UART1 dat a output is disabl ed. [PF4] Gen eral-p urpose I/O port.
21 1.5 Pin Functions Note: An I/O po rt and res ource I/O are mu ltipl exed, as shown l ike xxx x/Px x, at mos t pins l isted above. If the port c onflicts with res ource output at this type of pin, the res ource outpu t is given p riority. 92 AVR H - Reference v oltage of A/D co nverter (hi gh potentia l side).
22 CHAPTER 1 OVERVIEW 1.6 I/O Circuit Format T ables 1. 6.1 and 1.6.2 sh ow s I/O circ uit forma ts. ■ I/O Circuit Fo rmat T able 1.6-1 I/ O circuit format (1/2) Classification Circuit format Remark.
23 1.6 I/O Circuit Format D • CMOS le vel h ysteresi s input • No standby control T able 1.6- 1 I/O circuit format (1/2) Classification Circuit format Remarks CMOS Diffused resistor P-channel transistor N-channel transistor Digital input T able 1.
24 CHAPTER 1 OVE RVIEW 1.7 Memory Address Space The logical address space of the FR series consists of 4 gigab ytes (2 32 addresses ) a nd the CPU a ccesses them li nearly . ■ Memory map Figure 1. 7.1 shows the memor y addre ss space o f the MB91F1 09.
25 1.7 Memory Address Space ❍ Direct address ing area The followi ng area in th e addres s space is used for I/O . This area i s called the direct addres sing are a.
26 CHAPTER 1 OVE RVIEW 1.8 Handling of Devices This section pro vides notes on using devices. ■ Device Handling ❍ Latchup pre vention If volta ge highe r than Vcc or lower th an Vss is appl ied to a CMOS IC inp ut or outpu t pin or if voltage exce eding the r ating is appl ied b etwe en Vcc and V ss, latch up may be c ause d.
27 1.8 Handling of Devices Figure 1.8-2 Example of Using an External Cloc k (P ossible at 12.5 MHz or Lo wer) ❍ Connection of po wer pins (Vcc and Vss) When two or more Vcc or Vs s pins are used, th.
28 CHAPTER 1 OVE RVIEW ❍ Initialization by power -on rese t Devices contain registe rs that a re initia lized only by power -on re set. To ini tialize these regist ers, turn th e power of f and turn it o n again to execute power-on r esetting.
29 CHAPTER 2 CPU This chapter pro vides basic inf ormation on the FR series CPU core funct ions including the ar chitecture, specifications, and instructions. 2.1 CPU Architecture 2.2 Inte rnal Architect u re 2.3 Progr ammin g Mode l 2.4 Da ta Structure 2.
30 CHAPTER 2 CPU 2.1 CPU Architecture The FR30 CPU is a high perf ormance core that uses the RISC arc hitect ure an d support s ad vanced functional instructions geared to embedding applications.
31 2.2 Internal Architecture 2.2 Internal Architecture The FR CPU uses the Harvard ar chitecture in which the instruction b us and data bus are independent of each other . The "32 bits <--> 16 bits" b us con verter is connected to the data b us (D-BUS) to implement the i nterface betw een the CPU and periphe ral resour ces.
32 CHAPTER 2 CPU Figure 2.2-2 Instruction Pipeline Inst ructio ns are alway s execute d in orde r. That is, inst ruction A tha t is put into th e pipel ine before i nstruc tion B alw ays rea ches the write bac k stage before in structi on B. Instructi ons are normall y executed at a rate of on e instruction pe r cycle.
33 2.3 Programming Model 2.3 Programming Model This section explains the CPU registers that ar e essential f or programming. The CP U registers are classified into the f ollowing tw o groups: • Gene ral-purpose regist ers • Special register s ■ Gener al- Purp o se Regist ers Figure 2.
34 CHAPTER 2 CPU Figure 2.3-2 Configuration of special registers SCR CCR ILM PC PS TBR RP SSP USP MDH MDL 32 bits Program counter Program status Table base register Return pointer System stack pointer.
35 2.3 Programming Model 2.3.1 General-Purpos e Registers Register s R0 to R15 are general-purpose regis ter s. They are used as accum ulators f or v a rious types of operation or memory access pointers. ■ General-Purpose Registers Figure 2. 3.3 shows the confi guration of g eneral-pur pose regi sters.
36 CHAPTER 2 CPU 2.3.2 Special Register s The special register s are used f o r special purposes. They are the program counter (PC), pr ogram status (P S), table ba se regist er (TBR), return pointer (RP), sy stem st ac k pointer (SSP), user stack pointer ( USP), and m ultiplication/division result register (MDH/MDL).
37 2.3 Programming Model ❍ Program status (PS) The program status register holds the progra m s tatus in three parts, CCR, SCR, an d ILM. See Section 2.3.3 fo r more info rmation. The undefin ed bits a re all res erved. Wh en the reg ister is re ad, 0 is a lways read from thes e bits.
38 CHAPTER 2 CPU [Division] When ca lculatio n begins, a d ividend is stored in the MDL. The resu lt of divi sion by the DIV0S/DIV 0U, DIV1, DIV 2, DIV3 , or DIV4S in structi on is stor ed in the MDL .
39 2.3 Programming Model 2.3.3 Pr ogram Statu s Register (PS) The pr og ram status register holds the pr ogram stat us in three parts, ILM, SCR, and CCR. The undefined bits are all reserved. When the register is r ead, 0 is al ways read fr om these bits.
40 CHAPTER 2 CPU [bit 3] N: Negative flag This bit ind icates a si gn applic able when the ope ration re sult is as sumed to be an in teger that is rep resente d in two’s c omplement. 0: Ind icates th at the oper ation re sult is a positi ve valu e.
41 2.3 Programming Model [bit 8] T: St ep-trace-trap f lag This flag specifies whether to en able step -trace -trap. 0: Disab les step-t race-tra p. 1: Enabl es step-tr ace-trap. Settin g the bit to 1 inhibi ts all us er NMIs and user in terrupts. The flag i s cleared to 0 by resetting.
42 CHAPTER 2 CPU 2.4 Data Structure FR-series data is mapped as f ollows: • Bit ordering: Little endian • Byte ordering: Big endian ■ Bit Or dering The FR se ries uses l ittle endi an for bit or dering. Figure 2. 4.1 shows data mappi ng in bit ordering m ode.
43 2.5 Word Alignment 2.5 Word Ali gnment Since instructions and data are acces sed in b yte s, mapping ad dresses v ary depending on instruction length or data width. ■ Program Access A progra m runnin g in the FR series must be p laced at an address consis ting of a multiple of two.
44 CHAPTER 2 CPU 2.6 Memory Map This section shows an M B91F109 me mor y map and a me mory map common to the FR series. ■ MB91F1 09 Memor y Map The addre ss space i s 32 bits l ong linea rly.
45 2.6 Me mory Ma p ■ Memory Ma p Common to the FR Series The FR series defi nes the followi ng mem ory m ap. This mem ory m ap is c omm on t hroug hout the FR series reg ardless of types (except in s ingle chi p mode). Figure 2. 6.2 shows the memory map co mmon to the FR series.
46 CHAPTER 2 CPU 2.7 Instruction Overview The FR series suppor ts logical operation, bit manipulation, and direct ad dressing instructions, which are optimi zed for embeddi n g applications, in ad dition to g eneral RISC instructions.
47 2.7 Instruction Over vie w ❍ Logical operation and bit manipulation A logical o peration instruct ion can exe cute AND, O R, or EOR logi cal operati on between general -purpose regi sters or be tween a general- purpose re gister and mem ory (or I/O ).
48 CHAPTER 2 CPU 2.7.1 Branc h Instructions with Dela y Slots A branc h instruction ca uses the pr ogram to branc h and ex ecute the i nstruction at the branch des t ination after the inst ruction (called the de lay slot ) placed i mmediatel y after the branc h instruction is ex ecuted.
49 2.7 I nstruct ion Overvie w ❍ Ri that is re ferenced by the JMP:D @Ri or CALL:D @Ri instruction is not affected even when the instruction in the delay slot updates the Ri. [Example] ❍ RP that is referenc ed by the RET :D instruct ion is not affected even when the instruct ion in the delay slot updates the RP .
50 CHAPTER 2 CPU ■ Restri ctions on Branch Instructions with Delay Slots ❍ Instruc tions that can be place d in delay slots An inst ruction that ca n be exec uted in th e delay s lot must satisfy .
51 2.7 Instruction Over vie w 2.7.2 Branch Instructions without Delay Slots Instructions inc l uding branch instructions without dela y slots are e xecuted in or der of coding.
52 CHAPTER 2 CPU 2.8 EIT (Excepti on, Interrupt, a nd Trap) EIT indicates that the pr ogram being e xecuted is interrupted by an e v en t and another program is e xecuted. EIT is a generic name coined fr om the wor ds: exception, interrupt, and trap. An exception is an e vent that occurs in connection with the conte xt of the current execution.
53 2.8 EIT (Exception, Interrupt, and Trap) ■ Not e on EI T ❍ Delay slot The delay slot of a branch instructi on has res trictions on EIT. See Sec tion 2.
54 CHAPTER 2 CPU 2.8.1 EIT Interrupt Levels The EIT interrupt le vels range from 0 to 31, w hich are mana g e d using five bits. ■ Interrupt Levels Table 2.8.1 summar izes the as signment s of the EIT interru pt levels. Operation can b e performed on levels 16 to 31.
55 2.8 EIT (Exception, Interrupt, and Trap) ■ I Fla g The I flag spec ifies whether to enab le or disable inte rrupts. It is provided at bi t 4 of PS register CCR. ■ Interrupt Level Mask Register (ILM) ILM is a part of the PS register (bi ts 16 to 20) t hat holds an interru pt level mas k value .
56 CHAPTER 2 CPU 2.8.2 Interr upt Contr ol R egister (ICR) The interrupt contr ol register , which is pr ovided in the interrupt contr oller , is used to set the level f or each interrupt request. The ICR is divided to correspond to indi vidual interrupt causes.
57 2.8 EIT (Exception, Interrupt, and Trap) 2.8.3 System Stac k P ointer (SSP) The system st ack pointer ( SSP) indic ates the s tack used t o sa ve data f or EIT processing or restore data for returning fr om EIT .
58 CHAPTER 2 CPU 2.8.4 Interr upt Stac k The interrupt s tac k is the are a indicated b y the sy stem stac k pointer (SSP). The PC or PS v alue is sa ved to it or restore d fr om it. After an in terrupt is caused, the PC v alue is stored at the address i ndicate d by the SSP an d the PS value is stor e d at the addr e ss "SSP + 4 .
59 2.8 EIT (Exception, Interrupt, and Trap) 2.8.5 T able Base Registe r (TBR) The tabl e base register (TBR ) indicate s the f irst ad dress of the EIT vector t a ble.
60 CHAPTER 2 CPU 2.8.6 EIT V ector T able The 1-kilobyte area beginning fr om the address, indicated by the table base register (TBR), is t he EIT vector area.
61 2.8 EIT (Exception, Interrupt, and Trap) Table 2.8.3 is the v ector table in the ar chitectu re. Specia l functio ns are as signed to some v ectors .
62 CHAPTER 2 CPU 2.8.7 Multiple EIT Pr ocessing When multiple EIT e vents occur concurrently , the CPU selects one EIT event, accepts it, ex ecut es the EIT sequence, and then detects another EIT e vent. It repeats this operation f or all EIT e vents.
63 2.8 EIT (Exception, Interrupt, and Trap) Figure 2. 8.2 shows an example o f multipl e EIT proc essing. Figure 2.8-2 Example of Multiple EIT Pr oces sing T able 2.
64 CHAPTER 2 CPU 2.8.8 EIT Operation This section explains EIT operation. Suppose the transfer source "PC" appearing i n th e foll owing explanation indicates the address of the instr uction that detect ed an EIT event.
65 2.8 EIT (Exception, Interrupt, and Trap) [Operation] SSP - 4 --> SSP PS --> (SS P) SSP - 4 --> SSP Next ins tructio n addres s --> (SS P) Interrupt level of accepted request --> ILM .
66 CHAPTER 2 CPU ■ Operation for Step -trace-trap After the T flag in the PS SC R is set to enabl e the step-trace function , a trap occurs every time an instr uction is executed , resulting in a bre ak.
67 2.8 EIT (Exception, Interrupt, and Trap) ■ Coprocessor Nonexistent T rap If a coproces sor instruction th at attempts to use a coprocess or that is not instal led is executed, a coproce ssor nonex istent trap occur s.
68 CHAPTER 2 CPU 2.9 Reset Sequence This section explains CPU resetting. ■ Causes of Rese tting The caus es of resett ing are a s follows : • Input fro m an externa l reset pin • Software r eset.
69 2.10 Operat ion Mode 2.10 Opera tion Mode T wo operation modes, b us mode and access mode, are a vailable. The mode pins (MD2, MD1, and MD0) and mode register (MODR) are used to contr ol the operation mode . ■ Operation Mode Two operat ion modes , bus mode and acc ess mode, ar e availabl e.
70 CHAPTER 2 CPU ■ Mode Data Data that th e CPU writes at 0000 07FF H after resetting is called mode data. The mode regist er (MODR) exists at 0000 07FF H . After mode data is set to this register, the CPU oper ates base d on the mo de set to th e register.
71 2.10 Operat ion Mode MODR writing RSTX (reset) MD2,1,0 BW1 and BW0 of AMD0 to AMD5 Bus width specification.
72 CHAPTER 2 CPU.
73 CHAPTER 3 CLOC K GEN ERATOR AND CON TROLLER This chapter pro vides detailed information on the generation and contr ol of c loc k pulses that contr ol the MB91 F109. 3.1 Outline of Clock Generator and Contro ller 3.2 Re set Reason Re sister (R SRR) an d Watchdog Cycle Control Regist er (WTCR) 3.
74 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.1 Outline of Clock Generator and Controller The c l ock generator and contr oller are the modules that have the f ollowing functions: • CPU c l ock gene.
75 3.1 Outline of Clock Generator and C ontroller ■ Clock Generator and Contr oller Bloc k Diag ram Figure 3. 1.2 is a b lock diagram of the clo ck genera tor and contr oller.
76 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.2 Reset Reason Resister (R SRR) and Watchd og Cycle Control Register (WTC R) The reset reason register (RSRR) holds the type of the reset event that occurred, and the watchdog cyc le control register (WTCR) specifies the cyc le of the watchdog timer .
77 3.2 Reset Reas on Resister (RSRR) and Watchdog Cycle C ontrol Register (WTCR) [bit 09, 08] WT1, 0 These bits specify t he cycle of the watch dog timer. The bit s and the cyc les select ed by the bits have the relation ships sh own in Table 3. 2.1. These bit s are initial ized when the en tire register is reset.
78 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.3 Standby Control R egister (STCR) The standby contr ol register (STCR) is used to control standby op eration and specify the oscillation stabi lization wait time .
79 3.3 Standby Control Regis ter (STCR) φ i s twice as larg e as X0 when GCR CHC is 1, and is the cycle of PLL oscil lation freque ncy when CHC is 0. [bit 01, 00] (Reserv ed) These bit s are res erved. The v alue read fr om this bit is un defined. T able 3.
80 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.4 DMA Request Sup pression Registe r (PDRR) The DMA request suppression register (PDRR) is used to temporaril y suppress DMA requests to lighten the load t o the CPU.
81 3.5 Time base Timer Clea r Register (CTBR) 3.5 Timebase T imer Clear Register (C TBR) The timebase timer c lear register (CTBR) clea rs the timebase timer to 0 f or initialization.
82 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.6 Gear Control Re gister (GCR) The gear control register (GCR) contr ols the g ear functions of the CPU and peripheral clo cks .
83 3.6 Gear Control R egister (GCR) [bit 12] DBLON This bit speci fies the cl ock doubler operation mode. This bit is initia lized by resetting. This model do es not su pport the cl ock doub ler func tion. [bit 11, 10] PCK1, 0 These bits sp ecify the gear cycl e of peripher als.
84 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER When the clock doubler is set to O N, the CPU gear is fixed r egardless of the G CR value a nd therefore t he gear c an also b e set direc tly to th e desired v alue. [Example of programming] [bit 09] Re served bit Always write 1 to th is bit.
85 3.7 Watchdog Timer Res et Delay Register (WPR) 3.7 Watchd og Timer Reset Delay Re gister (WPR) The watchdog timer reset dela y register (W PR) c lears the flip-flop for the watc hdo g timer . This register can be used to dela y watchdog timer resets.
86 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.8 PLL Control Register (PCTR ) The PLL contr ol register (PCTR) is used to contr ol PLL oscillation. The setting of this register can be changed only when GCR CHC is 1. ■ Configuration of PLL Contr ol Re gister (PCTR) The PLL con trol regis ter (PCTR) i s used to cont rol PLL osc illation.
87 3.9 Gear Func tion 3.9 Gear Functi on The gear function supplies cloc k pulses by slo wing down the c lock pulse inter v als. The function uses tw o independent circuits f or the CPU and peripherals. Data can be transferred between the CPU and peripherals e ven when both cir cuits use different gear ratios.
88 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER [Example] The output fr om the divi de-by-two freq uency ci rcuit can be selected as the source cl ock by setting the CHC bit of the gear control register to 1. Setting the CHC bi t to 0 selects the clock having t he same c ycle as th e clock g enerated f rom the osc illation c ircuit.
89 3.9 Gear Func tion Figure 3.9-2 Clock Selection Timing Char t ■ Blocks That Use the Peripheral Clock The block s listed b elow use the per ipheral c lock, which c an be set by the gea r functi on, as the operati ng clock.
90 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.10 S tandby Mode (Lo w Power C onsump tion Mechanis m) The standb y mode implies the stop state and sl eep state . ■ Outline of Stop State In the sto p state, a ll interna l clocks and the op eration of th e oscilla tion circui t are sto pped so as to minim ize power c onsumpti on.
91 3.10 Standby Mode (Low Power Consumption Mechanism) *: When S TCR HIZX i s "0", the p revious s tate is he ld. Setti ng HIZX to " 1" puts th e pin to Hi -Z.
92 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.10.1 Stop State This section pro vides inf ormation on transition to and returning fr om the stop state . Figure 3.10.1 shows a stop contr oller bloc k diagram. ■ Stop Contr oller Block Dia gram Figure 3.
93 3.10 Standby Mode (Low Power Consumption Mechanism) [Example of setting the maximum gear speed:] ■ Returning fr om the Stop State An inter rupt or r esetting can be used to return fr om the stop state.
94 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER L level application to RSTX pin --> occurrence of internal reset --> restart of oscillation circuit operation --> wait for oscillation stabilizatio.
95 3.10 Standby Mode (Low Power Consumption Mechanism) 3.10.2 Sleep State This section pro vides inform ation on transition to the sleep state and returning from the sleep state . Figure 3.10.2 shows a b lock dia gram of the sle ep controlle r . ■ Sleep Controller Bloc k Diagram Figure 3.
96 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER [Example of setting the maximum gear speed] ■ Returning fr om the Sleep State An inter rupt or r esetting can be used to return fr om the sleep state.
97 3.10 Standby Mode (Low Power Consumption Mechanism) request oc cur simu ltaneou sly, the DMA reques t is given p riority. • When tra nsiti on t o the sl eep sta te ha s b een c au sed by a C- bus RA M pr og ram, d o not use an interrupt, but reset instead to return from the sleep s tate.
98 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.10.3 Standby Mode State T rans ition Figure 3.10.3 is a standb y mode state transition diagram. ■ Standby Mode State T rans ition Figure 3.
99 3.11 Watchdog Function 3.11 Watchdog Function The watchdog function detects pr ogram crashes. If A5 H and 5A H are not written to the watchdog reset postpone register within the specified time due to a pr ogram crash, the watc hd og timer issues a watchdog reset request.
100 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER Figure 3.11-2 W atchdog Timer Operating Timing <Note> • The tim e interval between the f irst A5 H and the nex t 5A H is not specifie d.
101 3.12 Reset Source Hol d Circuit 3.12 Reset Source Hold Circuit The reset source hold circuit holds the sour ce of previous resetting. Reading the cir cuit cle ars all flags to 0. Once a sour ce flag i s set, it i s not c leared unless t he cir cuit is read.
102 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER [Example] <Notes> • When the PO NR bit is 1, ass ume that the contents o f t he other bits are undefi ned. When it is req uired to check res et so urces, place a p ower-on re set chec k instr uction a t the begin ning.
103 3.13 DMA Suppressi on 3.13 DMA Suppression If an interrupt with a higher pri ority occurs during DMA transf er , the FR series interrupts DMA transfer and branc hes to t he corresponding interrupt r outine . This feature remains eff ect ive as long as an int errupt request continues.
104 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER [Example] <Note> Since t he register consist s of four bi ts, the DMA supp ression f unction cannot be u sed for more than 15 con curren t interru pts. Alway s give a DMA task a pri ority th at is at leas t 15 levels highe r than that o f other interrupts .
105 3.14 Clock Doubler Function 3.14 Clock Doubler F unction As the internal operating frequenc y goes higher , the external b us timing normally becomes more c omplicated. T o pre v ent this, the r atio of the e xternal b us frequency to the internal operating frequency can be adjusted to 1 to 2 (1 : 2).
106 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER [Example] Code as fo llows to use the PL L clock af ter the clock doubler function is disable d: [Example] ■ Note on Enabling or Disabling the Clock Doubler Function Enablin g or dis ablin g the clock doubler function ma y caus e a dead cy cle in the interna l cloc k.
107 3.14 Clock Doubler Function regist er. (Table 3 .14.1 shows an exam ple for the c ase that a 12.5 MH z oscillatio n is use d.) *1: Fixed to 1/1 regardle ss of se ttings *2: To dis able the c lock do ubler funct ion, s witch the clock t o the divi de-by- two cloc k in adv ance.
108 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.15 Examp le of PLL Clock Setting This section pro vides an example of PLL c lock setting and an e xample of the assemb ler source. ■ Example of PLL Clock Setting An exam ple of th e procedure for switching to 2 5 MHz op eration using P LL (in the case of 12.
109 3.15 Example of PLL Clock Setting • The peri pheral oper ating freque ncy mus t not exc eed 25 MHz . • Design s oftware so th at 100 micr oseconds or more ar e allowed u ntil oscilla tion stabi lizes after the PL L VC0 restarts. D o not allo w cache o n/off to cau se a wait time shortage.
110 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER CHC_1: call VCO_RUN PLL_S ET_END: ld @R15 +, PS ; pop processo r stat us ; ***** ***** ******** ******* ******** ***** ******* ******** ******* ; VCO Setti.
111 CHAPTER 4 BUS INTERFACE This chapt e r explains the basic items of the external b us interf ace, register configuration and functions, bu s operations, and b us timing and pr ovides b us operation program samples. 4.1 Outlin e of Bus Interface 4.2 Chip Select Area 4.
112 CHAPTER 4 BUS INTERFACE 4.1 Outline of Bus I nterface The bus interfac e controls the interf ace betw ee n external memor y and I/O . ■ Features of the Bus Inter face • 25-bit (32 megabyte s) .
113 4.1 Ou t line of B us Interf ace ■ Bus Interfac e Registers Figure 4. 1.1 shows the bus inter face regis ters. Figure 4.1-1 Bus Interface Regist ers For detai ls on the mod e register (MODR), see Section 2 .10, "Op eration M ode." 31 -------- 24 23 -------- 16 15 -------- 8 7 -------- 0 (Area Select Reg.
114 CHAPTER 4 BUS INTERFACE ■ Block Diagram of the Bus Interface Figure 4. 1.2 shows a block di agram of t he bus in terface Figure 4.1-2 Bus Interface Block Diagram 32 32 A-OUT EXTERNAL D ATA B U S.
115 4.2 C hip Se lect Area 4.2 Chip Select A rea A total of six types of chip se lect area are prepa red f or the b us interfac e . ■ Setting Chip Select Areas Each ar ea can be op tionally l ocated.
116 CHAPTER 4 BUS INTERFACE 4.3 Bus Interface The bu s interface include the f ollowing: • Usual b us interface • DRAM interfac e These interfa ces can onl y be used in the predetermined area. ■ Chip Se lect Areas and Bus Interfaces Table 4.3.1 s hows the corres pondence between each chip sele ct area and ava ilable in terface func tions .
117 4.3 Bus Interfa ce ❍ Bus siz e specification A bus wi dth can be option ally sp ecified for each area by re gister s etting. A bus widt h, set by pins MD2, M D1, an d MD0 at res et time, is speci fied fo r area 0. Af ter writi ng to the mode regist er (MODR), a b us size i s specifie d by the v alue set in the AM D0 register.
118 CHAPTER 4 BUS INTERFA CE 4.4 Area Select Register (ASR) and Area Mas k Register (AMR) The area se lect register s (ASR1 to ASR 5) and are a mask regi sters (AM R1 to AMR5) specify th e range of ad dress spac e for chi p selec t areas 1 to 5 .
119 4.4 Area S elect Regis ter (ASR) and Area Mask Register (AMR ) The area select registe rs (ASR1 to ASR5) and ar ea mask registe rs (AMR1 to AMR5) s pecify the range of address space f or chip select a reas 1 t o 5.
120 CHAPTER 4 BUS INTERFACE Figure 4.4 .1 s how s a map of the ar eas set i n the 64 k il obyte s b y i nit ial v alu es dur in g r eset an d a map of the areas set i n Examp les 1 and 2.
121 4.5 Area M ode Regist er 0 (AMD0 ) 4.5 Area Mode Register 0 (AMD0) Area mode re gister 0 (AMD0) specifie s the opera tion mode of c hip select area 0 ( area other that those specified by ASR1 to ASR5 and AMR1 to AMR5). At reset time, are a 0 is selecte d .
122 CHAPTER 4 BUS INTERFA CE <Note> Before wri ting to the M ODR, se t the bus width, equal to that set by the MD2, MD1, and MD0 pins, in BW1 and BW0 of A MD0. The bus wi dth of area 0 is sp ec ifi ed by the MD 2, MD 1, and MD0 pi ns at re se t time .
123 4.6 Area M ode Register 1 (AMD1 ) 4.6 Area Mode Reg ister 1 (AMD1) Area mode re gister 1 (AMD1) s p ecifies the operation mode of ch ip select are a 1 (area specified by ASR1 and AMR1).
124 CHAPTER 4 BUS INTERFACE 4.7 Area Mode Register 32 (AMD32) Area mode re gister 32 (AMD3 2) contr ols the operation mode of chip sele ct area 2 (area specified b y ASR2 and AMR2) a nd chip se lect area 3 (area spec ified by ASR3 and AMR3 ). These areas are accessed onl y via the usual bus and do not allo w the us e of special DRAM in te rfac es.
125 4.8 Area M ode Register 4 (AMD4 ) 4.8 Area Mode Reg ister 4 (AMD4) Area mode re gister 4 (AMD4) s p ecifies the operation mode of ch ip select are a 4 (area specified by ASR4 and AMR4).
126 CHAPTER 4 BUS INTERFACE 4.9 Area Mode Register 5 (AMD5) Area mode re gister 5 (AMD 5) specifies the bus mode of ch ip select area 5 (area specified by ASR5 and AMR5).
127 4.10 DRAM Control Regis ter 4/5 (DMCR4/5 ) 4.10 DRAM Control Registe r 4/5 (DMCR4/5) DRAM control registers 4 and 5 (DMCR4 and DMCR5) cont r ol the DRAM interface for areas 4 a nd 5 and are v alid only when the DR ME bits of A M D4 and AM D5 are set to " 1".
128 CHAPTER 4 BUS INTERFACE [bit 11] Q1W (Q1 wait bit) The Q1W bit sp ecifies wh ether to extend th e Q1cycle (t he "H" i nterval o f RAS), sp ecified at DRAM acces s time, b y one cy cle. 0: Does n ot extend Q 1 cycle (initial v alue). 1: Exte nds Q1 cycle.
129 4.10 DRAM Control Regis ter 4/5 (DMCR4/5 ) [bit 4] REFE (REFresh E nable bit) The REFE bi t specifi es whether to perform the c yclic refr esh operati on of the CA S before RAS (CBR) ty pe.
130 CHAPTER 4 BUS INTERFACE 4.11 Refresh Control Regis ter (RFCR) The refresh contr ol regist er (RFCR) controls the CBR (CAS bef ore RAS) refresh operation when t he DRAM interface is used.
131 4.11 Refresh Control Re gister (RFCR) [bit 2] STR (STaRt bit) The STR bit controls or starts a nd stops the downw ard counter . 0: STOP (initial val ue) 1: START When the STR is set, th e REL value i s loaded into the d ownward coun ter.
132 CHAPTER 4 BUS INTERFACE 4.12 Externa l Pin Control Reg ister 0 (EPCR0) External pin contr ol register 0 (EPCR0) contr ols the output of each signal. When output is permitted, this register outputs a desired timing signal in eac h bus mode . When the input is v alid, it receives an input signal fr om the outside .
133 4.12 E xternal Pin Control Re gister 0 (EPCR0 ) [bit 8] BRE (Bus Request Enabl e bit) The BRE bi t controls the BR Q and BGRNTX signals as descr ibed below. When thi s bit is r eset, the B RQ input becomes in valid an d the BGRN TX outpu t is inhibi ted.
134 CHAPTER 4 BUS INTERFACE [bit 0] COE0 (Chip sele ct Output Enable 0) The C0E0 bi t controls the CS0X output. Wh en this bi t is rese t, output is permitt ed. 0: Inhibi ts output. 1: Perm its outpu t (initial value). When the ex ternal bu s mode i s used, the C0E0 bit per forms no I/O por t control for the CS 0X pin.
135 4.13 E xternal Pin Control Re gister 1 (EPCR1 ) 4.13 External Pi n Control Reg ister 1 (EPCR1) External pin contr ol register 1 (EPCR1) controls address signal output.
136 CHAPTER 4 BUS INTERFACE 4.14 DRAM Sig nal Control Registe r (DSCR) The DRAM signal control register (DSCR) controls the output of each DRAM control signal.
137 4.14 DRAM Signal Control Register (DSCR) [bit 3] C0HE The C0HE bi t controls the CS0H ou tput. When this bit is reset, t he output i s inhibited . 0: Inhibi ts output (initial val ue). 1: Per mits outp ut. [bit 2] C0LE The C0LE bi t controls the CS0L o utput.
138 CHAPTER 4 BUS INTERFACE 4.15 Little Endian R egister (LER) When b us access b y the MB91F109 is performe d, the whole a rea is usual ly compose d of big endians. Ho we ver , setting the little endian register (LER) makes it possib le to handle one of ar eas 1 t o 5 as a littl e endian ar ea .
139 4.16 Relationship between Data Bus Widths and Control Signals 4.16 Relationship between Data Bus Widths and Control Sig nals Data bus control signals (W R0X-WR1 X, CS0H, CS 0L, CS1L, CS1H , D W0X, and D W1X) alwa ys correspond to data b u s by te locations on a one-to-one basis, regardless of big and little endians and data b us widths.
140 CHAPTER 4 BUS INTERFACE T able 4.16-1 Rela tionship between Data Bus Widths and Control Signals Bus width 16-bit bus width 8-bit bus width Data bus WR 2CA S/1WE 1CAS /2WE WR 2CAS/1W E 1CAS/2 WE D3.
141 4.16 Relationship between Data Bus Widths and Control Signals 4.16.1 Bus Access with Big Endia ns When externa l b us acce ss is performed for area s not set by the little endi a n regist er (LER), those area s are handled as big endian s. The FR series usually em plo ys big endians.
142 CHAPTER 4 BUS INTERFACE ❍ Byte access (during e xecution of LDUB a nd STB instructions) Figure 4.16-5 Relationship betwee n Internal Register and External Data Bus for Byte Access ■ Data Bus Wi dth The follo wing sho ws the r elation ship bet ween the internal register and ex ternal dat a bus fo r each data bus width .
143 4.16 Relationship between Data Bus Widths and Control Signals ❍ 8-bit bus width Figure 4.16-7 Relationship be tween Internal Register and External Da ta Bus for 8-bit Bus Width ■ External Bus Access Figure 4.16 -8 and Figure 4.1 6-9 show exter nal bus acc ess (in a 16- bit or 8-bit bus wid th) in words, h alf-words, and bytes .
144 CHAPTER 4 BUS INTERFACE ❍ 16-bit bus width Figure 4.16-8 E xternal Bus Access for 16-bit Bus Width MSB LSB 00 01 00 01 00 01 10 11 10 11 10 11 16bit 00 01 00 01 00 01 10 11 10 11 10 11 00 01 00 .
145 4.16 Relationship between Data Bus Widths and Control Signals ❍ 8-bit bus width Figure 4.16-9 E xternal Bus Acce ss for 8-bit Bus Width P A1/P A0 : Lower 2 bits of address specified b y program .
146 CHAPTER 4 BUS INTERFACE ■ Example of Connection to External Devices Figure 4.16-10 E xample of Connection between M B91F109 and Ex ternal Devices MB91F109 WW D31 R D23 R 0 1 D24 X D16 X 0 1 X D15 D08D07 D00 D07 D00 16-bit de vice* 8-bit device* * F or the 16/8-bit de vice, the data bus on the MSB side of the MB91F109 is used.
147 4.16 Relationship between Data Bus Widths and Control Signals 4.16.2 Bus Access with Little Endian s When e xt ernal b us access is pe rf ormed for a rea s se t b y the litt le e ndian regi st er (L ER) , those area s are handled as little endians.
148 CHAPTER 4 BUS INTERFACE ❍ Half-wor d acces s (during ex ecution of LDUH and STH instructions) Figure 4.16-12 Relationship between Internal Register and Extern al Data Bus for Half-w or d Access ❍ Byte access (during e xecution of LDUB a nd STB instructions) Figure 4.
149 4.16 Relationship between Data Bus Widths and Control Signals ■ Data Bus Wi dth The follo wing sho ws the r elation ship bet ween the internal register a nd exter nal data bus fo r each data bus width : ❍ 16-bit bus width Figure 4.
150 CHAPTER 4 BUS INTERFACE ■ Example of Connection to External Devices ❍ 16-bit bus width Figure 4.16-16 Ex ample of Connection between MB91F10 9 and External Devices (16-Bit Bus Width) ❍ 8-bit bus width Figure 4.
151 4.16 Relationship between Data Bus Widths and Control Signals 4.16.3 Extern al Access This secti on lis ts se veral e xternal access es. ■ W ord Access Bus width Big endian mode Lit tle endian m.
152 CHAPTER 4 BUS INTERFACE ■ Half-W ord Access Bus width Big endian mode Lit tle endian mode 16-bit b us width 8-bit bu s width address: 0 D31 D31 AA WR0X CASL WEL BB WR1X CASH WEH D16 AA BB D00 1).
153 4.16 Relationship between Data Bus Widths and Control Signals ■ Byte Ac cess Bus width B ig endian mode Little endian mode 16-bit b us width address: '0' D31 D31 AA WR0X CASL WEL D16 A.
154 CHAPTER 4 BUS INTERFACE 8-bit bu s width Bus width B ig endian mode Little endia n mode address: D31 D31 AA WR0X CAS WE D24 AA D00 '0' 1) Control pin Inter nal register External pin addr.
155 4.16 Relationship between Data Bus Widths and Control Signals 4.16.4 DRAM R elationships This section e xplains the DRAM relat ionships. ■ DRAM Control Pins Table 4.16 - 2 lists the rel ationship between the pin functions a nd bus widths use d in the DRAM interfac e.
156 CHAPTER 4 BUS INTERFACE ■ Row and Column Addresses The page siz e select bits (PGS3 to PGS0) o f DRAM con trol regi sters 4 and 5 ( DMCR4 and DMCR5) dete rmines whe ther to create DRAM interface ad dresses. When the high-sp eed page mode is used , PGS3 to PGS0 and the data bus width determi ne whether acces s is within a page.
157 4.16 Relationship between Data Bus Widths and Control Signals ❍ 16-bit data bus (using 2 DRAMs) Figure 4.16-19 Ex ample of Connection between MB91F109 and T wo 8-Bit Outpu t DRAMs (16-Bit Data B.
158 CHAPTER 4 BUS INTERFACE ■ Connection Example of DR AM Device • DRAM: 2CA S/1WE, p age size 512, × 16 -bit produc t • Bus wid th: 16 bits • Number o f banks: 2 (areas 4 and 5) Figure 4.
159 4.17 Bus Timing 4.17 Bus Timing This section pro vides b us access timing charts used in eac h mode and e x plains b us access ope ration f or the f ollowing items: • Usual b u s acc es s • Wa.
160 CHAPTER 4 BUS INTERFACE ❍ Usual DRAM interfac e The us ual DRAM inte rfac e conv erts the CAS cycle to a 2-clock cy cle by set ting the D SAS an d HYPR bit s o f DM CR4 a nd DCMR5 to "0". It h andl es " 5- cloc k cyc le s" as ba si c bus c y cles du ring read and write ope rations.
161 4.17 Bus Timing • Hyper DR AM inter face: Read • Hyper DR AM inter face: Write • Hyper DR AM inter face ■ DRAM R efresh • CAS befor e RAS (CBR) r efres h • Automatic wait cycle of CBR .
162 CHAPTER 4 BUS INTERFACE 4.17.1 Basic Read C yc le This section pro vides a cha r t of the basic read c yc le timing. ■ Basic Rea d Cycle Timing Chart ❍ Bus width: 16 bits, access: words, CS0 area ac cess Figure 4.17-1 Example of Basic Read Cycle Timing Char t [Explanation of operation] • CLK o utputs ex ternal bu s operat ion cloc ks.
163 4.17 Bus Timing • Output of CS0 X to CS5X (area chip select) si gnals is asser ted from the beg inning (BA1 ) of bus cy cles; t hat is , at the same time as A24- A00.
164 CHAPTER 4 BUS INTERFACE 4.17.2 Basic Write Cycles This sect ion pro vides a char t of the basic writ e cyc le timi ng. ■ Basic Wr ite Cycle Timing Char t ❍ Bus width: 8 bits, access: words, CS0 area acc ess Figure 4.
165 4.17 Bus Timing specif ied area s ar e 8 b its wide , D2 3 to D 16 auto matic ally be come I/O p orts, wh ich are set to High-Z. The above examp le sh ows the case, wh ere D2 3 to D16 and WR 1X ar e used as I/O p orts.
166 CHAPTER 4 BUS INTERFACE 4.17.3 Read Cycles in Eac h Mode This section pro vides read cyc le timing charts in each mode . ■ Read Cycle Timing Char ts ❍ Bus width: 16 bits, acces s: half-w ords Figure 4.17-3 Example 1 of Read Cycle Timing Char t ❍ Bus width: 16 bits, ac cess: bytes Figure 4.
167 4.17 Bus Timing ❍ Bus width: 8 bits, acc ess: half-wor ds Figure 4.17-6 Example 4 of Rea d Cycle Timing Chart ❍ Bus width: 8 bits, acc ess: bytes Figure 4.
168 CHAPTER 4 BUS INTERFACE 4.17.4 Write Cycles in Each Mode This section pro vides write cyc le timing charts in each mode. ■ Write Cycle Timing Chart ❍ Bus width: 16 bits, ac cess: wor ds Figure 4.17-8 Example 1 of Write Cycle Timing Chart ❍ Bus width: 16 bits, acces s: half-w ords Figure 4.
169 4.17 Bus Timing ❍ Bus width: 8 bits, acc ess: half-wor ds Figure 4.17-11 Example 4 of Write Cycle Timing Char t ❍ Bus width: 8 bits, access : bytes Figure 4.
170 CHAPTER 4 BUS INTERFACE 4.17.5 Read and Write Combination C yc les This section pro vides a read and write combination cyc le timing char t. ■ Read and Write Combination Cycle Timing Char t ❍ CS0 area: 1 6-bit bus width, wor d read CS1 area: 8-bit bus width, half-w or d r ead Figure 4.
171 4.17 Bus Timing 4.17.6 A u tomatic W ait Cyc les This sect ion pro vides an automatic w ai t cyc le tim ing char t. ■ Au tomatic W ait Cycle Timing Chart ❍ Bus width: 16 bits , access: half- w ord read/writ e Figure 4.
172 CHAPTER 4 BUS INTERFACE 4.17.7 External W ait Cyc les This sect ion pro vides an e xternal wait cycle timing char t. ■ External W ait Cy c le Timing Char t ❍ Bus width: 16 bits , access: half- w ords Figure 4.
173 4.17 Bus Timing 4.17.8 Usu al DRAM Interface: Read This section pro vides a usual DRAM interface read timing chart. ■ Usual DRAM Int erface: Read Timing C hart ❍ Bus width: 16 bits, access: w o rds, CS4 area access Figure 4.
174 CHAPTER 4 BUS INTERFACE edge of CA SL or CA SH for the 2CAS/1WE. For the 1CAS/2 WE, CAS correspon ds to D31 to D16 . For the 2CAS/1 WE, CASL correspond s to D31 to D24, and CAS H correspon ds to D23 to D16. In read cy cles, all o f D31 to D 16 are fetche d, irresp ective o f the bus wi dth and wor d, half- word, and byte acces s.
175 4.17 Bus Timing 4.17.9 Usu al DRAM Interface: Write This sect ion pro vides a usua l DRAM int er face wr ite timi ng char t. ■ Usual DRAM Int erface: Write Timing Char t ❍ Bus width: 16 bits, access: w o rds, CS4 area access Figure 4.
176 CHAPTER 4 BUS INTERFACE In an 8-bit data bus wi dth, write da ta is output from D31 to D24. • RAS is similar t o that at re ad cycles . • CAS is also simi lar to tha t at read c ycles.
177 4.17 Bus Timing 4.17.10 Usual DRAM Read C yc les This section pro vides usual DRAM re ad cyc le timing c ha rt s. ■ Usual DRAM Re ad Cycle Timing Charts ❍ Bus width: 16 bits , access: half- w ords Figure 4.17-18 Example 1 of Usual DRAM Read Cycle Timing Char t Q1 Q2 Q3 Q4 Q5 CLK A24-00 X #0 row .
178 CHAPTER 4 BUS INTERFACE ❍ Bus width: 16 bits, access: bytes Figure 4.17-19 Example 2 of Usual DRAM Read Cycle Timing Char t ❍ Bus width: 8 bits, access : half-w ords Figure 4.17-20 Example 3 of Usual DRAM Read Cycle Timing Char t Q1 Q2 Q3 Q4 Q5 Q1 Q2 Q3 Q4 Q5 CLK 1)1CAS/2WE A24-00 X #0 row .
179 4.17 Bus Timing 4.17.11 Usual DRAM Write Cyc les This section pr ovides usual DRAM write cyc le timing char ts. ■ Usual DRAM Wri te Cyc l e Timing Char ts ❍ Bus width: 16 bits , access: half- w ords Figure 4.17-21 Example 1 of Usual DRAM Write Cycle Timing Char t Q1 Q2 Q3 Q4 Q5 CLK 1CAS/2WE A24-00 X #0 row .
180 CHAPTER 4 BUS INTERFACE ❍ Bus width: 16 bits, access: bytes Figure 4.17-22 Example 2 of Usual DRAM Write Cycle Timing Char t ❍ Bus width: 8 bits, access : half-w ords Figure 4.17-23 Example 3 of Usual DRAM Write Cycle Timing Char t Q1 Q2 Q3 Q4 Q5 Q1 Q2 Q3 Q4 Q5 CLK 1)1CAS/2WE A24-00 X #0 row .
181 4.17 Bus Timing 4.17.12 A utomatic W ait Cyc les in Usual D RAM Interfac e This section pr ovides an automatic wait cycle timing chart in t h e us ual DRAM interface. ■ Au tomatic W ait Cycle Timing Chart in Us ual DRAM Interface ❍ Bus width: 8 bits, acc ess: bytes Figure 4.
182 CHAPTER 4 BUS INTERFACE 4.17.13 DRAM Interface in High -Speed P age Mode This section pro vides DRAM interface ope ration timing charts in high-speed page mode . ■ DRAM Interface Timing Char ts in High-Speed P age M ode ❍ Read cycle, bus width: 16 bits, a ccess: wor ds Figure 4.
183 4.17 Bus Timing [Explanation of operation] • Write control is perfor med with only the CAS control signals (includ ing CASL and CA SH) while RA S is low ered to "L", and then W E (inc luding W EL and WEH ) is lowered to "L". • Column ad dresse s and outp ut data ar e output in Q4 and Q 5 cycles .
184 CHAPTER 4 BUS INTERFACE ❍ Combination of high-speed page mode and basic b us cyc le Figure 4.17-28 Example 4 of DRA M Interface Timing Char t in High-Speed Pa g e Mode [Explanation of operation] • Even i f the CS area switches and anoth er CS area is accessed , RAS remai ns at "L" in high- speed pa ge mode.
185 4.17 Bus Timing 4.17.14 Single DRAM I nterface: Read This section pr ovides a read timing chart for a single DRAM interfa ce. ■ Single DRAM Interface: Read Timing Char t ❍ Bus width: 16 bits , access: words Figure 4.
186 CHAPTER 4 BUS INTERFACE 4.17.15 Single DRAM Interface: Write This section pr ovides a single DRAM interface writ e timing char t. ■ Single DRAM Interface: Write Timing Char t ❍ Bus width: 16 bits, access: wo rds Figure 4.
187 4.17 Bus Timing 4.17.16 Single DRAM I nterface This section pr ovides a single DRAM interface timing char t. ■ Single DRAM I nterface Timing Char t ❍ Combination of single DRAM and basi c bus cyc le , CS switch-o ve r Figure 4.
188 CHAPTER 4 BUS INTERFACE 4.17.17 Hyper DRAM Interfa ce: Read This section pr ovides a hyper DRAM interface timing char t. ■ Hyper DRAM Interface: Read Timing Char t ❍ Bus width: 16 bits, access: wo rds Figure 4.
189 4.17 Bus Timing 4.17.18 Hyper DRAM In terface: Write This section pr ovides a hy per DRAM interface write timin g char t. ■ Hyper DRAM Interface: Write Timing chart ❍ Bus width: 16 bits , access: words Figure 4.
190 CHAPTER 4 BUS INTERFACE 4.17.19 Hyper DRAM Interface This section pr ovides a hyper DRAM interface timing char t. ■ Hyper DRAM Interface Timing Char t ❍ Combination of hyper DRAM and basic bus cyc le , CS switch-o v er Figure 4.
191 4.17 Bus Timing 4.17.20 DRAM Refresh This section pro vides DRAM refresh timing char ts. ■ CAS before RAS (CBR) Refresh Figure 4.17-35 Example of CAS bef ore RAS (CBR) Refresh Timing Char t [Explanation of operation] • When execu ting CBR refre sh, set the REFE bit of DMC R4 and DMCR5 and the STR bit of the RFCR.
192 CHAPTER 4 BUS INTERFACE ■ Au tomatic W ait Cycle of CBR Refresh Figure 4.17-36 Example of Timing Char t of CBR Refres h A utomatic Wait Cyc le [Explanation of operation] • When in serting a CB R refresh auto matic wait c ycle, set the R3 W bit of th e RFCR.
193 4.17 Bus Timing 4.17.21 External Bus Requ est This section pro vides ex ternal b us request timing charts. ■ Bus Control Release Figure 4.17-38 Example of Bus Control Release Timing Chart [Explanation of operation] • When per forming bu s arbitrat ion by BR Q and BGRNTX, set th e BRE bit of EPC R0 to "1".
194 CHAPTER 4 BUS INTERFACE 4.18 Internal Clo ck Multiplicatio n (Clock Doub ler) The MB91F109 has a c lock m ultiplication circuit with whic h the inside of the CPU operates at a frequency one or two times t hat of the b us interface. The b us interface operates synchr onously with the CLK output pin regar dless of which c lock is chosen.
195 4.18 Internal Cl ock Multiplication (Clock Doubler ) Figure 4.18-2 Example of Timing fo r 1X Cloc k (BW -16bit, Acc ess-W ord Read) Internal clock Internal instr uction Internal instr uction CLK o.
196 CHAPTER 4 BUS INTERFACE 4.19 Program Example for Ex ternal Bus Operation This section pr ovides a simple pr ogram example f or external b us operation.
197 4.19 Progra m Example for External Bu s Operation stb r0, @r1 Wri te to dscr r egister init_amd 0 ldi:8 #0x08,r 0 // 16- bit bus, 0 -wait ldi:20 #0x620 ,r1 // amd0 r egister add ress s etting stb .
198 CHAPTER 4 BUS INTERFACE //Exter nal bus a ccess ldi:20 #0x626 ,r1 // rfcr r egister add ress setti ng sth r0,@ r1 // write to rfcr regist er init_a sr ldi: 32 #0x 001 300 1,r 0 // asr1 and amr1 re.
199 4.19 Progra m Example for External Bu s Operation ldi:32 #0x001 a6b8c, r 6 // CS5 addr ess (with in the pag e) ldi:32 #0x001 a6c00, r 7 // CS5 addr ess (outs ide of the page) bus_acc ld @r0, r 8 /.
200 CHAPTER 4 BUS INTERFACE.
201 CHAPTER 5 I/O POR TS This chapter outlines the I/O por ts and explains the register configuration and the requirements f or using external pins as I/ O pins. 5.1 Outlin e of I/O Port s 5.2 Port Da ta Registe r (PDR) 5.3 Data Direction Reg ister ( DDR) 5.
202 CHAPTER 5 I/O PORTS 5.1 Outline of I/O Ports When a resour ce is not allowed to use the corresponding pin as an I/O , the MB91F109 allo ws the pin to b e used as an I/O po rt. ■ Basic Block Diagram of I/O P or ts Figure 5. 1-1 show s the basic I/O port co nfigurati on.
203 5.2 Port Data Register (PDR) 5.2 Port Data Reg ister (PDR) The port data register s (PDR2 to PD RF) are I/O port I/O data register s. The corresponding data direction registers (DDR2 to DDRF) perf o rm I/O contr ol.
204 CHAPTER 5 I/O PORTS 5.3 Data Direction Reg ister (DDR) The data direction registers (DDR2 to DDRF) contr ol the I/O direction of the corresponding I/O ports in bit units.
205 5.4 Using Exter nal Pins as I/ O Ports 5.4 Using Extern al Pins as I/O Ports T able 5.4-1 lis ts the relationship between the initial v alue for e a ch exte rnal pin and the register specifying whether to use the e x ternal pin as an I/O port or control pin.
206 CHAPTER 5 I/O PORTS 23 P81 P81 EPCR0 (B RE bit) 0: P81 1: BGRNTX BGRNTX 24 P82 P82 EPCR0 (B RE bit) 0: P82 1: BRQ BRQ 25 P83 P83 EP CR0 (RDXE bit) 0 : P83 1 : RDX RDX T able 5.4-1 E xternal Bu s Functions to be Se lected (1 /4) Pin No. P in code Initial value Switch-over register T able 5.
207 5.4 Using Exter nal Pins as I/ O Ports 4 PB5 PB5/DREQ2 DSCR (C1 LE) 0: PB 5 1: CS1L Pin va lues ar e always input to DESQ2. CS1L DREQ2 5 PB6 PB6 DS CR (C1HE bit) and D ATCR (AKSE2 , AKDE2 bi ts) C.
208 CHAPTER 5 I/O PORTS 81 P F2 PF2/SC0 (input) PCNL (POE N) 0: PF2 1: OPCA3 SMR (SCKE) 0: pin values ar e input to SC0 during opera tion. 1: SC0 (outp ut) OPCA 3 SC0 82 P F3 PF3/SI1/TRG2 Pin values are a lways i nput to SI1 and TRG2 ( during o peration).
209 5.4 Using Exter nal Pins as I/ O Ports T able 5.4-4 Exter nal Bus Functions to be Se lected (4/4) Pin No. Pin code Initial value Switch-over register 74 AVSS (AVRL) AVSS (AVRL) - 17 RSTX RSTX - 95.
210 CHAPTER 5 I/O PORTS.
211 CHAPTER 6 EXTERNAL INTERR UPT/NMI CONTROLLER This chapter explains the ge neral outlines of the external interrupt/NMI contr oller , configuration/functions of registers, and operations of the e xternal interrupt /NMI controll er . 6.1 Overview o f External Interrupt/NMI Controller 6.
212 CHAPTER 6 EXTERNAL INTERRUPT/N MI CONTROLLER 6.1 Overview of External In terrupt/NMI Controller The ex ternal interrupt/NMI contr oller is a b lock that contr ols an e xternal interrupt request input to NMIX or INT0 to INT3.
213 6.2 Enable Inter rupt Request Register (ENIR ) 6.2 Enable Interrupt Requ est Register (ENIR) The enable interrupt request register (ENIR) is used to mask the output of an e xternal interrupt request.
214 CHAPTER 6 EXTERNAL INTERRUPT/N MI CONTROLLER 6.3 External Interrupt Request Register (EIRR) When the e xternal interrupt request register (EIRR) is read, it indic ates that there are external interrupt requests. When it is written, the flip-flops indicating these requests are c leared.
215 6.4 E xternal Lev el Register (ELVR ) 6.4 External Level R egister (ELVR) The external level register (EL VR) selects the request detection mode . ■ External Level Registe r (EL VR) The config uration of the exte rnal level register (ELVR) is shown be low: The external level r egister ( ELVR) sel ects the request dete ction mod e.
216 CHAPTER 6 EXTERNAL INTERRUPT/N MI CONTROLLER 6.5 External Inte rrupt Op eration After the external level re gister a nd enable inter r upt request r egister are set, the request set in the EL VR register is input to the corresponding pin. This module then issues an interrupt request signal to the interrupt contr oller .
217 6.6 Ext ernal Interrupt Re quest Levels 6.6 External Inte rrupt R equest Levels When an edg e is selecte d f or the interrupt reque st mode , a pulse widt h of at least three machine cycles (periphe ral clock machine cycles) is requi red to detect an edg e .
218 CHAPTER 6 EXTERNAL INTERRUPT/N MI CONTROLLER 6.7 Nonmaskable Interrup t (NMI) Operation NMI is the interrupt with the highest priority among other user in terrupts. It can onl y be masked during the period fr om immediat ely after a reset to the completion of the ILM setting.
219 CHAPTER 7 DELAYED INTERRUPT MODULE This chapter pro v ides an overview of the dela yed interrupt module and explains the register configuration and functions and the operations of the delay ed interrupt module . 7.1 Over view of Delayed Interrupt Modu le 7.
220 CHAPTER 7 DELAYED INTERRUPT MODULE 7.1 Overview of De layed Interrupt Modu le The dela yed interrupt module causes an interrupt for changing a task. Software can use this module to issue or cancel an interrupt request to the CPU . ■ Delaye d Inte rrupt Module Register Figure 7.
221 7.2 Delayed Interrupt Control Regis ter (DICR) 7.2 Delayed Interrupt Control Register (DIC R) The dela yed interrupt contr ol register (DICR) is used to contro l dela yed interrupts.
222 CHAPTER 7 DELAYED INTERRUPT MODULE 7.3 Operati on of D elaye d Int errupt Modul e The dela yed interrupt module causes an interrupt for changing a task.
223 CHAPTER 8 INTERRUPT CON TR OLLER This chapt e r pro vides an o verview of t he inte rrupt controll er and expl ains the register configuration and functions and the operations of the interrupt contr oller . The ch apter also explains the hold r e quest cancel request function using examples.
224 CHAPTER 8 INTERRUPT CONTROLLER 8.1 Overview o f Interrupt Cont ro ller The interrupt controller accepts interrupts and perf orms arbitrat ion over them.
225 8.1 Ov erview of Interrupt C ontroll er ■ Interrupt Contr olle r Registers Figure 8. 1-1 shows th e interrup t controlle r registers . Figure 8.1- 1 Interr upt Controller Regist ers (1/2) bit7 6.
226 CHAPTER 8 INTERRUPT CONTROLLER Figure 8.1- 2 Interr upt Controller Reg isters (2/2) bit7 6543210 Address:00000420 H Address:00000421 H Address:00000422 H Address:00000423 H Address:00000424 H Addr.
227 8.2 Interrupt Controller Block Dia gram 8.2 Interrupt Controller B lock Diagram Figure 8.2-1 is an interrupt controller b lock diagram. ■ Interrupt Contr oller Block Diagram Figure 8.
228 CHAPTER 8 INTERRUPT CONTROLLER 8.3 Interrupt Control Register (ICR) One interrupt contr ol regist er is pr ovided f or each type of interrupt input and is used to set the interrupt level of the corr esponding interrupt request.
229 8.3 Interrupt Control Register (ICR ) ICR4 is fi xed to "1 " and cannot be set to "0 ". T able 8.3-1 Correspondences between the Interrupt Level Setting Bits and Interrupt Leve.
230 CHAPTER 8 INTERRUPT CONTROLLER 8.4 Hold Request Cance l Request Level Setting Reg ister (HRCL) The HRCL register is used to s et the interrupt level f or issuing a hold request cancel request.
231 8.5 Priorit y Check 8.5 Priority Check IWhen m ultiple interrupt causes are generated si m ultaneousl y , this module selects one having the highest priority and posts the interrupt level and number of the cause to the CPU . NMI is given the highest priority among the int errupt causes handled b y this module.
232 CHAPTER 8 INTERRUPT CONTROLLER DMAC 2 (end, error) 28 1C ICR12 38 C H 000FFF8C H DMAC 3 ( end, error) 29 1D ICR1 3 388 H 000FFF88 H DMAC 4 ( end, error) 30 1E ICR14 384 H 000 FFF84 H DMAC 5 ( end,.
233 8.5 Priorit y Check ■ Nonmaskable Interrupt (N MI) When NMI o ccurs s imultaneo usly with ot her interr upts, NMI i s alway s selected . ❍ When NMI occurs, the following types of information a.
234 CHAPTER 8 INTERRUPT CONTROLLER 8.6 Returning from the Stan dby Mode (Stop/Slee p) This module implements the function to return fr om standby mode when an i nt errupt request is issued.
235 8.7 Hold Request Cancel Request 8.7 Hold Req uest Cancel Request For processing a high-priority int errupt while the CPU is i n hold state, cancellation of the hold request must be requested from the sour ce f or the hold request . The interrupt level used to determine whether to issue a c ancel request must be set in the HRCL register .
236 CHAPTER 8 INTERRUPT CONTROLLER 8.8 Example of Using the Ho ld Request Cancel Req uest Function (HRCR ) When the CPU is to perform priority pr ocessing during DMA transfer , the DMA side must cancel the hold request and release the CPU fr om the hold stat e .
237 8.8 Exa mple of Using the Hold Request Cancel Request Function (HRCR) ■ Hold Request Cancel Request Sequence ❍ Example of interrupt r outine Figure 8.8-2 Example of Timing for Hold Request Cancel Re quest Sequence (Interrupt Level: HRCL > a) The inter rupt le vel change s when an inte r rupt req uest is issued.
238 CHAPTER 8 INTERRUPT CONTROLLER Exampl e of inter rupt rou tines The above examp le indic ates tha t a prior ity int errupt is caused during e xecutio n of inter rupt routine I.
239 CHAPTER 9 U-TIMER This chapt e r pro vides an o verview of t he U-TIMER a nd explains the register configuration and functions and the operations of the U-TIMER.
240 CHAPTER 9 U-TIME R 9.1 Overview of U-TIMER The U-TIMER is a 16-bit timer that generates a U AR T baud rate. Combining the chip operating frequency and U-TIMER reload v alue can g e nerate a desired baud rate . Since a count underflow causes an i n terrupt, the U-TIMER can also be used as an interval tim er .
241 9.2 U-TIMER Registers 9.2 U-TIMER Reg isters The f ollow ing three U- TIMER register s are used: • U-TIME R (UTIM) • Reload register (UTIMR ) • U-TIMER cont r ol register (U TIMC) ■ U-TIMER (UTIM) The UTIM indi cates the ti mer value. Acces s it using a 16-bit tra nsfer in struction.
242 CHAPTER 9 U-TIME R In additi on to a nor mal 2(n +1) cycle cl ock, an o dd frequen cy clock can be set for the UAR T. Setting 1 in UCC1 generates 2n+3 cycle clock pulses.
243 9.3 U-TIMER O peration 9.3 U-TIMER Operatio n This section explains how to calculate the U-TIMER baud rate and also explains the cascade m o de . ■ Calculating the Baud Rate The UART uses the underfl ow flip-flop (f. f. in the figure) of the corresp onding U-TIMER (U- TIMERx --> UA RTx, x = 0, 1, 2) as the baud r ate clock source .
244 CHAPTER 9 U-TIME R.
245 CHAPTER 10 UART This chapter pr ovides an o ver view of the U AR T and e xplains the register configuration, function s an d the operations of the U AR T . 10.1 Overview of U ART 10.2 Serial Mode Register (SMR) 10.3 Serial Con trol Register (SCR) 10.
246 CHAPTER 10 UART 10.1 Ove rview of UA RT The U ART is a serial I/O port used to implement asynchr onous (start-stop) comm unicat ion or CLK synchr on ous communication.
247 10.1 Over view of UART ■ U ART Bloc k Diagram Figure 10 .1-2 is a UA RT block dia gram. Figure 10.1-2 U ART Bloc k Diagram SC SI SO SIDR SODR MD1 PEN PE MD0 P ORE SBL FRE SMR SCR CL SSR RDRF CS0.
248 CHAPTER 10 UART 10.2 Serial Mod e Register (SMR) The serial mode register (SMR) specifies the U ART operation mode. Set the operation mode while U AR T operation is stopped.
249 10.2 Se rial Mode Regist er (SMR) [bit 1] SCKE (SCLK E nable) When c ommunicatio n is p erformed in CLK synchronou s mod e (mode 2) , this bi t speci fies whether t o use the S C pin as a clock in put pin or a clock output p in. Set this bit to "0 " in CLK a synchron ous mode or external c lock mode.
250 CHAPTER 10 UART 10.3 Serial Con trol Register (SCR) The serial control register ( SCR) controls t he transfer pr ot ocol used f or serial comm unication.
251 10.3 Ser ial Control Register (SCR) <Note> Seven- bit data can be used on ly in no rmal mod e (mode 0) for async hronous (sta rt-stop) communi cation. Use eight- bit data in multipr ocessor mod e (mode 1) or CLK synch ronous communi cation mo de (mode 2).
252 CHAPTER 10 UART 10.4 Serial Inp ut Data Register (SIDR) and Serial Output Data Register (SODR) The serial input data register (SIDR) is a data b uffer register f or receiving data, and the serial output data register (SODR) is a data b uffer register f or transmitting data.
253 10.5 S erial St atus Register (SSR) 10.5 Serial Status Register (SSR ) The serial status register (SSR) consists of flags t hat sho w the U ART operating status.
254 CHAPTER 10 UART [bit 4] RDRF (Receive Da ta Register Full) This bit is an i nterrupt req uest flag in dicating that r eceived data is stored in the SIDR register . The bit is set whe n received d ata is loade d to the SIDR register and cl eared automati cally when the rec eived data i s read from th e SIDR regis ter.
255 10.6 UART Opera tion 10.6 UART Operatio n U A RT has the f ollowing three operation modes, whic h can be changed b y setting a v a lue in the SMR or SCR register . • Asynchronous (star t-stop) normal mode • Asynchronous (star t-stop) multipr ocessor mode • CLK synchronous mode ■ U ART Operation Modes Table 10.
256 CHAPTER 10 UART ❍ Extern al cloc k When the external c lock is s elected with "1" set in CS0 , the baud rate is deter mined as fo llows (f is th e extern al cloc k freque ncy): • Asynchr onous (sta rt-stop) : f/16 • CL K sync hronous : f f can be u p to 3.
257 10.7 A synchronous (Start-Stop) Mode 10.7 Asynchronou s (Start-Stop) Mode The U ART handles data of only NRZ (nonreturn-to-z ero) f ormat. Data transfer begins with a star t bit (L-level data) f or the specified number of data bits in LSB firs t mode and ends with a stop bit (H -le vel data).
258 CHAPTER 10 UART 10.8 CLK Synch ronous Mode The U ART handles onl y dat a of NRZ (nonreturn-to-z ero) f ormat. Figure 10.8-1 shows the relationship between the transmission/reception cloc k and the data. ■ Format of Data T ransferred in CLK Synchronous Mode Figure 10.
259 10.8 CLK Synchronous Mode • SCR regist er •P E N : 0 • P, SBL , A/D: These bits are i nvalid. • CL: 1 • REC: 0 (for in itialization) • RXE, TXE : At leas t one mus t be set to 1 .
260 CHAPTER 10 UART 10.9 UART Interrupt Occurrence and F lag Setting T iming The U ART has five fla gs and two interrupt causes. The five flags are P E, ORE, FRE, RDRF , and TDRE. One of the tw o interrupt causes is for data reception and the other is for data transmissi on.
261 10.9 UART Interrupt Occurre nce and Flag Setting Timing ■ Interrupt Flag Set Timing f or Data Recepion in Mode 1 When the las t s to p bi t i s dete cte d a fter da ta rec ep tio n/tr an sfe r is c omp le ted, the OR E, FRE, a nd RDRF flags are set t o issue an interru pt req uest t o th e CPU.
262 CHAPTER 10 UART ■ Interrupt Flag Set Timing f or Data T ransmission in M ode 0, 1, or 2 TDRE is cle ared when data i s written to the S ODR regis ter.
263 10.10 Notes on Us ing the UART and Example for U sing the UART 10.10 Notes on Usin g the UART and Exam ple for Using the UART This section pro vides an example f or use of the U AR T and notes on using the U ART . ■ Notes on Using the U ART Set the co mmunication mod e while UART o peration is stopped.
264 CHAPTER 10 UART Figure 10.10-2 Comm unication Flo wchar t for Mode 1 END Yes No Yes No START (Host CPU) Set "0" in A/D Communication with slave CPU Set transfer mode to 1 Set address dat.
265 10.11 Setting Examples of Baud Rates and U-TIMER Reload Values 10.11 Setting Examples of Baud Rates and U-TIMER Relo ad Values T ables 10 .11-1 a nd 10.11-2 ar e sample settings f or baud rates a nd U-TIMER reload va l u es . The frequencies in the ta bles indicate peripheral machine c lock frequencies.
266 CHAPTER 10 UART.
267 CHAPTER 11 A/D CONVERTER (Suc cessive approximation type) This chapt e r pro vides an o verview of t he A/D co n verter and ex plains the registe r configuration and functions and the operations of the A/D con ver ter . 11.1 Ove r view of A/D Converter (Successive Appr oximat ion Type) 11.
268 CHAPTER 11 A/D CONVERTER (Succe ssive approximation type ) 11.1 Ove rview of A/D Con verter (Successive App roximation Type) The A/D con verter conv er ts analog input vo ltage to digital v alues. ■ Char acteri stics o f A/D Con verter • Minimum convers ion time: 5.
269 11.1 Overvi ew of A/D Converter (Succe ssive Approximat ion Type) ■ A/D Con ver ter Block Dia g ra m Figure 11 .1-2 is an A /D convert er block d iagram.
270 CHAPTER 11 A/D CONVERTER (Succe ssive approximation type ) 11.2 Con trol Status Register (A DCS) The control status register (ADCS) c ontrols the A/D con ver ter and displa y s status inf ormation. Do not rewrite the ADCS during A/D con version. Do not use a Read Modify Write (RMW) instruction to access it.
271 11.2 Contro l Status Register (ADCS) <Note> Set the bi t to "0" fo r cleari ng it whil e A/D conver sion is s topped. The bit is initial ized to "0" when the r egister is reset. A Read Mo dify Wr ite instr uction r eads "1 " from th is bit.
272 CHAPTER 11 A/D CONVERTER (Succe ssive approximation type ) <Notes> The external pin trigge r signa l is detecte d on the falling edge . If the bit s etting is changed to select an external tr igger m ode while t he external trigger in put leve l is low , the A/ D conv erter may start .
273 11.2 Contro l Status Register (ADCS) <Note> A/D conv ersion that is s tarted in continuou s conve rsion m ode or c onvert-and -stop mo de continue s until t he BUSY b it stops it. Writin g "0" to t he BUSY b it stops A/D co nversion.
274 CHAPTER 11 A/D CONVERTER (Succe ssive approximation type ) If the sam e channel as that se t by ANS2 t o ANS0 i s set, on ly one ch annel is su bjected to A/ D conve rsion (s ingle co nversi on mode) .
275 11.3 Data Regis ter (ADCR) 11.3 Data Register (ADCR) The data register (ADCR) is use d to store a digital va lue that is the con version result. ■ Configuration of Data Regis ter (ADCR) The conf.
276 CHAPTER 11 A/D CONVERTER (Succe ssive approximation type ) 11.4 A/D Co nverter Operation The A/D con ve r te r operates i n successive appro ximation m ode and features a 10 -bit resolution. The A/D con ver ter has only one register (1 6 bits) to s t or e the co n version result s.
277 11.4 A/D Converter Operation In conti nuous conversi on mode, t he A/D converter continu es conv ersion until the BUSY bit is set to "0 ". Writin g "0" to th e BUSY bi t forcibly terminates A/D conv ersion. Note that fo rced termi nation in terrupts c onversion in prog ress.
278 CHAPTER 11 A/D CONVERTER (Succe ssive approximation type ) 11.5 Con version Data Protection Functi on The A/D con verter of the MB91F109 has a con version data pr otection function that features contin uo us con ver sio n using DMA C and securing m ultiple data items.
279 11.5 Conversion Data Protection Function Figure 11.5-1 W orkflow of the Data Pr otection Function when DMA T ransfer is Used NO YES YES NO * End DMAC end interrupt routine Set DMAC The workflow for A/D converter termination is omitted.
280 CHAPTER 11 A/D CONVERTER (Succe ssive approximation type ) 11.6 Notes on Using the A/D Con verter This section pro vides notes on using the A/D con ver ter ■ Notes on Using the A/D Converter ❍.
281 CHAPTER 12 16-BIT RELOAD TIMER This chapt e r pro vides an o verview of t he 16-bit reload timer , and explains the register configuration and functions, and operations of the 16-bit reload timer . 12.1 Ov erview o f 16-Bi t Reload Timer 12.2 Cont rol Stat us Regis te r (TMCSR ) 12.
282 CHAPTER 12 16-BIT RELOAD TIMER 12.1 Ove rview of 16-bit Reload Ti mer The 16-bit reload timer consists of a 16-bit decrementing counter , 16-bit reload register , internal count c lock pulse generation prescaler , and contr ol reg ister .
283 12.1 Over view of 16-bit Reload Timer ■ 16-Bit Reload Timer Block Diagram Figure 12 .1-2 is a 16 -bit reloa d timer b lock diagram . Figure 12.1-2 16-Bit Re load Timer Block Diagram 16 / / 8 RELD / UF OUTE 16 OUTL 2 / OUT INTE GATE CTL. / 2 UF IRQ CSL1 CNTE CSL0 TRG / 2 IN CTL.
284 CHAPTER 12 16-BIT RELOAD TIMER 12.2 Con trol Status Register (T MCSR) The contr ol status register is used to contr ol the 16-bit timer operation mode and interrupts. Set the bits other than UF , CNTE, and TRG again when CNTE is 0. Sim ultaneous writing is enable d.
285 12.2 C ontrol Status R egister (TMC SR) [bit 3] INTE This is an int errupt enabl e bit. When the UF bit changes to "1" while th is bit is "1" , an interrupt request is issued . No inter rupt reques t is issu ed while th is bit i s "0".
286 CHAPTER 12 16-BIT RELOAD TIMER 12.3 16-Bi t Timer Register (TMR) and 16-Bit Reload Registe r (TMRLR) The 16-bit timer register (TMR) is used to read the count value of the 16-bit timer . The 16-bit reload register (TMRLR) stores the initial count v alue .
287 12.4 Operation of 16-Bit Reloa d Timer 12.4 Operation o f 16-Bit Reload Tim er The 16-bit reload timer perf orms the f ollowing tw o types of operat ion: • Internal cloc k operation • Underflo.
288 CHAPTER 12 16-BIT RELOAD TIMER Figure 12.4-2 Underflow Operation Timing 0000 H (RELD=1) 0000 H FFFF H (RELD=0) -1 -1 -1 Count clock Counter Data loading Underflow setting Underflow set Counter Cou.
289 12.5 Counter States 12.5 Counter States The states of the counter are determined b y the CNTE bit of the control regist er and the internal W ait signal as f ollo ws: CNTE = "0", W ait =.
290 CHAPTER 12 16-BIT RELOAD TIMER.
291 CHAPTER 13 BIT SEARCH MOD ULE This chapter pro v ides an overview of the bi t searc h module . It explains the register configuration, functions, operations, and the sa ve/restore pr ocessing of th e bit searc h module . 13.1 Overview of the Bit Search Module 13.
292 CHAPTER 13 BIT SEARCH MODULE 13.1 Ove rview of the Bit Search Modu le The bit sear ch module searc hes the data written to the input register f or 0, 1, or a c hange point, and returns the detected bit position. ■ Bit Search Module Registers Figure 13 .
293 13. 2 Bit Sea rch Mo dule Re gist ers 13.2 Bit Search Module R egisters The bit searc h module uses the fo llo wing four registers: • 0-detecti on data register ( BSD0) • 1-detecti on data reg.
294 CHAPTER 13 BIT SEARCH MODULE ❍ Read Data save d for the internal status of the bit sea rch module is rea d from this regis ter. When the interr upt handle r uses the bit sear ch modul e, the reg ister is u sed to sa ve the cu rrent statu s and restore i t.
295 13.3 Bit Search Module Operation a nd Save/Restore Processing 13.3 Bit Search Module Ope ration and Save/Restore Processing This section e xplains the operations of the bit searc h mo dule f or 0-detection, 1-detection, and change-point detection and also e xplains save and restore pr ocessing.
296 CHAPTER 13 BIT SEARCH MODULE ■ Change-P oint Dete ction The module scans the data written to the change- point det ection dat a registe r from bit 30 to LSB while comp aring each bit with the MSB value and returns the position whe re the value d ifferent from the MSB was f irst detec ted.
297 13.3 Bit Search Module Operation a nd Save/Restore Processing ■ Save/Restore Processing When the internal status o f the bit sear ch modul e must be saved a nd restored , such as wh en the module i s used in th e interrupt handler , proceed as follows : 1.
298 CHAPTER 13 BIT SEARCH MODULE.
299 CHAPTER 14 PWM TIMER This chapt e r pro vides an o verview of t he PWM time r and expla ins the re gister configuration and functions and the operations of the PWM timer . 14.1 Overvie w of PW M Timer 14.2 PWM Timer Blo ck Diagram 14.3 Control Status Regi ster (PCNH, PCNL) 14.
300 CHAPTER 14 PWM TIMER 14.1 Ove rview of PWM Timer The PWM time r can effici ently output ac curate PW M wa veforms. The MB91F109 contains f our channels of PWM timer .
301 14.1 Ov erview of PWM Timer ■ PWM Timer Registers Figure 14 .1-1 shows the PW M timer re gisters. Figure 14.1-1 PWM Timer Registers 15 0 000000DC H R/W 000000DF H R/W 000000E0 H R 000000E2 H W 0.
302 CHAPTER 14 PWM TIMER 14.2 PWM T imer Block Diagram Figure 14.2-1 is a general block dia gram of the PWM timer . Figure 14.2-2 is a b lo ck diagram of a single PWM timer channel.
303 14.2 PWM Time r Block Diagram ■ Block Diagram of Single PWM Timer Channel Figure 14.2-2 Block Diagram of Single PWM Timer Channel 1/1 cmp 1/4 ck 1/16 1/64 SQ R IRQ PCSR PDUT Prescaler Peripheral.
304 CHAPTER 14 PWM TIMER 14.3 Con trol Status Register (PC NH, PCNL) The contr ol status register (PCNH, PCNL) is used to contr ol the PWM timer or indicate the timer status. Note that the register has a bit that cannot be rewritten during PWM timer operation.
305 14.3 Contr ol Status Regist er (PCNH, PC NL) [bit 12] RTRG: Restart enable bit This bit enables o r disable s restart by a softw are trigger o r trigger input. [bits 11, 10] CKS1, CKS0: Counter c lock select bit These bit s select th e counter clock for th e 16-bit decrementi ng counter.
306 CHAPTER 14 PWM TIMER [bit 5] IREN: Interrupt request enable bit This bit enables o r disable s interrupt r equests. [bit 4] IRQF: Interrupt request flag When the interrupt caus e selected by bits 3 and 2 ( IRS1 and IRS0) is genera ted while bi t 5 (IREN) is set to 1 ( Enable), th is bit is s et to caus e an interr upt request t o the CPU.
307 14.3 Contr ol Status Regist er (PCNH, PC NL) Polarity After resetting Duty cy cle matching Counter borrow Normal polarity O utput of L Invers e polarity O utput of H.
308 CHAPTER 14 PWM TIMER 14.4 PWM C ycle Setting Register (PCSR ) The PWM cyc le set ting regist er (PCSR) is used to set a cyc le . This register has a buff er .
309 14. 5 PWM Duty C ycle Set tin g Regist er (PDUT) 14.5 PWM Duty Cycle Setting Register (PDUT) The PWM duty cyc le sett ing register (PDUT) is used to set a duty c y cle . This register has a b uffe r . A borr ow occurring i n the counter t rigger s a transf er fr om the b uffer .
310 CHAPTER 14 PWM TIMER 14.6 PWM T imer Register (PTMR) The PWM timer register (PTMR) is used to read the val ue of the 16-bit decrementing counter . ■ PWM Timer Register (PTMR) The confi guration of the PWM ti mer regis ter (PTMR) is shown below. Use a 16-bi t data ins truction to access the cycle setting reg ister.
311 14.7 General C ontrol Register 1 (G CN1) 14.7 General Contro l Register 1 (GCN1) The general control register 1 (GCN1) is used to select the sour ce of PWM timer trig ger input. ■ Configuration of General Control Register 1 (GCN1) The config uration of the gener al contro l register 1 ( GCN1) is shown bel ow.
312 CHAPTER 14 PWM TIMER ■ Bit Functions of General Control Register 1 (GCN1) [bits 15-12] TSEL 33-30: ch3 trigger input select bits [bits 11-8] TSEL 23-20: ch2 trigger input sele ct bits T able 14.
313 14.7 General C ontrol Register 1 (G CN1) [bits 7-4] TSEL 13 -10: ch1 trigger input select bits [bits 3-0] TSEL 03 -00: ch0 trigger input select bits T able 14.
314 CHAPTER 14 PWM TIME R 14.8 Gen eral Control Register 2 (GCN 2) The general control regist er 2 (GCN2) is used f or ge nerating a star t trigger b y software . ■ General Control Register 2 (GCN2) The co nfiguration of the gener al contro l register 2 (GCN2) is shown below.
315 14.9 PWM Operati on 14.9 PWM Operation PWM operation outputs pulses continuously . ■ PWM Oper ation. Upon detec tion of a s tart trigg er, the PW M timer outputs pu lses conti nuously. The cycle of o utput puls es can be c ontrolled b y changing th e PCSR v alue, and th e duty ratio can be c ontrolled b y changi ng the PDUT val ue.
316 CHAPTER 14 PWM TIMER ❍ T rigger r estar t disabled Figure 14.9-1 P WM Operation Timing Char t (T r igger Restar t Disabled) ❍ T rigger r estar t disabled Figure 14.9-2 PWM Operation Timing C hart (T rigger Res tart Enabled) m n 0 PWM Start trigger A rising edge is detected.
317 14.1 0 One-Shot Op eratio n 14.10 One-Sh ot Operation One-shot operation outputs a single pulse . ■ One-Shot Oper ation Upon detec tion of a tri gger in one-sho t operatio n mode, the PW M timer can o utput a sing le pulse of arbitrar y width. When an e dge is de tected dur ing operati on while restart is en abled, the counte r is relo aded.
318 CHAPTER 14 PWM TIMER ❍ T rigger r estar t disabled Figure 14.10-1 O ne-Shot Operati on Timing Chart (T ri gger Restar t Disabled) ❍ T rigger r estar t enabled Figure 14.10-2 One-Shot Operation Timing Chart (T rigger Res tart Ena bled) m n 0 PWM Start trigger A rising edge is detected.
319 14.11 Interr upt 14.11 Interrupt Figure 14.11-1 sho ws the causes of interrupts and their timing. ■ Interrupt Figure 14.11-1 Causes of Interrupts and Their Timing (PWM Output: Normal P olarity) 0003 0002 0001 0000 0003 PWM Start trigger Load Clock Count value Interrupt Effective edge Duty cycle matching Counter borrow *: A maximum of 2.
320 CHAPTER 14 PWM TIMER 14.12 Con stant "L" or C onstant "H" Output from PWM Timer Figure 14.12-1 shows ho w the PWM timer ca n keep output at a lo w level . Figure 14.12- 2 shows ho w the PWM timer can keep output at a high le vel.
321 14.13 Starting Multiple PW M Timer Channels 14.13 Starting Multip le PWM Timer Chan nels General contr ol registers 1 and 2 (GCN1 and GCN2) can be used to start mul t iple PWM timer channels. Selecting a s t ar t trigger with the GCN1 re gister enables si multaneous s tart of m ultiple channels.
322 CHAPTER 14 PWM TIMER ■ Starting M ultiple PWM Timer Channels Using the 1 6-Bit Reload Timer In step 3) of the foregoi ng setting procedure, se lect the 16 -bit reload timer as the start trigg er in GCN1 and then star t the 16-bit r eload timer instead of GCN2 i n step 5).
323 CHAPTER 15 DMAC This chapter pr ovides an o ver vie w of the DMA C and explains the register configuration and functions and the operations of the DMA C. 15.1 Overview of D MAC 15.2 DMAC Para meter Descriptor Point er (DPDP) 15.3 DMAC Control Status Regi ster (DACSR) 15.
324 CHAPTER 15 DMAC 15.1 Ove rview of DMAC The DMA C is a b uilt-in modul e of the M B91F109 that implem ents dire ct memory acce ss (DMA ). ■ DMA C Chara cterist ics • Eight c hannels • Three m.
325 15.1 Ove rview of DMAC ■ DMA C Bloc k D i a gr a m Figure 15 .1-2 is a DM AC block diagram. Figure 15.1-2 DMA C Bloc k Diagram DPDP DACSR SADR DADR DATCR DACK0-2 EOP0-2 3 3 3 3 8 DRE Q 0-2 5 BLK.
326 CHAPTER 15 DMAC 15.2 DMAC Param eter Descriptor Poin ter (DPDP) The DMA C parameter descriptor pointer (DPDP) is an internal register of the DMA C and is used to store the fir st address of the DMA C descriptor tab le in RAM. DPDP bits 6 to 0 are al wa ys 0, and t he first a ddress of th e descriptor that c a n be set is 128 b ytes.
327 15.3 D MAC Control Status R egister (DACSR) 15.3 DMAC Control Status R egister (DACSR) The DMA C contr ol status register (D A CSR) is an inter n al register of the DMA C that specifies control status inf ormat ion on the entire DMAC.
328 CHAPTER 15 DMAC These bit s are initi alized to "0" by res etting. These bit s can be both read and written, b ut can onl y be set to "0". A Read Mo dify W rite in struction always reads "1" fro m each of t hese bits .
329 15.4 DMAC Pin Control Regi ster (DATCR) 15.4 DMAC Pin Contro l Register (DATCR) The DMA C pin control regist er (D A TCR) is an internal register of the DMA C and is used to contr ol the e x ternal transfer request input pins, e xternal transfer request ac knowledgment output pins, and e xternal transfer end output pins.
330 CHAPTER 15 DMAC ■ Bit Functions of DMA C Pin Control Register (D A TCR) [bit 21,20, 13, 1 2, 5, 4] LSn1, LSn0: Transfer request input detect level sele ct Each of these bit s selec ts the dete ction le vel of the corres ponding external transfe r request input pi n DREQn as sho wn in Table 15.
331 15.4 DMAC Pin Control Regi ster (DATCR) [bit 16, 8, 0] EPDEn These bit s speci fies the time when th e tran sfer end output s ignal is to be gener ated from the corresp onding outpu t pin and also specif y whether to enabl e the output function of the corresp onding trans fer end o utput signal pin.
332 CHAPTER 15 DMAC 15.5 Descrip tor Register in RAM This descriptor register has the setup inf ormation for the corr esponding channel in DMA transfer m ode . The descriptor register has a 12-b yte are a for eac h channel t hat is all ocated to the memor y address spec ified by DPDP .
333 15.5 D escriptor Re gister in RAM [bits 5, 4] DCS1, DCS0: Transfer destination address update mode These bit s speci fy the mode in whi ch the trans fer sour ce or de stination address is upda ted each tim e DMA t ransfer is p erforme d. Table 15.
334 CHAPTER 15 DMAC [bits 1, 0] MOD1, MOD0: Tr ansfer mode Thes e bits spec ify the tr ans f er mode. The conti nuous trans fer mode can be us ed for chann els 0 to 2 only. ■ Secon d W or d of a De scripto r The seco nd word c ontains th e transfe r sour ce addre ss.
335 15.6 DMAC Tra nsfer Modes 15.6 DMAC Transfer Mode s The DMA C suppor ts the follo wing three transfer modes: This section explains the operation in these modes. • Single/block t ransfer mode • Continuous transfer mode • B urst transfer mode ■ Single/Block T ransfer Mode 1.
336 CHAPTER 15 DMAC ■ Continuous T r ansfer Mode 1. The initi alizati on routin e sets the descr iptor. 2. The program initialize s the DM A transfer request sou rce. Set the ex ternal tran sfer re quest input pi n to the H-lev el or L-l evel dete ction mode.
337 15.6 DMAC Tra nsfer Modes ■ Burst T ransfer Mode 1. The initiali zation rou tine sets the desc riptor. 2. The program initial izes the DMA transfer request source. To u se the in ternal pe ripheral circuit as the trans fer reques t source, en able interrupt requ ests and disable i nterrupts in the ICR of the i nterrupt control ler.
338 CHAPTER 15 DMAC 15.7 Ou tput of Transfer Requ est Acknowledgm ent and Transfer End signa ls Channels 0, 1, and 2 ha ve a function that out puts transfer request ac knowledgment and transfer end signals fr om the corresponding pins.
339 15.8 Notes on DMAC 15.8 Notes on DMAC This section pro vides notes on using the DMA C. ■ Interc hanne l Priority Order Once the DMAC starts wi th a DMA tra nsfer reque st from on e channel, DMA transfer r equests from ano ther channel are su spended u ntil the c urrent trans fer ends.
340 CHAPTER 15 DMAC ❍ PDRR regist er The suppressio n function for a DMA tra nsfer operation specified via the HRCL register i s valid only when an inte rrupt requ est wit h highe r priorit y is act ive.
341 15.8 Notes on DMAC itse lf contin ues. ■ External T r ansfer fr om Internal Memory In block tr ansfer m ode, DMA tran sfer is performed twice for a single DRE Q. In co ntinuous transfer m ode, DMA tr ansfer is perfor med even if DREQ is cancele d.
342 CHAPTER 15 DMAC 15.9 DMAC T iming Charts This section pro vides the fol lowing DMA C timing char ts: • Timing charts for t he descriptor access bloc k • Timing charts for t he data transfer b .
343 15.9 D MAC Timing Charts 15.9.1 Tim ing Char ts of the Descrip tor Access Block This secti on sho ws timing c har ts of th e descr iptor acces s bloc k.
344 CHAPTER 15 DMAC ❍ Required pin input mode: edge , descriptor address: external ❍ Required pin input mode: edge , descr ipt or address: i ntern al <Note> The sect ion from when a DRE Qn is generated to when th e DMAC ope ration s tarts sho ws the case w her e the DMAC op eration star ts firs t.
345 15.9 D MAC Timing Charts 15.9.2 Tim ing Char ts of Data T r ansfer Bloc k This secti on sho ws timing c har ts of th e data t ransfer bl ock. ■ Data T ra nsfer Block f or 16-Bit or 8-Bit Data .
346 CHAPTER 15 DMAC ❍ T ransfe r sour ce area : inter nal RAM, t ra nsf er dest ination area : ext ern al (A) CLK DREQn Addr pin Data pin RDXD WRnX DACK EOP #2 #2 W D D DDD D D W W D W.
347 15.9 D MAC Timing Charts 15.9.3 T ransfer Stop Timing Cha r ts in Continuous T ransfer Mode This section sho ws transfer stop timing char ts in continuous transf er mode .
348 CHAPTER 15 DMAC ■ T ransfer Stop in Continuous T r ansfer Mode (When Both Addresses are Changed) for 16-Bit or 8-Bit Data ❍ T ransfer source area: external, tra nsfer destination area: externa.
349 15.9 D MAC Timing Charts 15.9.4 T ransfer T erminatio n Timing Char ts This section sho ws transfer termi nation timing charts. ■ T ransfer T ermination (When Either Address is Unchanged.
350 CHAPTER 15 DMAC ■ T ransfer T ermination (When Bo th Addresses are Chang ed.) ❍ Bus width: 16 bits, data length: 8/16 bits ❍ Bus width: 16 bits, data length: 32 bits CLK Addr pin Data pin RD.
351 CHAPTER 16 FLASH MEMORY This chapter explains the flash memory functions and operations. The chapter pro vides information on usi n g the flash memory from the FR-CPU . For information on using the flash memory fr om the ROM writer , refer to the user’ s guide f or the R OM writer .
352 CHAPTER 16 FLASH MEMORY 16.1 Ou tline of Flash Memory This de vice type has an internal fl ash memory of 254 k ilobytes (2 megabits) th at enables to perf orm the f ollo wing functions with a sing.
353 16.1 O utline of Flash Memory ■ Execution Status of the A utomatic Algorithm When the au tomati c algo rithm is star ted in CPU pr ogrammi ng mode , its op erati on stat us can be checke d with the inte rnal Busy or Rea dy signal ( RDY/BUSYX ).
354 CHAPTER 16 FLASH MEMORY 16.2 Block Diagram of Flash Memo ry Figure 16.2-1 is a bloc k diagram of the flash memory . ■ Block Diagram of Flash Memory Figure 16.
355 16.3 Flash Me mory Status Register ( FSTR) 16.3 Flash Memory Status Reg ister (FSTR) The flash memory status register (FSTR) indicates the operation status of the flash memory . This register also contr ols interrupts to the CPU and writing to the flash memory .
356 CHAPTER 16 FLASH MEMORY When this bit is "1", writing data and commands to the flash memory bec omes valid and the automatic algorithm can be sta rted. Howev er, data from flash mem ory is re ad in 16-bit access mod e, during whic h flash memory cannot be used as progra m memory becau se 32- bit acc ess is in hibite d.
357 16.4 Sector Configuration of Flash Memory 16.4 Sector Configur ation of Flash Mem ory Figure 16.4-1 s how s the sector configurat ion of the flash memory .
358 CHAPTER 16 FLASH MEMORY T able 16.4-1 Sector Addresse s Sector address Address range Corresponding bits Sector capacity SA0 000C08 00-1h to 000DFFFC-Dh (MSB side 16 bits) bit 31 to 16 63 Kbyte SA1.
359 16.5 Fl ash Memory Access Modes 16.5 Flash Memory Access Modes The foll owing two types of access mode are a vailab le for t he FR-CPU: • ROM mode: One w ord (32 bits) can be read in one cyc le , b ut not written.
360 CHAPTER 16 FLASH MEMORY For detai ls on the auto matic al gorithm, see Sec tion 16.6, " Starting th e Automati c Algorit hm." ❍ Restrictions Address assignm ent and end ians in t his mode differ from those for writing with the ROM w riter.
361 16.6 S tarting the Aut omatic Algorithm 16.6 Starting the Automatic Algo rithm For writing data to or erasing data fr om flash memor y , star t the automatic algori t hm stored in flas h memor y . ■ Comm and Operat ion At the star t of the automati c algorithm, one to six hal f-words (16 bits ) are written.
362 CHAPTER 16 FLASH MEMORY ❍ Progr am (Write) In CPU programm ing mode, data is basica lly writte n in hal f-word uni ts. The wr ite ope ration is performed i n four cy cles of bus operation. The comma nd sequence h as two "unl ock" cyc les, which are fol lowed by a Writ e Setup c omman d and a wr ite dat a cycle .
363 16.6 Starting the Automatic Algorithm During th e time-out period, an y command othe r than Sector Eras e and Temporari ly Stop Erase is reset at r ead time, an d the precedi ng comman d sequenc e is ignored .
364 CHAPTER 16 FLASH MEMORY 16.7 Execution Status of the Automatic A lgorithm This flash memory has tw o har dware components for perf orming a Write or Erase sequence in the automatic algorithm. These components indicate the internal operation status of flash memory and the completion of operations to external components.
365 16.7 Execution Status of the Automatic Algorithm Table 16.7- 1 lists th e possi ble status es of the hardware s equence fl ag. [bit 7] DPOLL (Dat a polling) ❍ A utomatic wri te operation status .
366 CHAPTER 16 FLASH MEMORY ❍ T empora r y sector erase stop status When a r ead operation is performed during tempor ary sector erase stop, flas h memory outpu ts "1" if t he address indicated b y the addre ss signal is i ncluded in t he sector in erase state .
367 16.7 Execution Status of the Automatic Algorithm Suppose that the data polling and togg le bit fun ctions indi cate that th e erase alg orithm i s running .
368 CHAPTER 16 FLASH MEMORY.
369 APPENDI X The appendices pr ovide more details and pr ogramming references concerning the I/O maps, interrupt vectors, pin statuses in CPU states, precautions on using the little endian area, and instructions. A I/O Ma ps B Interrupt Vectors C. Pin S tatus for Each C PU Stat us D.
370 APPENDIX A I/O Maps APPENDIX A I/O Maps The ad dresses li sted from T able A.1 to T able A.6 are assigned t o the re gisters of the functions for peripherals that are b uilt -in in the MB91F109.
371 APPENDIX A I/ O Maps ■ I-O Ma ps T able A-1 I/O Map (1/6) Address Register Internal resource +0 +1 +2 +3 000000 H P DR3 [R/W] XXXXXXX X P DR2 [R/W] XXXXXXX X - - Port data re gister 000004 H P D.
372 APPENDIX A I/O Maps 000054 H -- R e s e r v e d 000058 H -- T able A-1 I/O Map (1/6) Address Register Internal resource +0 +1 +2 +3 T able A-2 I/O Map (2/6) Address Register Internal resource +0 +.
373 APPENDIX A I/ O Maps 00009C H -- R e s e r v e d 0000A0 H - 0000A4 H - 0000A8 H - 0000AC H - 0000B0 H - 0000B4 H - 0000B8 H - T able A-2 I/O Map (2/6) Address Register Internal resource +0 +1 +2 +.
374 APPENDIX A I/O Maps 0000DC H GCN1 [R/W] 00110010 00010 000 - G CN2 [R/W] 0000000 0 PWM 0000E0 H P TMR [R] 11111111 11111 111 PCSR [W] XXXXXXX X XXXXXXXX 0000E4 H P DUT [W ] XXXXXX XX XXXXXXXX P CN.
375 APPENDIX A I/ O Maps T able A-4 I/O Map (4/6) Address Register Internal resource +0 +1 +2 +3 000254 H - R eserved 000258 H - 00025C H - 000260 H - 000264 H - 000268 H - 00026C H - 000270 H - 00027.
376 APPENDIX A I/O Maps T able A-5 I/O Map (5/6) Address Register Internal resource +0 +1 +2 +3 000400 H ICR0 0 [R/W] ---11111 ICR01 [R/W] ---1111 1 ICR02 [R/W ] ---111 11 ICR03 [R/W] ---11111 Inte rr.
377 APPENDIX A I/ O Maps 000600 H DD R3 [W] 00000000 DDR2 [W] 0000000 0 - - Data directi on regi ste r 000604 H DD R7 [W] -------0 DDR6 [W] 0000000 0 DDR5 [W] 00000000 DDR4 [W] 00000000 000608 H DDRB .
378 APPENDIX A I/O Maps <Note> Do not exe cute RMW instructi ons for reg isters for wh ich a wr ite-only bi t is se t. Data in ar eas mar ked as "Res erved" or " -" is und efined.
379 APPENDIX B Inter rupt Vectors APPENDIX B In terrupt V ectors T able B. 1 and T able B. 2 list the inte rrupt vector s. The interrupt vector tables l i st causes for MB91F109 interrupts together with interrupt vector or interrupt contr ol register assignments.
380 APPENDIX B Interrupt Vectors UART 2 rece ption com pletion 22 16 ICR06 3A4 H 00 0FFFA4 H UART 0 se nd completi on 23 17 ICR07 3A0 H 000FFFA0 H UART 1 se nd completi on 24 18 ICR08 39C H 00 0FFF9C .
381 APPENDIX B Inter rupt Vectors Reserved for the syste m 47 2F ICR3 1 340 H 000FFF40 H Reserved for the s ystem 4 8 30 - 33C H 000 FFF3C H Reserved for the s ystem 4 9 31 - 33 8 H 000FFF38 H Reserve.
382 APPENDIX B Interrupt Vectors Reference: The area 1 kilobyte after the a ddress ind icated by th e TBR is a vector address fo r EIT. Each vec tor is 4 bytes in siz e.
383 APPENDIX C Pin Status for Each CPU Status APPENDIX C Pin Status for Each CPU Status T able C. 1 explai ns the te rms used in the pin s tatus l ist. T ab le C-2 to T abl e C-5 l ist the pin status for eac h CPU stat us. Note that th e pin status at reset differ s between the external bus mode and single chip mode .
384 APPENDIX C Pin Status for Each CPU Status ■ Pin Statu s f or Eac h CPU Status T able C-2 Pin Status for 16-bit External Bus Length and 2CA1WR Mode Pin name Function During sleep During stop Bus .
385 APPENDIX C Pin Status for Each CPU Status PA6 CLK P: Previous status re tained F: CLK outpu t P, F: Previ ous stat us ret ained Output Hi-Z/ Input fi xed to 0 CLK Output CLK Output PB0 RAS0 P: Previous status re tained F: Previou s value ret ained Executed when DRAM pin i s set.
386 APPENDIX C Pin Status for Each CPU Status PF4 SO1, TRG3 Previou s status retained Pr evious statu s retained O utput H i-Z/ Input fi xed to 0 Previous sta t us retained O utput Hi-Z/ Input allowed.
387 APPENDIX C Pin Status for Each CPU Status T able C-3 Pin Status for 16-bit External Bus Length and 2CA1WR Mode Pin name Function During sleep During stop Bus release (BGRNT) Reset time HIZX=0 HIZX.
388 APPENDIX C Pin Status for Each CPU Status PA6 CLK P: Previous status ret ained F: CLK outpu t P, F: Previ ous status re tained Output H i-Z/ Input fi xed to 0 CL K Output CLK Output PB0 RAS0 P: Previous status ret ained F: Prev ious value reta ined Executed w hen DRAM pin is set.
389 APPENDIX C Pin Status for Each CPU Status PF4 SO1, TRG3 Previou s status retained Pre vious status retained O utput H i-Z/ Input fi xed to 0 Pre vious s tatu s retained Outp ut Hi-Z/ Input allowed.
390 APPENDIX C Pin Status for Each CPU Status T able C-4 Pin St atus in 8-bit External Bus Mode Pin name Function During sleep During stop Bus release (BGRNT) Reset time HIZX=0 HIZX=1 P20 to P27 Port .
391 APPENDIX C Pin Status for Each CPU Status PA6 CLK P: Previous status re tained F: CLK outpu t P, F: Previ ous stat us ret ained Output Hi-Z/ Input fi xed to 0 CLK Output CLK Output PB0 RAS0 P: Pre.
392 APPENDIX C Pin Status for Each CPU Status PF2 SC0, OCPA3 Previou s sta t us retained Pr evious statu s retained O utput H i-Z/ Input fi xed to 0 Previous sta t us retained O utput Hi-Z/ Input allo.
393 APPENDIX C Pin Status for Each CPU Status T able C-5 Pin Status in Single Chip Mode Pin name Function During sleep During stop — Reset time HIZX=0 HIZX=1 P20 to P27 Port Previous status retained.
394 APPENDIX C Pin Status for Each CPU Status P: when a general- purpose p ort is spec ified, F: when the sp ecified f unction is selected PB5 DREQ2 Previous status retained O utput Hi-Z/ All pins Inp.
395 APPENDIX D Notes on Using Little Endian Areas APPENDIX D No tes on Using Little Endian Areas This section contains notes on using little endian areas f or eac h item belo w . D.1 C Compiler (fcc91 1) D.2 Assembler (fasm 911) D.3 Lin ker (flnk911) D.
396 APPENDIX D Notes on Using Little Endian Areas D.1 C Compiler (fcc 911) When the operations described below are perf ormed f or little endian areas from progra ms in C, the result s of the respec tive operations ma y be rende red uncertain.
397 APPENDIX D Notes on Using Little Endian Areas #define STRMOVE(DEST,SRC) DE ST.c=SRC.c;DEST.i=SR C.i; void ma in(voi d) { STRMOV E(little_st,normal _st); } Moreover , as the memb er allocati on for a stru cture is di fferent for ea ch com piler, it ma y differ from that of another compiler .
398 APPENDIX D Notes on Using Little Endian Areas Do not all ocate dou ble and lo ng double type var iables to l ittle endi an areas. [Example of incorrect processing] Transfer of double type data double b ig = 1.
399 APPENDIX D Notes on Using Little Endian Areas D.2 Assembler (fsm9 11) The f ollow ing two items require caution when using little endian areas during programming in FR-series Assemb ler: • Sections • D ata Acce ss ■ Sectio ns Little endi an areas are al located prim arily for data exchange data with little endian type CPU s.
400 APPENDIX D Notes on Using Little Endian Areas /* 32-bit d ata is ac cessed with a ST ( or LD) inst ruction.*/ ST r0, @r1 /* 16-bit d ata is ac cessed with a STH ( or LDH) ins truction. * / STH r2, @r3 /* 8-bit da ta is accessed w ith a STB (or L DB) instruct ion.
401 APPENDIX D Notes on Using Little Endian Areas D.3 Linker (flnk911) The f ollow ing two items require caution with respect to link-time section allocation during program design when em p lo y ing little endian areas.
402 APPENDIX D Notes on Using Little Endian Areas D.4 Debuggers (sim911, em l911, and mon9 11) This section pro vides notes on the simulator deb u g ger an d em ulator or monitor debug g er . ■ Sim ulator D eb ugger There is no memor y area spe cificat ion comm and ind icating little en dian area s.
403 APPENDIX E Instructions APPENDIX E In structions This section lis ts the instru ctions f or the FR-series. Bef ore the instructions are lis ted, the follo wing items are explained: • How to r ea.
404 APPEND IX E I nstruc tions 6) Indicates fl ag change s 7) Indicates th e operation f or the ins truction Flag change Changes Does not change Cleared Set C .
405 APPENDIX E Instructions ■ Addressing Mode Codes T able E-1 Explanation of Addressing Mode Codes Code Meaning Ri Register using dir ect addres sing (R0 toR15, AC, FP , SP) Rj Register using dir e.
406 APPEND IX E I nstruc tions @(R13, Rj ) Register usin g relative and indir ect addres sing (Rj: R0 to R15, AC, FP, a nd SP) @(R14 ,d isp10) Register us ing rel ative and indirect a ddressin g (disp.
407 APPENDIX E Instructions ■ Instruction Formats T able E-2 Instruction Formats Type Instruction format A B C *C’ D E MSB LSB 16bit OP Rj Ri 84 4 OP i8/o8 Ri 484 OP u4/m4 Ri 84 4 ADD ,ADDN,CMP ,L.
408 APPEND IX E I nstruc tions F T able E-2 Instruction Formats OP rel11 51 1.
409 APPENDIX E Instructions E.1 FR-Series Instructions This section describes the FR-series instructions in the f ollowing or der: ■ FR-Series I nstructions Table E.1-1 Addit ion and Su btraction I nstructi ons Table E.1-2 Compare O peratio n Instructi ons Table E.
410 APPEND IX E I nstruc tions ■ Addition and Subtraction Instructions ■ Comp are Oper ation Inst ructio ns T able E.1-1 Addition and Subtra ction Instructions Mnemonic Type OP Cycle NZVC Operatio.
411 APPENDIX E Instructions ■ Logical Operation Instructions ■ Bit Operation Instructions T able E.1-3 Logical Operation Instructions Mnemonic Type OP Cycle NZVC Operation Remark s AND Rj , Ri AND.
412 APPEND IX E I nstruc tions ■ Multiplication and Divis ion Instructions ■ Shift Instruct ions *3 The assem bler crea tes BEOR L if the bit i s ON in u 8&0x0F an d BEORH if th e bit is ON in u8&0x F0. Both BEO RL and BE ORH may b e created.
413 APPENDIX E Instructions ■ Immediate V alue S etting or 16/32-Bit Imme diate V alue T ransfer Instruction ■ Memory Load Instructions *: Spec ial register Rs : TBR, RP, USP, S SP, MDH, M DL (Not.
414 APPEND IX E I nstruc tions ■ Memory Store Instructions *: Spec ial register Rs : TBR, RP, USP, S SP, MDH, M DL (Notes) The asse mbler calculat es and sets values in th e o8 and o4 fiel ds of hardw are specificati ons as follow s: Disp10/4 --> o8, di sp9/2 --> o8, disp 8 --> o8: D isp10, disp 9, and dis p8 are sig ned.
415 APPENDIX E Instructions ■ Standard Branch ( Without Delay) Instructions (Notes) • The num ber of cyc les item "2 /1" means 2 cycles for branc h and 1 for no nbranch .
416 APPEND IX E I nstruc tions ■ Delayed-Branch Instructions (Notes) • The assemb ler calc ulates and sets valu es in the rel1 1 and rel8 fie lds of the har dware specif ication as follows: (labe l12-PC-2)/2 -> rel11, (label9 -PC-2)/2 -> r el8: Labe l12 and la bel9 are signed.
417 APPENDIX E Instructions ■ Other Instructions T able E.1-13 Other Instruct ions Mnemonic Type OP CYCLE N ZVC Operation Remarks NOP E 9F-A 1 ---- Remains unchanged.
418 APPEND IX E I nstruc tions (Notes) • LDM0 (regl ist) and LD M1 (reglist) have a*(n- 1) +b+1 exe cution c ycles when th e specified number of register s is n. • STM0 (reglist) a nd STM1 ( reglist) ha ve a* n+1 execut ion cycle s when th e specifie d numb er of regist ers is n.
419 APPENDIX E Instructions ■ 20-Bit Del a yed-Branch Macro Instructions 2) When label 20-PC-2 is outsid e of the ra nge in 1) and include s an e xternal refer ence symbo l, an ins t ruc tion is cr eated as f ollows: Bxc c false xcc is the excl usion cond ition of c c.
420 APPEND IX E I nstruc tions ■ 32-Bit Sta ndar d Branch Macro Instructions 2) When label 20-PC-2 i s outsid e of the range in 1) and include s an exte rnal refer ence symbo l, an instr uction is cr eated as f o llo ws: Bxc c false xcc : Counter conditio n of cc LDI:20 # label20,R i JMP:D @Ri false: T able E.
421 APPENDIX E Instructions ■ 32-Bit Del a yed-Branch Macro Instructions 2) When label 32-PC-2 is outsid e of the ra nge in 1) and include s an e xternal refer ence symbo l, an ins t ruc tion is cr eated as f ollows: Bxc c false xcc i s the exc lusion co ndition o f cc.
422 APPEND IX E I nstruc tions ■ Direct Addressing Instructions *: Plac e an NOP afte r the DMO V instruc tion that s pecifies R 13+ as th e transfe r source.
423 APPENDIX E Instructions ■ Coprocessor Control Instructions Notes: • {CRi|CRj}:= CR0|CR1|CR2|CR3|CR4|CR5|C R6|CR7|CR8|CR9|CR10|CR11|CR12|CR1 3|CR14|CR15 u4:= C hannel specifi cation u8:= C ommand specifi cation • As this devic e type does n ot have c oprocess ors, these i nstructio ns canno t be used.
424 APPEND IX E I nstruc tions.
425 INDEX INDEX The index f ollows on the next page . This is listed i n alphabetic or der ..
426 INDEX Index Numerics 0-detecti on ................ ................... ................... ..... 295 16/31-b it immedi ate value tr ansfer or immediat e value se tting .......... ................... ............. ..... 413 16/8-bit d ata, data transfe r block for .
427 INDEX bus co ntrol acquisiti on . .................... ................... . 193 bus co ntrol release . ................... ............. .............. 193 bus co nverter, 32 bits - 16 bits .. ............. ................ 32 bus co nverter, Harvard-Princ eton .
428 INDEX descriptor, fi rst word of .......... ............. .................. 3 32 descriptor, s econd word of ........... ................... ..... 334 descriptor, th ird word of ................ ................... ..... 334 detection data registe r 0 (BSD0) .
429 INDEX external trigger or internal tim er to start A /D converter , using ......................... ................... .............. 280 external wait cycle ti ming chart .............. .............. 172 F FBGA-112, ou tside di mension .. .....
430 INDEX interrup t flag set timing for d ata rece ption in mode 1 .................. ............. ................... ..... 261 interrup t flag set timing for d ata rece ption in mode 2 .................. ............. ................... ..... 261 interrup t flag set tim ing for data tra nmission in mode 0, 1 or 2 .
431 INDEX power-on, in put of source o scillatio n at ............... ... 27 power-on, pi n condition at ... ................... ................ 27 PPDR regi ster ........ ............. ................... .............. 3 40 priority che ck .... ...
432 INDEX standby mode (sto p or sleep s tate), returning fro m ........ ................... ............. ..... 234 standby m ode state t ransition ............ .................... 98 standby m ode, type o f operation in ........... ............. 90 starting multiple PWM time r chann el using 16- bit reload time r .
433 INDEX W wait cycle .. ....... ...... ...... ....... ...... ....... ...... ....... ...... . 159 watchdo g controller blo ck diagram .. ................... ... 99 watchdo g timer res et delay re gister (W PR), bit function of .......................
434 INDEX.
CM7 1 - 1 01 0 6-1E FUJITSU SEMICONDUCTOR • CONTROL LER MANUALl FR30 32- B it M icroc ontrol ler MB91F109 Hardwar e Ma nual February 2000 the firs t e d it i on P u b l i s h e d FUJITSU LIMITE D Electronic Devices Edited Tec h n ica l Com m unicati on D e pt.
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FUJITSU SEMICONDUCTOR FR30 32-Bit Microcontroller M B91F109 Hardware Manual.
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