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AMD Geode™ SC1200/SC1201 Processor Data Book AMD Geode™ SC1200/SC1201 Processor Data Book Marc h 2006 Publicat ion ID: 32579B.
2 AMD Geode™ SC1200/SC1201 Processor Data Book © 2006 Advanced Micr o Devices, Inc. All rights reser ved. The contents of this docu ment are pr ovid ed in connection with Adv anced Mi cro Devices , Inc.
AMD Geode™ SC1200/SC1201 Processor Data Book 3 Contents 32579B Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . .
4 AMD Geode™ SC1200/SC1201 Processor Data Book Contents 32579B 6.0 Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . .
AMD Geode™ SC1200/SC1201 Processor Data Book 5 List of Figures 32579B List of Figures Figure 1-1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3-1. Signal Groups .
6 AMD Geode™ SC1200/SC1201 Processor Data Book List of Figures 32579B Figure 7-6. Capture Video Mode Weave Example Using Two Video Frame Bu ffers . . . . . . . . . . . . . . . 319 Figure 7-7. Video Block Diagr am . . . . . . . . . . . . . . . . . . .
AMD Geode™ SC1200/SC1201 Processor Data Book 7 List of Figures 32579B Figure 9-45. Enhanced Para llel Port Timing Diagr am . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 Figure 9-46. ECP Forward Mode Timing Diagram .
8 AMD Geode™ SC1200/SC1201 Processor Data Book List of Figures 32579B.
AMD Geode™ SC1200/SC1201 Processor Data Book 9 List of T ables 32579B List of T ab l es Table 2-1. SC1200/SC1201 Processor Memo ry Controller Reg ister Summary . . . . . . . . . . . . . . . . . . . 18 Table 2-2. SC1200/SC1201 Processor Memo ry Controller Reg isters .
10 AMD Geode™ SC1200/SC1201 Processor Data Book List of T ables 32579B Table 5-29. Banks 0 and 1 - Common Cont rol and Status Re gisters . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 5-30. Bank 1 - CEIR Wakeup Configur ation and Control R egisters .
AMD Geode™ SC1200/SC1201 Processor Data Book 11 List of T ables 32579B Table 6-22. F3: PCI Heade r Registers for Au dio Support Summa ry . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 Table 6-23. F3BAR0: Audio Support Registers Summary .
12 AMD Geode™ SC1200/SC1201 Processor Data Book List of T ables 32579B Table 9-17. TV DAC (4 Outputs: CVBS, SVY/TVR, SVC/TVB, CVBS/TVG) . . . . . . . . . . . . . . . . . . . . . 384 Table 9-18. ACCESS.bus In put Timing Paramete rs . . . . . . . . . .
AMD Geode™ SC1200/SC1201 Processor Data Book 13 1 Overview 32579B 1.0 Ov er vie w 1.1 General Description The AMD Geode™ SC1200 and SC1 201 processors are members of the AMD Geode processor family of fully inte- grated x86 system chips .
14 AMD Geode™ SC1200/SC1201 Processor Data Book Overview 32579B 1.2 Features General Features ■ 32-Bit x86 processor , up to 266 MHz, with MMX instruc- tion set suppor t ■ Memory controller with.
AMD Geode™ SC1200/SC1201 Processor Data Book 15 Overview 32579B — VBI Generation Suppor t: – Wide Screen Signaling (WSS) – Closed caption – Extended Data Se rvices (EDS) – Cop y Generation Management System (CGMS) — F our-field NTSC or eight-field P AL generation — Macrovision cop y protection v ersion 7.
16 AMD Geode™ SC1200/SC1201 Processor Data Book Overview 32579B.
AMD Geode™ SC1200/SC1201 Processor Data Book 17 2 Architecture Overview 32579B 2.0 Architecture Ov er vie w As illustrated in Figure 1-1 on pa ge 13, the SC1200/ SC1201 processor co ntains the f oll.
18 AMD Geode™ SC1200/SC1201 Processor Data Book Architecture Overview 32579B T able 2-1. SC1200/SC1201 Pro cessor Memory Contr oller Regi ster Summary GX_B ASE+ Memory Offset Width (Bits) T ype Name/Function Reset V alue 8400h-8403h 32 R/W MC_MEM_CNTRL1.
AMD Geode™ SC1200/SC1201 Processor Data Book 19 Architecture Overview 32579B 4 RFSHTST (T est Refresh). This bit, when set high, generates a refre sh r equest.
20 AMD Geode™ SC1200/SC1201 Processor Data Book Architecture Overview 32579B GX_BASE+8408h-840Bh MC_BANK_CFG (R/W) Reset V alue: 41104110h 31:16 RSVD (Reserved). Write as 0070h 15 RSVD (Reserved). Write as 0. 14 SODIMM_MOD_BNK (SODIMM Module Banks - Banks 0 and 1).
AMD Geode™ SC1200/SC1201 Processor Data Book 21 Architecture Overview 32579B 11 RSVD (Reserved). Write as 0. 10:8 RRD (ACT(0) to A CT(1) Command Period, tRRD). Minimum number of SDRAM cloc ks between ACT and A CT command to two different component banks within the same module bank .
22 AMD Geode™ SC1200/SC1201 Processor Data Book Architecture Overview 32579B 2.1.2 Fast-PCI Bus The GX1 module co mmunicates with the Core Logic mod- ule via a F ast-PCI bus that c an wo rk at up to 6 6 MHz. Th e F ast-PCI bu s is inter nal f or the SC1200/SC1201 processor and is connected to the Ge neral Configuration Bloc k (see Section 4.
AMD Geode™ SC1200/SC1201 Processor Data Book 23 Architecture Overview 32579B • USB: See Section 6. 2.4 "Univ ersal Serial Bus" on page 147. The USB function uses signal AD29 as th e IDSEL f or PCI configuration. • LPC: See Section 3.4.
24 AMD Geode™ SC1200/SC1201 Processor Data Book Architecture Overview 32579B.
AMD Geode™ SC1200/SC1201 Processor Data Book 25 3 Signal Definitions 32579B 3.0 Signal Definitions This section defines the signal s and describes the externa l interf ace of the SC1200/SC12 01 processor . Figure 2-1 shows the signals organized by their functional groups .
26 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B Figure 3-1. Signal Groups (Continued) The remaining subsectio ns of this chapter describe: • Section 3.
AMD Geode™ SC1200/SC1201 Processor Data Book 27 Signal Definitions 32579B 3.1 Ball Assignments The SC1200/SC1201 processor is highly configurable as illustrated in Figure 3-1 on pa ge 25. Strap options and reg- ister programming are used to set v arious modes of opera- tion and specific signals on specific balls.
28 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B Figure 3-2. BGU4 81 Ball Assignment Diagr am S S S S S S S S S 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 .
AMD Geode™ SC1200/SC1201 Processor Data Book 29 Signal Definitions 32579B T able 3-2. BGU481 Ball Assignme nt - Sort ed b y Ball Number Ball No. Signal Name I/O (PU/PD) Buffer 1 Ty p e Pow e r Rail .
30 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B A28 6 DPOS_POR T1 I/O IN USB , O USB AV C- CUSB --- A29 6 DNEG_PORT1 I/O IN USB , O USB AV C- CUSB --- A30 V IO PWR --- ---.
AMD Geode™ SC1200/SC1201 Processor Data Book 31 Signal Definitions 32579B C1 AD26 I/O IN PCI , O PCI V IO Cycle Multiplex ed D2 I/O IN PCI , O PCI C2 AD24 I/O IN PCI , O PCI V IO Cycle Multiplex ed .
32 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B C30 GPIO7 I/ O (PU 22.5 ) IN TS , O 1/4 V IO PMR[17] = 0 and PMR[8] = 0 RTS 2 # O (PU 22.5 ) O 1/4 PMR[17] = 1 and PMR[8] = 0 IDE_DA CK1# O (PU 22.5 ) O 1/4 PMR[17] = 0 and PMR[8] = 1 SDTEST0 O (PU 22.
AMD Geode™ SC1200/SC1201 Processor Data Book 33 Signal Definitions 32579B D22 6, 2 AFD#/DSTRB# O O 14/14 V IO PMR[23] 3 = 0 and (PMR[27] = 0 and FPCI_MON = 0) TFTD2 O O 1/4 PMR[23] 3 = 1 and PMR[15].
34 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B J2 C/BE1# I/O (PU 22.5 ) IN PCI , O PCI V IO Cycle Multiplex ed D9 I/O (PU 22.5 ) IN PCI , O PCI J3 AD15 I/O IN PCI , O PCI V IO Cycle Multiplex ed A15 O O PCI J4 P A R I/O (PU 22.
AMD Geode™ SC1200/SC1201 Processor Data Book 35 Signal Definitions 32579B N15 V SS GND --- --- --- N16 V SS GND --- --- --- N17 V SS GND --- --- --- N18 V CORE PWR --- --- --- N19 V CORE PWR --- --- --- N28 V SS GND --- --- --- N29 GPIO12 I/O (PU 22.
36 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B U30 BIT_CLK I IN T V IO FPCI_MON = 0 F_TRD Y# O O 1/4 FPCI_MON = 1 U31 SD A T A_IN I IN T V IO FPCI_MON = 0 F_GNT0# O O 2/5.
AMD Geode™ SC1200/SC1201 Processor Data Book 37 Signal Definitions 32579B AC1 I DE _ DA T A 1 I /O IN TS1 , TS 1/4 V IO PMR[24] = 0 TFTD16 O O 1/4 PMR[24] = 1 AC2 I DE _ DA T A 2 I /O IN TS1 , TS 1/.
38 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B AJ1 TEST2 O O 2/5 V IO PMR[29] = 1 PLL5B I/O IN T , TS 2/5 PMR[29] = 0 AJ2 X32I I WIRE V BA T --- AJ3 X32O O WI RE V BA T -.
AMD Geode™ SC1200/SC1201 Processor Data Book 39 Signal Definitions 32579B AL24 MA4 O O 2/5 V IO --- AL25 6 MD8 I/O IN T , TS 2/5 V IO --- AL26 6 MD10 I/O IN T , TS 2/5 V IO --- AL27 6 MD9 I/O IN T , TS 2/5 V IO --- AL28 MA12 O O 2/5 V IO --- AL29 6 MD23 I/O IN T , TS 2/5 V IO --- AL30 V IO PWR --- --- --- AL31 V SS GND --- --- --- 1.
40 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B T able 3-3. BGU481 Ball Assignment - Sorted Alphabetical ly b y Signal Name Signal Name Ball No.
AMD Geode™ SC1200/SC1201 Processor Data Book 41 Signal Definitions 32579B F_AD6 A20 F_AD7 A18 F_C/BE0# D21 F_C/BE1# B17 F_C/BE2# D17 F_C/BE3# C17 F_DEVSEL# V31 F_FRAME# A22 F_GNT0# U3 1 F_IRD Y# B20.
42 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B MD23 AL29 MD24 AB28 MD25 AC28 MD26 AC29 MD27 AC30 MD28 AE31 MD29 AD29 MD30 AD30 MD31 AD31 MD32 AJ15 MD33 AJ16 MD34 AH16 MD3.
AMD Geode™ SC1200/SC1201 Processor Data Book 43 Signal Definitions 32579B TVR A24, C23 TVREF C24 TVRSET A25 V BA T AL3 V CCCRT D12 V CORE (T otal of 28) N13, N14, N18, N19, P4, P13, P14, P18, P19, P.
44 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B 3.2 Strap Options Sev eral balls are read at powe r-up that set up the state of the SC1200/SC1201 processor. These balls are typically multiplex e d with other functions that are outputs after the power-up sequence is complete.
AMD Geode™ SC1200/SC1201 Processor Data Book 45 Signal Definitions 32579B 3.3 Multiplexing Configuration The tables that follo w list multiplexing options and their configurations. Cer tain multiple xing options may be chosen per signal; others are av ailable only f or a group of signals .
46 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B GPIO A CCESS.bus N29 GPIO12 PMR[19] = 0 AB2C PMR[19] = 1 M29 GPIO13 AB2D GPIO U ART A G1 GPIO18 PMR[16] = 0 DTR1#/BOUT1 PMR.
AMD Geode™ SC1200/SC1201 Processor Data Book 47 Signal Definitions 32579B T able 3-6. Three-Signal/Group Multiplexing Ball No. Default Alternate1 Alternate2 Signal Configur ation Signal Configuratio.
48 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B T able 3-7. Four-Signal/Gr oup Multiple xing Ball No. Default Alternate1 Alternate2 Alternate3 Signal Configuration Signal .
AMD Geode™ SC1200/SC1201 Processor Data Book 49 Signal Definitions 32579B 3.4 Signal Descriptions Information in the tables that f ollow ma y ha ve duplicate inf or m ation in multiple tab les. Multiple references all contain identi - cal information.
50 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B X32I AJ2 I/O Crystal Conn ections. Connected directly to a 32.768 KHz cr ystal. This clock input is required ev en if the inte r- nal RT C is not being used. Some of the inter nal clocks are derived from this clock.
AMD Geode™ SC1200/SC1201 Processor Data Book 51 Signal Definitions 32579B DQM7 AB31 O Data Mask Control Bits. During memo ry read cycles, these outputs control whether SDRAM output buff ers are driven on the MD bus or not. All DQM signals are asser ted during read cycles.
52 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B VO P D 7 D2 0 O Video Output P or t Data. The data is output from the Video Processor in VESA Video Interface P or t Rev 1.
AMD Geode™ SC1200/SC1201 Processor Data Book 53 Signal Definitions 32579B TFTDCK AA1 O TF T Clock. Cloc k to e xternal CRT D A Cs or TFT . IDE_RST# A10 GPIO17+ IOCS0# TFTDE P2 O TFT Data Enable . Can be used as blank signal to exter- nal CRT D ACs. IDE_CS1# B18 AC K# + VO PC K + FPCICLK FP_VDD_ON AB1 O TFT Power Control.
54 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B 3.4.5 TV Interface Signals Signal Name Ball No. T ype Description Mux CVBS A23, A24, D24 O Composite Vide o. Includes synchronization, luminance and chrominance components of video.
AMD Geode™ SC1200/SC1201 Processor Data Book 55 Signal Definitions 32579B 3.4.6 ACCESS.b us Interface Signals Signal Name Ball No. T ype Description Mux AB1C N31 I/O ACCESS.b us 1 Serial Clock. This is the serial clock f or the interface . Note: If selected as AB1C function but not used, tie AB1C high.
56 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B INT A# D26 I PCI Interrupts. The SC1200/SC1201 processor pro- vides inputs for the optional “le vel-sensitiv e” PCI inter- rupts (also known in industr y terms as PIRQx#).
AMD Geode™ SC1200/SC1201 Processor Data Book 57 Signal Definitions 32579B ST OP# G1 I/O Ta r g e t S t o p . STOP# is asserted to indicate that the cur- rent target is requesti ng that the master stop the curren t transaction. This signal is used with DEVSEL# to indicate retr y , disco nnect, or target abor t.
58 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B PERR# H2 I/O Pa r i t y E r ro r. PERR# is used for repor ting data parity errors during all PCI transactions e xcept a Special Cycle. The PERR# line is driven two PCI clocks after the data in which the error was detected.
AMD Geode™ SC1200/SC1201 Processor Data Book 59 Signal Definitions 32579B 3.4.8 Sub-ISA Interface Signals Signal Name Ball No. T ype Description Mux A[23:0] See T ab le 3-3 on page 40 O Address Line.
60 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B 3.4.9 Low Pin Count (LPC) Bus Interface Sig nals Signal Name Ball No. T ype Description Mux LAD3 L29 I/O LPC Address-Data. Multiplex ed command, address, bidirectional data, an d cycle status.
AMD Geode™ SC1200/SC1201 Processor Data Book 61 Signal Definitions 32579B 3.4.10 IDE Interf ace Signals Signal Name Ball No. T ype Description Mux IDE_RST# AA1 O IDE Reset. This signal resets all de vices attached to the IDE interf ace. TFTDCK IDE_ADDR2 U2 O IDE Address Bits.
62 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B 3.4.11 Universal Serial Bus (USB) Interface Signals Signal Name Ball No. T ype Description Mux PO WER_EN AH1 O Po wer Enable. This signal enables the pow er to a self- powered USB hub .
AMD Geode™ SC1200/SC1201 Processor Data Book 63 Signal Definitions 32579B RI2# AJ8 I Ring Indicato r . When low , indicates to the mod em that a telephone r ing signal has been received by the modem. They are monitored during pow er-off for w akeup e vent detection.
64 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B PD7 A18 I/O Parallel P ort Data . T ransf er data to and from the periph- eral data bus and the appropriate P arallel P or t data regis- ter . These signals hav e a high current drive capability .
AMD Geode™ SC1200/SC1201 Processor Data Book 65 Signal Definitions 32579B 3.4.15 A C 97 Audio Interface Si gnals Signal Name Ball No. T ype Description Mux BIT_CLK U30 I A udio Bit Clock. The serial bi t cloc k from the codec. Note: If selected as BIT_CLK function but not used, tie BIT_CLK low.
66 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B PWRBTN# AH5 I Po wer Button. An input used by the power management logic to monitor e xter nal system e vents , most typically a system on/off button or s witch.
AMD Geode™ SC1200/SC1201 Processor Data Book 67 Signal Definitions 32579B 3.4.17 GPIO Interface Signals Signal Name Ball No. T ype Description Mux GPIO0 D11 I/O GPIO P ort 0. Each signal is configured independ ently as an input or I/O , with or without static pull-up, and with either open-drain or to tem-pole ou tput type .
68 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B 3.4.18 Debug Monitoring Interf ace Signals Signal Name Ball No. T ype Description Mux FPCICLK B18 O Fast-PCI Bus Monitoring Signal s. When enabled, this group of signals provides f or monitorin g of the internal F ast-PCI b us f or debug purpose s .
AMD Geode™ SC1200/SC1201 Processor Data Book 69 Signal Definitions 32579B TDO E30 O JT A G T est Data Output --- TMS F28 I JT A G T est Mode Select. This signal has an inter nal weak pull-up resistor . --- TRST# E29 I JT A G T est Reset. This signa l has an interna l weak pull-up resistor .
70 AMD Geode™ SC1200/SC1201 Processor Data Book Signal Definit ions 32579B 3.4.21 P ower and Gr ound Connectio ns 1 Signal Name Ball No. T ype Description AV SSPLL2 C16 GND Analog PLL2 Gr ound Co nnection. AV SSPLL3 AK3 GND Analog PLL3 Gr ound Conn ection.
AMD Geode™ SC1200/SC1201 Processor Data Book 71 4 General Configuration Block 32579B 4.0 General Configur ation Bloc k The General Configuration bloc k includes registers for: • Pin Multiplexing a.
72 AMD Geode™ SC1200/SC1201 Processor Data Book General Configuration Block 32579B 4.2 Pin Multiplexing, Interrupt Se lection, and Base Address Register s The registers described in T ab le 4-2 are used to deter mine general configuration for the SC1200/SC1201 processor .
AMD Geode™ SC1200/SC1201 Processor Data Book 73 General Configuration Block 32579B 25 A C97CKEN (Enable A C97_CLK Output). This bit e nab les the output drive of AC97_CLK (ball P31). 0: AC97_CLK output is HiZ. 1: AC97_CLK output is enabled. 24 TFTIDE (TF T/IDE).
74 AMD Geode™ SC1200/SC1201 Processor Data Book General Configuration Block 32579B 23 TFTPP (TFT/Parallel P ort). Determines w hether cer tain balls are used for TFT/V OP or PP/A CB1. This bit is set to 1 at power-on if the TFT_PRSNT strap (ball P29) is pulled high.
AMD Geode™ SC1200/SC1201 Processor Data Book 75 General Configuration Block 32579B 22 RSVD (Reserved). Must be set equal to PMR[14] (LPCSEL). The LPC_R O M strap (ball D6) determines the power-on reset (POR) state of PMR[14] and PMR[22]. 21 IOCSEL (Select I/O Commands ) .
76 AMD Geode™ SC1200/SC1201 Processor Data Book General Configuration Block 32579B 12 TRDESEL (Select TRDE#). Selects ball function. Ball # 0: Sub-ISA Signal 1: GPIO Signal Name Add’l Dependencies Name Add’l Dependencies H1 / D11 TRDE# None GPIO0 None 11 EIDE (Enable IDE Outputs).
AMD Geode™ SC1200/SC1201 Processor Data Book 77 General Configuration Block 32579B 19:18 PLL1 and TV Encoder Clock Frequency . PLL1 supplies the clock for the TV Encoder . 00: TV Encoder clock is 27 MHz from crys tal oscillato r . PLL1 is pow ered down.
78 AMD Geode™ SC1200/SC1201 Processor Data Book General Configuration Block 32579B 3 BUS16 (16-Bit Wide Boot Memory). (Read Only) This bit repor ts the status of the BOO T16 strap (ball C8). If the BOO T16 strap is pulled high, at reset 16-bit access to ROM in the S ub-ISA interf ace is enabled.
AMD Geode™ SC1200/SC1201 Processor Data Book 79 General Configuration Block 32579B 4.3 W A TCHDOG The SC1200/SC1201 processor includes a WA TC HDOG function to serve as a f ail-sa fe mechanism in case the sys- tem becomes hung.
80 AMD Geode™ SC1200/SC1201 Processor Data Book General Configuration Block 32579B W A TCHDOG Interrupt The W A TCHDOG interr upt (if configured and enabled) is routed to an IRQ signal.
AMD Geode™ SC1200/SC1201 Processor Data Book 81 General Configuration Block 32579B 4.4 High-Resolution Timer The SC1200/SC1201 processor provides an accurate time value that can be used as a time stamp b y system soft- ware . This time is called the High-Resolutio n Timer .
82 AMD Geode™ SC1200/SC1201 Processor Data Book General Configuration Block 32579B T able 4-4. High-Resolutio n Timer Register s Bit Description Offset 08h-0Bh TIMER V alue Register - TMV ALUE (RO) Reset V alue: xxxxxxxxh This register contains the current value of the High-Resolution Timer .
AMD Geode™ SC1200/SC1201 Processor Data Book 83 General Configuration Block 32579B 4.5 Cloc k Generators and PLLs This section describes the r egisters f or the clocks required by the GX1 module, Core Logic module, and the Video Processor , and how these clocks are generated.
84 AMD Geode™ SC1200/SC1201 Processor Data Book General Configuration Block 32579B 4.5.1 27 MHz Cr ystal Oscilla tor The inter nal oscillator employs an e xter nal crystal co n- nected to the on-chip amplifie r . The on-chip amplifier is accessible on the X27I input and X27O output signals.
AMD Geode™ SC1200/SC1201 Processor Data Book 85 General Configuration Block 32579B 4.5.2 GX1 Module Core Cloc k The core clock is generated by an Analog Delay Loop (ADL) clock generator from the inter nal F ast-PCI clock. The clock can be an y whole number multiple of the input clock between 4 and 10.
86 AMD Geode™ SC1200/SC1201 Processor Data Book General Configuration Block 32579B 4.5.4 SuperI/ O Clocks The SuperI/O module requires a 48 MHz input for F ast infrared (FIR), U AR T , and other functions. This clock is sup- plied by PLL4 using a multiplier value of 576/(108x3) to generate 48 MHz.
AMD Geode™ SC1200/SC1201 Processor Data Book 87 General Configuration Block 32579B 4.5.7 Clock Registe r s The cloc k genera tor and PLL registers are de scribed in T abl e 4-8.
88 AMD Geode™ SC1200/SC1201 Processor Data Book General Configuration Block 32579B Offset 1Eh-1Fh Core Cloc k Frequency Control Regi ster - CCFC (R/W) Reset V alue: Strapped V alue This register controls the configuration of the core clock multiplier and the ref erence clocks .
AMD Geode™ SC1200/SC1201 Processor Data Book 89 5 SuperI/O Module 32579B 5.0 SuperI/O Module The SuperI/O (SIO) module i s a PC98 and ACPI compliant SIO that offers a single-cell solution to the most co mmonly used ISA perip herals.
90 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B 5.1 Features PC98 and A CPI Compliant • PnP Configuration Register str ucture • Flexib le resource allocation for all logic.
AMD Geode™ SC1200/SC1201 Processor Data Book 91 SuperI/O Module 32579B 5.2 Module Ar chitecture The SIO module comprises a collection of generic func- tional blocks .
92 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B 5.3 Configuration St ructure / Access This section descr ibes the st ructure of the config uration register file, and the method of ac cessing the configuration registers.
AMD Geode™ SC1200/SC1201 Processor Data Book 93 SuperI/O Module 32579B Write accesses to unimplemented registers (i.e., accessing the Data register while the I ndex register points to a non- ex isti.
94 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B 5.4 Standard Configur ation Register s As illustrated in Figure 5-4, the Standard Configuration reg- isters are broadly divided.
AMD Geode™ SC1200/SC1201 Processor Data Book 95 SuperI/O Module 32579B T able 5-3 provides the bit definitions f or the Standard Con- figuration registers. • All reser ved bits return 0 o n reads, e xcept where noted otherwise. They must not be m odified as such modifica- tion may cause unpredictable results.
96 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B Index 75h DMA Channel Select 1 (R/W) Indicates selected DMA channel for DMA 1 of the logical de vice (1 - the second DMA channel in case of using more than one D MA channel). 7:3 Reserved.
AMD Geode™ SC1200/SC1201 Processor Data Book 97 SuperI/O Module 32579B 5.4.1 SIO Control and Configuration Register s T able 5-4 lists the SIO Control and Configuration regi sters and T able 5-5 pro vides their bit formats. T able 5-4. SIO Control and C onf iguration Register Map Index T ype Name P ower Rail Reset V alue 20h RO SID .
98 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B 5.4.2 Logical Device Contr ol and Configuration As described in Section 5.3.2 "Banked Logical Device Reg- isters" on page 92, each functio nal b lock is associated with a Logical Device Number (LDN).
AMD Geode™ SC1200/SC1201 Processor Data Book 99 SuperI/O Module 32579B T able 5-7. RTC Configura tion Register s Bit Description Index F0h RAM Lock Register - RLR (R/W) When any non-reser v ed bit in this register is se t to 1, it c an be cleared only by hardw are reset.
100 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B 5.4.2.2 LDN 01h - Sy stem Wakeup Contr ol T able 5-8 lists registers that are relev ant to the configura- tion of System W akeup Control (SWC). These regi sters are descri bed earlier in T able 5-3 "Standard Configuration Reg- isters" on page 95.
AMD Geode™ SC1200/SC1201 Processor Data Book 101 SuperI/O Module 32579B 5.4.2.3 LDN 02h - Infrared Communication P ort or Serial P ort 3 T able 5-9 lists the configurati on registers which affect the Infrared Communication P or t or Ser ial P ort 3 (IRCP/SP3).
102 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B 5.4.2.4 LDN 03h and 08h - Serial P ort s 1 and 2 Serial P or ts 1 and 2 are iden tical, e xcept for their reset v al- ues. Serial Port 1 is designated as LDN 03h and Seri al P or t 2 as LDN 08h.
AMD Geode™ SC1200/SC1201 Processor Data Book 103 SuperI/O Module 32579B 5.4.2.5 LDN 05h and 06h - A CCESS.bus P or ts 1 and 2 A CCESS.b us por ts 1 and 2 (ACB1 and ACB2) are identi- cal. Each ACB is a tw o-wire synchronous ser ial interf ace compatible with the A CCESS.
104 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B 5.4.2.6 LDN 07h - P arallel P ort The P arallel P or t suppor ts all IEEE 1284 standard commu- nication modes: Compatibility (known also as Standard or SPP), Bidirectional (known also as PS/2), FIFO , EPP (known also as Mode 4) and ECP (with an optional Extended ECP mode).
AMD Geode™ SC1200/SC1201 Processor Data Book 105 SuperI/O Module 32579B 5.5 Real-Time Cloc k (RTC) The RTC pro vides timekeeping and calenda r management capabilities. The RTC uses a 32.768 KHz signal as th e basic clock f or timeke eping. It also includes 24 2 b ytes of batter y-back ed RAM f or general-pur pose use.
106 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B External Elements Choose C 1 and C 2 capacitors (see Figure 5-5 on page 105) to match the cr ystal’ s load capacitance. The load capacitance C L “seen” b y cr ystal Y is comprised o f C 1 in series with C 2 and in parallel with the parasitic capacitance of the circuit.
AMD Geode™ SC1200/SC1201 Processor Data Book 107 SuperI/O Module 32579B 5.5.2.4 Timekeeping Data Format Time is kept in BCD or binar y format, as deter mined by bit 2 (DM) of Control Register B (CRB), and in either 12 or 24- hour f or mat, as determined by bit 1 of this register .
108 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B 5.5.2.6 P ower Supply The device is supplied from two supply voltages , as shown in Figure 5-8: • System standby pow er supp.
AMD Geode™ SC1200/SC1201 Processor Data Book 109 SuperI/O Module 32579B 5.5.2.7 System P ower States The system power state ma y be No P o wer , P ower On, P ower Off or P ower F a ilure . T able 5-18 indicates the pow er- source combinations for each state .
110 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B 5.5.2.9 Interrupt Handling The RTC has a single Interr upt Request line which hand les the following three interrupt condi tions: • P eriodic interr upt. • Alar m interrupt.
AMD Geode™ SC1200/SC1201 Processor Data Book 111 SuperI/O Module 32579B 5.5.3 RTC Registers The RTC registers can be acce sse d (see Section 5.4.2.1 "LDN 00h - Real-Time Clock" on page 98) at any time dur- ing nor mal operation mode (i.e.,when V SB is within the rec- ommended operation range).
112 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B Index 03h Minutes Alarm Register - MINA (R /W) Reset T ype: V PP PUR 7:0 Minutes Alarm Data. V alues can be 00 to 59 in BCD f ormat, or 00 to 3B in binar y format. When bits 7 and 6 are both set to 1, unconditional match is selected.
AMD Geode™ SC1200/SC1201 Processor Data Book 113 SuperI/O Module 32579B 2 Data Mod e. This bit is reset at V PP power-up reset only . 0: Enab le BCD f ormat. 1: Enable Binar y f orm at. 1 Hour Mod e. This bit is reset at V PP power-up reset only . 0: Enable 12-hour format.
114 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B T able 5-21. Divider Chain Contr ol / T est Selection DV 2 DV 1 DV 0 Configuration CRA6 CRA 5 CRA4 0 0 X Oscillator Disabled 0 1 0 Normal Operation 01 1 T e s t 10 X 1 1 X Di vider Chain Reset T able 5-22.
AMD Geode™ SC1200/SC1201 Processor Data Book 115 SuperI/O Module 32579B 5.5.3.1 Usage Hints 1) Read bit 7 of CRD at each system pow er-up to vali- date the contents of the R TC registers and the CMOS RAM. When this bit is 0, the contents of these re gis- ters and the CMOS RAM are questionable.
116 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B 5.6 System W akeup Contr ol (SWC) The SWC wak es up the system b y sending a power-up request to the ACPI controller in respon.
AMD Geode™ SC1200/SC1201 Processor Data Book 117 SuperI/O Module 32579B 5.6.2 SWC Regist ers The SWC registers are organized in two banks. The offsets are related to a base address that is deter mined by the SWC Base Address Register in the logical device configu- ration.
118 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B T able 5-2 9. Banks 0 and 1 - Common Control and Status Register s Bit Description Offset 00h W akeup Events Status Regist er - WKSR (R/W1C ) Reset V alue: 00h This register is set to 00h on power-up of V PP or software reset.
AMD Geode™ SC1200/SC1201 Processor Data Book 119 SuperI/O Module 32579B T able 5-30. Bank 1 - CEIR W akeup Configuration and Contr ol Registers Bit Description Bank 1, Offset 03h CEIR W akeup Control Register - IR WCR (R/W) R eset V alue: 00h This register is set to 00h on power-up of V PP or software reset.
120 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B CEIR Wakeup Range 1 Registers These two registers (IR WTR1L and IRWTR1H) define the low and high limits of time range 1 (see T able 5-26 on page 116). The v alu es are represented in units of 0.
AMD Geode™ SC1200/SC1201 Processor Data Book 121 SuperI/O Module 32579B 5.7 A CCESS.bus Interface The SC1200/SC1201 processor has two ACCESS .bus (A CB) controllers. A CB is a two- wire synchronous serial interf ace compatible with the A CCESS.b us physical la yer , Intel's SMBus, and Philips’ I 2 C .
122 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B 5.7.3 Acknowledge (A CK) Cyc le The AC K cycle consists of two signals: the ACK cloc k pulse sent by the master with each byte tr ansferred, and the ACK signal sent by the receiving device (see Figure 5- 15).
AMD Geode™ SC1200/SC1201 Processor Data Book 123 SuperI/O Module 32579B 5.7.4 Acknowledge After Eve ry Byte Rule According to this rule, the master generates an acknowl- edge clock pulse after each byte transf er , and the receiver sends an acknowledge signal after e very byte receiv ed.
124 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B Sending the Address Byte When the device is the active master of the A CCESS.
AMD Geode™ SC1200/SC1201 Processor Data Book 125 SuperI/O Module 32579B Master Error Detection The ACB detects illegal Star t or Stop Conditions (i.e., a Star t or Stop Condition within the data transf er , or the ackno wledge cycle) and a conflict on the data lines o f the A CCESS.
126 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B 5.7.10 A C B Registers Each functional block is associated with a Logical Device Number (LDN) (see Section 5.3 .2 "Bank ed Logical Device Registers" on page 92). A CCESS.
AMD Geode™ SC1200/SC1201 Processor Data Book 127 SuperI/O Module 32579B 2 NMA TCH ( New Ma tch). (R/W1C) Writing 0 to this bit is ignored. If ACBCTL1[2] is set, an interrupt is sent wh en this bit is set. 0: Software writes 1 to this bit. 1: Address byte follo ws a Star t Condition or a repeated star t, causing a match or a global-call match.
128 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B 4 A CK (Acknowledge). This bit is ignored in transmit mode . When the device acts as a receiv er (sla v e or master), this bit holds the stop transmitting instruction that is transmitted dur ing the ne xt acknowledge cycle .
AMD Geode™ SC1200/SC1201 Processor Data Book 129 SuperI/O Module 32579B 5.8 Legacy Functional Blocks This section bri efly describes th e f ollowing bloc ks that pro- vide legacy device functions: • P arallel P ort . (Similar to P arallel P or t in the National Semiconductor PC87338.
130 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B T able 5-35. P arallel P or t Bit Map f or Firs t Level Offset Offset Name Bits 76543210 000h D A T AR Data Bits AFIFO Address.
AMD Geode™ SC1200/SC1201 Processor Data Book 131 SuperI/O Module 32579B 5.8.2 U ART Fun ctionality (SP1 and SP2) Both SP1 and SP2 provide UA RT functionality . The generic SP1 and SP2 suppor t serial data communication with remote peripheral d e vice or modem using a wired interf ace.
132 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B T able 5-38. Bank Select ion Encoding BSR Bits Bank Selected 76543210 0xxxxxxx 0 1 0 xxxxxx 1 1 1 xxxx1 x 1 1 1 xxxxx1 1 11100000 2 11100100 3 T able 5-39. Bank 1 Register Map Offset T ype Name 00h R/W LBGD(L).
AMD Geode™ SC1200/SC1201 Processor Data Book 133 SuperI/O Module 32579B T able 5-42. Bank 0 Bi t Map Register Bits O f f s e t N a m e 76543210 00h RXD RXD[7:0] (Receiver Data Bits) TXD TXD[7:0] (T .
134 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B T able 5-44. Bank 2 Bi t Map Register Bits O f f s e t N a m e 7 654321 0 00h BGD(L) BGD[7:0] (Low Byte) 01h BGD(H) BGD [15:8].
AMD Geode™ SC1200/SC1201 Processor Data Book 135 SuperI/O Module 32579B 5.8.3 IR Communications P ort (IRCP) / Serial P ort 3 (SP3) Funct ionality This section describes the IRCP/SP3 suppor t registers . The IRCP/SP3 functional block pro vides advanced, ve rsa- tile serial communications features with IR capabilities.
136 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B T able 5-47. Bank Select ion Encoding BSR Bits Bank Selected Functionality 76543210 0 xxxxxxx 0 U A R T + I R 1 0xxxxxx 1 1 1xxxx 1 x 1 1 1xxxxx 1 1 11100000 2 11100100 3 11101000 4 I R O n l y 11101100 5 11110000 6 11110100 7 T able 5-48.
AMD Geode™ SC1200/SC1201 Processor Data Book 137 SuperI/O Module 32579B T able 5-50. Bank 3 Register Map Offset T ype Name 00h RO MID . Module and Revision Identification 01h RO SH_LCR. Link Control Shadow 02h RO SH_FCR. FIFO Control Shadow 03h R/W BSR.
138 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B T able 5-53. Bank 6 Register Map Offset T ype Name 00h R/W IRCR3. IR Contro l 3 01h R/W MIR_PW . MIR Pulse Width 02h R/W SIR_PW . SIR Pulse Width 03h R/W BSR. Bank Select 04h R/W BFPL.
AMD Geode™ SC1200/SC1201 Processor Data Book 139 SuperI/O Module 32579B T able 5-56. Bank 1 Bi t Map Register Bits O f f s e t N a m e 76543210 00h LBGD(L) LBGD[7:0] (Low Byte Data) 01h LBGD(H) LBGD[15:8] (High Byte Data) 02h RSVD RSVD 03h LCR BKSE SBRK STKP EPS PEN STB WLS[1:0] BSR BKSE BSR[6:0] (Bank Select) 04h-07h RSVD RSVD T able 5-57.
140 AMD Geode™ SC1200/SC1201 Processor Data Book SuperI/O Module 32579B 06h RFRML(L)/ RFRCC(L) RFRML[7:0] / RFRCC[7:0] (Low Byte Data) 07h RFRML(H)/ RFRCC(H) RSVD RFRML[12:8] / RFRCC[12:8] (High Byte Data) T able 5-5 9. Bank 4 Bit Map (Continued) Register Bits O f f s e t N a m e 76543210 T able 5-60.
AMD Geode™ SC1200/SC1201 Processor Data Book 141 6 Core Logic Mo dule 32579B 6.0 Core Logic Module The Core Logic module is an enh anced PCI-to-Sub-ISA bridge (South Br idge), this module is A CPI-compliant, and provides A T/Sub-ISA functionality . The Core Logic module also contains state-of-the-a r t power manageme nt.
142 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B Integrated A udio • A C97 V ersion 2.0 compliant interface to audio codecs • Secondar y codec suppor t • AMC97 codec .
AMD Geode™ SC1200/SC1201 Processor Data Book 143 Core Logic Mo dule 32579B 6.2.1 Fast- PCI Interface to Exte rnal PCI Bus The Core Logic modu le provides a PCI bus interf ace that is both a slav e for PCI cycles init iated b y the GX1 module or other PCI master de vices, and a non-preemptive master f or DMA transf er cycles.
144 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B 6.2.2.1 Video Re trace Interrupt Bit 7 of the “Serial P ack et” can be used to generate an SMI whenev er a video retrace occurs within the GX1 module. This function is nor mally not used for po wer management but f or SoftV GA routines.
AMD Geode™ SC1200/SC1201 Processor Data Book 145 Core Logic Mo dule 32579B F or example, if a channel had one Mode 4 device and one Mode 0 de vice, then the Mode 4 device w ould hav e com- mand timings f or Mode 0 and data timing f or Mode 4. Th e Mode 0 device would ha v e both command and data timings f or Mode 0.
146 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B 6.2.3.4 UltraDMA/33 Mode The IDE controller of the Core Logic mod ule suppor ts UltraDMA/33. It utilizes the standard IDE Bus Master func- tionality to interface , initiate and control the transfer .
AMD Geode™ SC1200/SC1201 Processor Data Book 147 Core Logic Mo dule 32579B 6.2.4 Universal Serial Bus The Core Logic mod ule provides three complete, indepen- dent USB por ts. Each por t has a Data “Negative” and a Data “P ositiv e” signal. The USB por ts are Open Host Controller Interface (Open- HCI) compliant.
148 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B 6.2.5.1 Sub-ISA Bus Cycles The ISA bus controller issues multiple ISA cycles to satisfy PCI transactions that are larger than 16 bits. A full 32-bit read or write resul ts in two 16-bit ISA transactions or f our 8- bit ISA transactions.
AMD Geode™ SC1200/SC1201 Processor Data Book 149 Core Logic Mo dule 32579B Figure 6-3. PCI to ISA Cycles wit h Delay ed T ransaction Enabled 6.2.5.3 Sub-ISA Bu s Data Steering The Core Logic mod ule performs all of the required data steerin g from SD[7:0] to SD[15:0] dur ing norma l 8-bit ISA cycles, as well as during DMA and ISA master cycles.
150 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B 6.2.5.5 ISA DMA DMA transf ers occur between ISA I/O per ipherals and sys- tem memory (i.
AMD Geode™ SC1200/SC1201 Processor Data Book 151 Core Logic Mo dule 32579B 6.2.5.6 ROM Interface The Core Logic mo dule positively decodes memo ry addresses 000F0000h-000FFFFFh (64 KB) an d FFFC0000h-FFFFFFFFh (256 KB) at reset.
152 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B Figure 6-6. PCI Change to Sub-ISA and Back 6.2.6 A T Compatibility Lo gic The Core Logic module integrates: • T wo 8237-e.
AMD Geode™ SC1200/SC1201 Processor Data Book 153 Core Logic Mo dule 32579B DMA T ransfer Modes Each DMA channel can be programmed for single , blo ck , demand or cascade transf er modes. In the most commonly used mode, single transfer mode, one DMA cycle occurs per DRQ and the PCI bus is released after e v er y cycle .
154 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B DMA Addressing Capability DMA transf ers occu r o ver the entire 32-bit address range of the PCI bus.
AMD Geode™ SC1200/SC1201 Processor Data Book 155 Core Logic Mo dule 32579B 6.2.6.3 Programmable Interrupt Contr oller The Core Logic module con tains two 8259A-equiv alent programmab le interr upt controllers, with eight interrupt request lines each, for a total of 16 interr upts.
156 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B PIC Interrupt Sequence A typical A T -compatible interrupt sequ ence is as f ollows . Any unmasked interrupt generates the inter nal INTR signa l to the CPU. The interrupt contro ller then responds to the interrupt acknowledge (INT A) cycles from the CPU .
AMD Geode™ SC1200/SC1201 Processor Data Book 157 Core Logic Mo dule 32579B 6.2.7.1 I/O P ort 092h System Control I/O P or t 092h allows f or a fast k eyboard asser tion of an A20# SMI and a fast ke yboard CPU reset. Decoding for this register may be disabled via F0 Index 52h[3].
158 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B 6.2.9 P ower Mana gement Logic The Core Logic mo dule integrates advanced pow er man- agement features including idle timer.
AMD Geode™ SC1200/SC1201 Processor Data Book 159 Core Logic Mo dule 32579B 6.2.9.2 Sleep States The SC1200/SC1201 processor suppor ts four Sleep states (SL1-SL3) and the Soft Off stat e (G2/S5 ). These states are fully compliant with the A CPI specification, revision 1.
160 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B 6.2.9.3 P ower Planes Control The SC1200/SC1201 processor suppor ts up to thre e power planes. Three signals are used to control thes e power planes. T able 6-6 describes th e signals and when each is asser ted.
AMD Geode™ SC1200/SC1201 Processor Data Book 161 Core Logic Mo dule 32579B P ower Button The power b utton (PWRBTN#) input provides two e vents: a wak e request, and a sleep request.
162 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B 6.2.10 Po wer Management Programming The power management resources provided by a com- bined GX1 module and Core Logic module base d system suppor ts a high efficiency power management implementa- tion.
AMD Geode™ SC1200/SC1201 Processor Data Book 163 Core Logic Mo dule 32579B The automatic speedup events (video and IRQ) f or Sus- pend Modulation should be used together with software- controlled sp.
164 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B 6.2.10.3 Peripheral P o wer Manageme nt The Core Logic module provides peripheral power man- agement using a combination of device idle timers, address traps, and general pur pose I/O pins.
AMD Geode™ SC1200/SC1201 Processor Data Book 165 Core Logic Mo dule 32579B P ower Management SMI Status Repor ting Registers The Core Logic mod ule updates status registers to reflect the SMI sources. P o wer management SMI sources are the de vice idle timers, address traps, and general pur pose I/O pins.
166 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B 6.2.10.4 P ower Manageme nt Programming Summary T able 6-9 provides a programming register summar y f or the power management timers, tr aps, and functions. For com- plete bit inform ation regarding the registe rs listed in T able 6-9, ref er to Section 6.
AMD Geode™ SC1200/SC1201 Processor Data Book 167 Core Logic Mo dule 32579B 6.2.11 GPIO Interface Up to 64 GPIOs in the in the Core Logi c module are pro- vided f or system control.
168 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B Physical Region Descriptor T able Address Bef ore the bus master star ts a master transfer it must be pro- grammed with a pointer (PRD T able Address register) to a Ph ysical Region Descr iptor T able .
AMD Geode™ SC1200/SC1201 Processor Data Book 169 Core Logic Mo dule 32579B 4) Read the SMI Status register to clear the Bus Master Error and End of P age bits (bits 1 and 0). Set the correct directi on to the Read or Write Contro l bit (Command register bit 3).
170 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B 6.2.12.2 A C97 Codec Interface The AC97 codec (e.g., LM4548) is the master of the serial interf ace and generates the clocks to Core Logic module. Figure 6-13 shows the signal connections between two codecs and the SC1 200/SC1201 processor : • Codec1 can be AC97 Re v .
AMD Geode™ SC1200/SC1201 Processor Data Book 171 Core Logic Mo dule 32579B 6.2.12.3 VSA T echnolo g y Suppor t Hardware The Core Logic mod ule incor porates the required hard- ware in order to suppor t the Vir tual System Architecture™ (VSA) technology f or capture and playback of audio using an external codec.
172 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B In F ast P ath Write, the Core Log ic module responds to writes to the following addresses: 388h, 38Ah, 38Bh, 2x0h, 2x2h, a.
AMD Geode™ SC1200/SC1201 Processor Data Book 173 Core Logic Mo dule 32579B 6.2.12.4 IRQ Configuration Registers The Core Logic modul e provides the ability to set and cle ar IRQs inter nally through software control. If the IRQs are configured for softw are control, they do not respond to ex ter nal hardware .
174 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Mo dule 32579B 6.2.12.6 LPC Interface Signal Definitions The LPC specification lists seven required and six optional signals for supporti ng the LPC interface . Many of the sig- nals are the same sign als f ound on the PCI interface and do not require any new pins on the host.
AMD Geode™ SC1200/SC1201 Processor Data Book 175 Core Logic Module - PCI Configuration Space and Ac cess 32579B 6.3 Register Descriptions The Core Logic modul e is a multi-function module.
176 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Re gister Summary 32579B 6.3.2 Register Su mmary The tables in this subsection summarize the registe rs of the Core Logic module. Included in the tables are the regis- ter’ s reset v alues and page references where the bit f or- mats are f ound.
AMD Geode™ SC1200/SC1201 Processor Data Book 177 Core Logic Module - Register Summar y 32579B 6Ch-6Fh 32 R/W ROM Mask Register 0000FFF0h Page 200 70h-71h 16 R /W IOCS1# Base Address Register 0000h P.
178 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Re gister Summary 32579B B8h 8 RO DMA Shadow Register xxh P age 217 B9h 8 RO PIC Shadow Register xxh P age 217 BAh 8 RO PIT Shado.
AMD Geode™ SC1200/SC1201 Processor Data Book 179 Core Logic Module - Register Summar y 32579B T able 6-15. F0B AR0: GPIO Support Registers Summary F0BAR0+ I/O Offset Width (Bits) T ype Name Reset Va.
180 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Re gister Summary 32579B T able 6-17. F1: PCI He ader Registers for SMI Status and A CPI Suppor t Summary F1 Index Width (Bits) T.
AMD Geode™ SC1200/SC1201 Processor Data Book 181 Core Logic Module - Register Summar y 32579B T able 6-19. F1BAR1: A CPI Suppor t Registers Summar y F1BAR1+ I/O Offset Width (Bits) T ype Name Reset .
182 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Re gister Summary 32579B T able 6-20. F2: PCI Header Register s f or IDE Controller Suppo r t Summary F2 Index Width (Bits) T ype.
AMD Geode™ SC1200/SC1201 Processor Data Book 183 Core Logic Module - Register Summar y 32579B T able 6-21. F2BAR4: IDE Controlle r Support Registers Su mmary F2BAR4+ I/O Offset Width (Bits) T ype Na.
184 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Re gister Summary 32579B T able 6-23. F 3B AR0: Audio Support Re gisters Summary F3BAR0+ Memory Offset Width (Bits) T ype Name Re.
AMD Geode™ SC1200/SC1201 Processor Data Book 185 Core Logic Module - Register Summar y 32579B T able 6-24. F5: PCI He ader Registers for X-Bus Expansion Suppor t Summary F5 Index Width (Bits) T ype .
186 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Re gister Summary 32579B T able 6-26. PCIUSB: USB PCI Confi guration Registe r Summary PCIUSB Index Width (Bits) T ype Name Reset.
AMD Geode™ SC1200/SC1201 Processor Data Book 187 Core Logic Module - Register Summar y 32579B T able 6-27. USB_BAR: USB Contr oller Register s Summary USB_BAR0 +Memory Offset Width (Bits) T ype Name.
188 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Re gister Summary 32579B T able 6-28. ISA Legacy I/O Re gister Summary I/O P or t T ype Name Reference DMA Channel Control Regist.
AMD Geode™ SC1200/SC1201 Processor Data Book 189 Core Logic Module - Register Summar y 32579B 487h R/W DMA Channel 0 High P age Register P age 301 489h R/W DMA Channel 6 High P age Register P age 30.
190 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B 6.4 Chipset Register Space The Chipset Register Space of the Core Logic module is comprised of six separate functions (F0-F5), ea ch with its own register space .
AMD Geode™ SC1200/SC1201 Processor Data Book 191 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B 4 Memory Write an d In validate. Allow the Core Logic module to do memory wr ite and in validate cycles , if the PCI Cache Line register (F0 Index 0Ch) is set to 32 bytes (08h).
192 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B Index 0Ch PCI Cache Line Size Register (R/W) Reset V alue: 00h 7:0 PCI Cache Line Size Register . This register sets the size of the PCI cache line, in increments of f our bytes .
AMD Geode™ SC1200/SC1201 Processor Data Book 193 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B Index 40h PCI Function Control Register 1 (R/W) Reset V alue: 39h 7:6 Reserved. Must be set to 0. 5 Reserved. Must be set to 0.
194 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B 1 P ower Management Configuration T rap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI Function 1 (F1) register space, an SM I is generated.
AMD Geode™ SC1200/SC1201 Processor Data Book 195 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B 2 IDE Reset. Reset IDE bus . 0: Disab le. 1: Enab le (driv e IDE_R ST# lo w). Write 0 to clear. This bit is lev el-sensitiv e and must be cleared after the reset is enabled.
196 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B Index 4Ch-4Fh T op of System Memor y (R/W) Reset Value: FFFFFFFFh 31:0 T op of Syste m Memory . Highest address in system used to deter mine acti ve decode for e x ternal PCI mastered memor y cycles.
AMD Geode™ SC1200/SC1201 Processor Data Book 197 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B Index 52h ROM/A T Logic Control Register (R/W) Re set V alue: 98h 7 Snoop Fast Keyboar d Gate A20 and Fast Reset. Enab les the snoop lo gic associat ed with k eyboard commands for A20 Mask and Reset.
198 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B Index 54h-59h Reser ved Reset V alue: 00h Index 5Ah Decode Control Register 1 (R/W) Reset Value: 01h Indicates PCI positive or negativ e decodi ng for v arious I/O por ts on the ISA bus .
AMD Geode™ SC1200/SC1201 Processor Data Book 199 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B 4 Secondary IDE C ontr oller P ositive Decode . Selects PCI positiv e or subtractive decoding f or accesses to I/O por ts 170h- 177h and 376h-377h (excluding writes to 377h).
200 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B Index 60h-63h ACPI Contr ol Re gister (R/W) Reset V alue: 00000000h 31:8 Reserved. Must be set to 0. 7 SUSP_3 V Shut Down PL L5.
AMD Geode™ SC1200/SC1201 Processor Data Book 201 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B 6 Writes Result in Chip Select. When this bit is set to 1, wr ites to c onfigured I/O address (base address configured in F0 Index 70h; range configured in bits [4:0]) cause IOCS1# to be asser ted.
202 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B 25 Writes Result in Chip Select. When this bit is set to 1, wr ites to conf igured memor y address (bas e address configured in F0 Index 78h; range configured in bits [18:0]) cause DOCCS# to be asser ted.
AMD Geode™ SC1200/SC1201 Processor Data Book 203 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B Index 81h P ower Management Enable Register 2 (R/W) Reset V alu e: 00h 7 Video Access Idle Timer Enable. T urn on Video Idle Timer Count Register (F0 Inde x A6h) and generate an SMI when the timer e xp ires.
204 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B 2 Parallel/Serial Idle Ti mer Enable. T ur n on P arallel/Serial P or t Idle Timer Count Register (F0 Inde x 9Ch) and generate an SMI when the timer expires .
AMD Geode™ SC1200/SC1201 Processor Data Book 205 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B Index 82h P ower Management Enable Register 3 (R/W) Reset V alu e: 00h 7 Video Access T rap.
206 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B 1 Floppy Disk Access T rap. 0: Disab le. 1: Enab le. If this bit is enabled and an access occurs in the address ranges listed below , an SMI is generated.
AMD Geode™ SC1200/SC1201 Processor Data Book 207 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B 2 Video Retrace Interrupt SMI. Allow SMI generation whenev er video retrace occurs. 0: Disab le. 1: Enab le. This inf orm ation is decoded from the serial connection (PSERIAL r egister , bit 7) from the GX1 module.
208 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B Index 85h Second Level PME/SMI Status Mirror Register 2 (RO) Reset V alue: 00h The bits in this register c ontain second lev el status repor ting.
AMD Geode™ SC1200/SC1201 Processor Data Book 209 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B Index 86h Second Level PME/SMI Status Mirror Register 3 (RO) Reset V alue: 00h The bits in this register c ontain second lev el status repor ting.
210 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B Index 87h Second Level PME/SMI Status Mirror Register 4 (RO) Reset V alue: 00h The bits in this register cont ain second lev el status repor ting.
AMD Geode™ SC1200/SC1201 Processor Data Book 211 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B Index 89h General Pu rpose Timer 1 Control Register (R/W) Re set V alue: 00h 7 General Purpose Timer 1 TImebase . Selects timebase for General Purpose Timer 1 (F0 Index 88h).
212 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B Index 8Ah General Purpose Timer 2 Count Register (R/W) Reset V alu e: 00h 7:0 GPT2_COUNT . This field represents the load v alue for Gener al Pur pose Timer 2.
AMD Geode™ SC1200/SC1201 Processor Data Book 213 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B Index 8Eh V GA T imer Count Register (R/W) Reset V alue: 00h 7:0 V GA Timer Load V alue. This field represents the load value f or V GA Timer .
214 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B Index 96h Su spend Configuration Register (R/W) Reset V alue: 00h 7:3 Reserved. Must be set to 0. 2 Suspend Mode Conf iguration.
AMD Geode™ SC1200/SC1201 Processor Data Book 215 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B Index 9Eh-9Fh Keyboar d / Mouse Idle Timer Co unt Register (R/W) Reset V alue: 0000h 15:0 Keyboar d / Mouse Idle Timer C ount.
216 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B Index A Ch-ADh Secondar y Hard Disk Idle Timer Count Register (R/W) Reset V alue: 0000h 15:0 Secondary Hard Disk Idle Timer Count.
AMD Geode™ SC1200/SC1201 Processor Data Book 217 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B Index B8h DMA Shadow Register (RO) Reset V alue: xxh 7:0 DMA Sha dow . This 8-bit por t sequences through the following list of shado wed DMA Controller registers.
218 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B Index BBh R TC Index Shadow Register (RO) Reset V alue: xxh 7:0 RTC Index Shadow . The RTC Shadow register contains the last written v alue of the RTC Inde x register (I/O P ort 070h).
AMD Geode™ SC1200/SC1201 Processor Data Book 219 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B Index CCh User Defined Device 1 Contr ol Register (R/W) Re set V alue: 00h 7 Memory or I/O Mapp ed. Determines how User Defined Device 1 is mapped.
220 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B Index ECh Timer T est Register (R/W) Reset V alue: 00h 7:0 Timer T est V alue. The Timer T e st register is intended only f or test and debug pur poses .
AMD Geode™ SC1200/SC1201 Processor Data Book 221 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B 4 User Defined Device Idle Timer 1 (UDEF1) SMI Status. Indicates whether or not an SMI was caused by e xpiration of User Defined Device 1 (UDEF1) Idle Timer Count Register (F0 Inde x A0h).
222 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B 3 Keyboar d/Mouse Access T rap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the ke yboard or mouse.
AMD Geode™ SC1200/SC1201 Processor Data Book 223 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B 2 Codec SD A T A_IN SMI Status. Indicates whether or not an SMI was ca used by A C97 Codec producing a positive edge on SD A T A_IN.
224 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B 6.4.1.1 GPIO Supp ort Registers F0 Inde x 10h, Base Address Register 0 (F0 BAR0) points to the base address of where the GPIO runtime an d configu- ration registers are located.
AMD Geode™ SC1200/SC1201 Processor Data Book 225 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B Offset 10h-13h GPDO1 — GPIO Data Ou t 1 Register (R/W) Reset V alue: FFFFFFFFh 31:0 GPIO Data Out. Bits [31:0] of this register correspond to GPIO63-GP IO32 signals, respectively .
226 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B 5:0 Signal Select. Selects the GPIO signal to be configured in the Bank se lected via bit 5 setting (i.
AMD Geode™ SC1200/SC1201 Processor Data Book 227 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B 4 PME Edge/Level Select. Selects the type (edge or lev el) of the signal that issues a PME from the selected GPIO signal. 0: Edge input.
228 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B 6.4.1.2 LPC Support Registers F0 Inde x 14h, Base Address Register 1 (F0 BAR1) points to the base address of the regist er space that contains the configuration registers for LPC suppor t.
AMD Geode™ SC1200/SC1201 Processor Data Book 229 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B 8 IRQ8# Source. Selects the interf ace source of the IRQ8# signal. 0: ISA - IRQ8# inter nal signal. (Connected to inter nal R TC.
230 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B 14 IRQ14 P olarity . If LPC is selected as the interface source for IRQ14 (F0BAR1+I/O Offset 00h[14] = 1), this bit allows signal polarity s election.
AMD Geode™ SC1200/SC1201 Processor Data Book 231 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B 2 SMI# P olarity . This bit allows signal polar ity se lection of the SMI# generated from LPC . 0: Active high. 1: Active lo w .
232 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B 2 DRQ2 Source. Selects the interface source of the DRQ2 signal. 0: ISA - DRQ2 (unavailab le e xternally). 1: LPC - LDR Q# (ball L28).
AMD Geode™ SC1200/SC1201 Processor Data Book 233 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B 1 LPC Serial Port 0 Addressing. Serial P or t 0 addresses. See bit 16 f or decode. Address selection made via F0BAR1+I/O Offset 14h[4:2].
234 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - Bridg e, GPIO , and LPC Registers - Function 0 32579B Offset 18h-1Bh LAD_D1 — LPC Address D ecode 1 Register (R/W) Reset V alue: 00000000h 31:16 Reserved. Must be set to 0. 15:9 Wide Generic Base Address Select.
AMD Geode™ SC1200/SC1201 Processor Data Book 235 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32579B 3 LPC Timeout Err or Status. Indicates whether or not an error was generated by a timeout on LPC . 0: No . 1: Y es . Write 1 to clear.
236 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32579B 6.4.2 SMI Status an d A CPI Registers - Function 1 The register space design ated as Function 1 (F1) is used to configure the PCI por tion of suppor t hardware for the SMI Status and ACPI Support registe rs .
AMD Geode™ SC1200/SC1201 Processor Data Book 237 Core Logic Module - SMI Status and ACPI Registers - Function 1 32579B 6.4.2.1 SMI Status Suppor t Registers F1 Index 10h, Base Address Register 0 (F1BAR0), p oints to the base address f or SMI Status register locations.
238 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32579B 6 SMI Source is a V GA Timer Event. Indicates whether or not an SMI was caused by the e xpiration of the V GA Timer (F0 Index 8Eh).
AMD Geode™ SC1200/SC1201 Processor Data Book 239 Core Logic Module - SMI Status and ACPI Registers - Function 1 32579B 12 SMI Source is NMI. (Read to Clear) Indicates whether or not an SMI was caused by NMI activity . 0: No . 1: Y es . 11 SMI Source is IRQ2 of SIO Module.
240 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32579B 1 SMI Source is A udio Subsystem . (Read Only , Read Does Not Clear) Indicates whether or not an SMI w as caused by the audio subsystem.
AMD Geode™ SC1200/SC1201 Processor Data Book 241 Core Logic Module - SMI Status and ACPI Registers - Function 1 32579B 0 SMI Source is Expired General Purpose Timer 1. Indicates whether or not an SMI wa s caused by the e xpiration of Gen- eral Pur pose Timer 1 (F0 Inde x 88h).
242 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32579B Offset 08h-09h SMI Speedup Disable Register (Read to Enable) Reset V alue: 0000h 15:0 SMI Speedup Disable.
AMD Geode™ SC1200/SC1201 Processor Data Book 243 Core Logic Module - SMI Status and ACPI Registers - Function 1 32579B Offset 22h-23h Second Level A CPI PME/SMI Status Register (RC) Rese t V alue: 0000h The bits in this register cont ain second lev el of SMI status repor ting.
244 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32579B 21 EXT_SMI5 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an asser tion of EXT_SMI5. 0: No . 1: Y es .
AMD Geode™ SC1200/SC1201 Processor Data Book 245 Core Logic Module - SMI Status and ACPI Registers - Function 1 32579B 10 EXT_SMI2 SMI Status. (Read Only) Indicates whether or not an SMI was caused b y an asser tion of EXT_SMI2. 0: No . 1: Y es . T o enable SMI generation, set bit 2 to 1.
246 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32579B 0 EXT_SMI0 SMI Enable. When this bit is asser ted, allow EXT_SMI0 to generate an SMI on negative-edge e v ents. 0: Disab le. 1: Enab le.
AMD Geode™ SC1200/SC1201 Processor Data Book 247 Core Logic Module - SMI Status and ACPI Registers - Function 1 32579B 6.4.2.2 A CPI Support Registers F1 Index 40h, Base Address Register 1 (F1BAR1), p oints to the base addre ss of wher e the A CPI Suppor t registers are located.
248 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32579B 0 PWRBTN_DBNC_DIS (Power Button Debounce). When enabled, a high-to-low or lo w- to-high transition of greater than 15.8 ms is required on PWRBTN# before it is recognized.
AMD Geode™ SC1200/SC1201 Processor Data Book 249 Core Logic Module - SMI Status and ACPI Registers - Function 1 32579B 4 BM_STS (Bus Master Status). Indicates if PME was caused b y a system bus master requesting the system bus. 0: No . 1: Y es . For the PME to gener ate an SCI, set F1BAR1+I/O Offset 0Ch[1] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1.
250 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32579B 13 SLP_EN (Sleep Enable). (Write Only) Allow the system to sequence into the sl eeping state associated with the SLP_TYPx (bits [12:10]).
AMD Geode™ SC1200/SC1201 Processor Data Book 251 Core Logic Module - SMI Status and ACPI Registers - Function 1 32579B 0 BIOS_E N (BIOS En able). When this bit is asser ted, allow SMI generati on by A CPI software via writes to GBL_RLS (F1BAR1+I/O Offset 0Ch[2]).
252 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32579B 5 THRM_STS. Indicates if PME was caused by activity on THRM#.
AMD Geode™ SC1200/SC1201 Processor Data Book 253 Core Logic Module - SMI Status and ACPI Registers - Function 1 32579B 7 Reserved. Must be set to 0 6 USB_EN . Allow USB e vents to generate a SCI. 0: Disab le. 1: Enab le 5 THRM_EN. Allow THRM# to generate an SCI.
254 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - SMI Sta tus and A CPI Registers - Function 1 32579B 5 GPWIO_SMIEN1. Allow GPWIO1 to generate an SMI. 0: Disable. (Def ault) 1: Enab le. See F1BAR1+I/O Offset 07h[3] for debounce inf ormation.
AMD Geode™ SC1200/SC1201 Processor Data Book 255 Core Logic Module - SMI Status and ACPI Registers - Function 1 32579B Offset 18h-1Bh A CPI SCI_ROUTING Re gister (R/W) Reset V alue: 00000F00h 31:17 Reserved.
256 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - IDE C ontr oller Registers - Function 2 32579B 6.4.3 IDE Controller Registers - Function 2 The register space design ated as Function 2 (F2) is used to configure Channels 0 and 1 and the PCI portion of sup- por t hardware f or the IDE controllers.
AMD Geode™ SC1200/SC1201 Processor Data Book 257 Core Logic Module - IDE Controller Registers - Function 2 32579B Index 30h-3Fh Reserved Reset V alue: 00h Index 40h-43h Channel 0 Drive 0 PI O R egister (R/W) Reset V alue: 00009172h If Index 44h[31] = 0, F ormat 0.
258 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - IDE C ontr oller Registers - Function 2 32579B Index 44h-47h Channel 0 Drive 0 DMA C ontrol Register (R /W) Reset V alue: 00077771h The structure of this register depends on the v alue of bit 20.
AMD Geode™ SC1200/SC1201 Processor Data Book 259 Core Logic Module - IDE Controller Registers - Function 2 32579B Index 48h-4Bh C hannel 0 Drive 1 PIO Register (R/W) Reset V alue: 00009172h Channel 0 Drive 1 Programmed I/O Control Register . See F2 Inde x 40h for bit descriptions.
260 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - IDE C ontr oller Registers - Function 2 32579B 6.4.3.1 IDE Controller Support Registers F2 Index 20h, Base Address Register 4 (F2BAR4), p oints to the base address o f where the registers for IDE control- ler configuration are located.
AMD Geode™ SC1200/SC1201 Processor Data Book 261 Core Logic Module - IDE Controller Registers - Function 2 32579B Offset 08h ID E Bus Master 1 Command Register — Secondar y (R/W) Reset V alue: 00h 7:4 Reserved. Must be set to 0. Must retur n 0 on reads.
262 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - A udio Registers - Function 3 32579B 6.4.4 Audio Regist ers - Function 3 The register designated as Func tion 3 (F3) is used to con- figure the PCI por tion of suppor t hardware f or the audio registers.
AMD Geode™ SC1200/SC1201 Processor Data Book 263 Core Logic Module - A udio Reg isters - Function 3 32579B 6.4.4.1 A udio Support Re gisters F3 Index 10h, Base Address Register 0 (F3BAR0), p oints to the base address of where the registers for audio sup- por t are located.
264 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - A udio Registers - Function 3 32579B 16 Codec Status V alid. (Read Only) Indicates if the status in bits [15:0] of this r egister is valid. This bi t is high during slots 3 to 11 of the AC97 frame (i.
AMD Geode™ SC1200/SC1201 Processor Data Book 265 Core Logic Module - A udio Reg isters - Function 3 32579B 4 Audio Bus Master 2 SMI Status. Indicates if an SMI was caused by an e vent occurring on A udio Bus Master 2. 0: No . 1: Y es . SMI generation is enabled when A udio Bus Master 2 is enabled (F3BAR0+Memory Offse t 30h[0] = 1).
266 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - A udio Registers - Function 3 32579B 4 Audio Bus Master 2 SMI Status. Indicates if an SMI was caused by an e vent occurring on A udio Bus Master 2. 0: No . 1: Y es . SMI generation is enabled when A udio Bus Master 2 is enabl ed (F3BAR0+Memory Offse t 30h[0] = 1).
AMD Geode™ SC1200/SC1201 Processor Data Book 267 Core Logic Module - A udio Reg isters - Function 3 32579B 12 DMA T rap SMI Sta tus. (Read to Clear) Indicates if an SMI was caused by a trapped I/O access to the DMA I/O T rap. 0: No . 1: Y es. (See the note included in the general description of this register above.
268 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - A udio Registers - Function 3 32579B 5 Low MPU I/O T rap. If this bit is enabled and an access occurs at I/O P or t 300h-301h, an SMI is generated. 0: Disab le. 1: Enab le. T op lev el SMI status is repor ted at F1BAR0+I/O Offset 00h/02h[1].
AMD Geode™ SC1200/SC1201 Processor Data Book 269 Core Logic Module - A udio Reg isters - Function 3 32579B 7 IRQ7 Intern al. Configures IRQ7 f or inter nal (so ftware) or e xternal (hardware) use. 0: Exter nal. 1: Internal. 6 Reserved. Must be set to 0.
270 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - A udio Registers - Function 3 32579B 20 Mask Internal IRQ4. (Write Only) 0: Disab le. 1: Enab le. 19 Mask Internal IRQ3. (Write Only) 0: Disab le. 1: Enab le. 18 Reserved. (Write Only) Must be set to 0.
AMD Geode™ SC1200/SC1201 Processor Data Book 271 Core Logic Module - A udio Reg isters - Function 3 32579B 1 Assert Masked Internal IRQ1. 0: Disab le. 1: Enab le. 0 Reserved. Must be set to 0. Offset 20h Audio Bus Master 0 Command Register (R/W) Reset V alue: 00h Audio Bus Master 0: Output to codec; 32-bit; Left and Right Channels; Slots 3 and 4.
272 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - A udio Registers - Function 3 32579B Offset 28h Audio Bus Master 1 Command Register (R/W) Reset V alue: 00h Audio Bus Master 1: Input from codec; 32-Bit; Left and Right Channels; Slots 3 and 4.
AMD Geode™ SC1200/SC1201 Processor Data Book 273 Core Logic Module - A udio Reg isters - Function 3 32579B Offset 30h Audio Bus Master 2 Command Register (R/W) Reset V alue: 00h Audio Bus Master 2: Output to codec; 16-Bit; Slot 5. 7:4 Reserved. Must be set to 0.
274 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - A udio Registers - Function 3 32579B Offset 38h Audio Bus Master 3 Command Register (R/W) Reset V alue: 00h Audio Bus Master 3: Input from codec; 16-Bit; Slot 5. 7:4 Reserved. Must be set to 0.
AMD Geode™ SC1200/SC1201 Processor Data Book 275 Core Logic Module - A udio Reg isters - Function 3 32579B Offset 40h Audio Bus Master 4 Command Register (R/W) Reset V alue: 00h Audio Bus Master 4: Output to codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memor y Offset 08h[19] selects slot).
276 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - A udio Registers - Function 3 32579B Offset 48h Audio Bus Master 5 Command Register (R/W) Reset V alue: 00h Audio Bus Master 5: Input from codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memory Offset 08h[20] sele cts slot).
AMD Geode™ SC1200/SC1201 Processor Data Book 277 Core Logic Module - X-Bus Expansion Interface - Fu nction 5 32579B 6.4.5 X-Bus Expansion Interface - Function 5 The register space design ated as Function 5 (F5) is used to configure the PCI por tion of suppor t hardware for accessing the X-Bus Expansion suppor t registers.
278 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - X-Bus Expansi on Interface - Function 5 32579B Index 1Ch-1Fh Base Address Register 3 - F5BAR3 (R/W) Reset V alue: 00000000h Reserved. Reser ved f or possible future use by the Core Logic module.
AMD Geode™ SC1200/SC1201 Processor Data Book 279 Core Logic Module - X-Bus Expansion Interface - Fu nction 5 32579B Index 44h-47h F5BAR1 Mask Address Register (R/W) Reset V alue: 00000000h T o use F5BAR1, the mask register sho uld be programmed first.
280 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - X-Bus Expansi on Interface - Function 5 32579B Index 64h-67h Scratchpad: Usually used for Co nfiguration Bl oc k Address (R/W) Reset V alue: 00000000h BIOS writes a value, of t he Configuration Bloc k Address.
AMD Geode™ SC1200/SC1201 Processor Data Book 281 Core Logic Module - X-Bus Expansion Interface - Fu nction 5 32579B 6.4.5.1 X-Bus Expansio n Suppor t Registers F5 Index 10h, Base Address Register 0 (F5BAR0) set the base address that allows PCI access to addi tional I/O Con- trol suppor t registers.
282 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - X-Bus Expansi on Interface - Function 5 32579B Offset 08h-0Bh I/O Control Regi ster 3 (R/W) Reset V alue: 00009000h 31:16 Reserved. Write as read. 15:13 IO_USB_XCVR_V ADJ (USB V oltage Adjustment Conn ection).
AMD Geode™ SC1200/SC1201 Processor Data Book 283 Core Logic Module - USB Controller Registers - PCIUSB 32579B 6.4.6 USB Controller Registers - PCIUSB The registers designated as PCIUSB are 32-bit registers decoded from the PCI address bits [7 :2] and C/BE[3:0]#, when IDSEL is high, AD[10:8] select the app ropriate func- tion, and AD[1:0] are 00.
284 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - USB Con tr oller Registers - PCIUSB 32579B Index 06h-07h Status Register (R/W) Reset V alue: 0280h The PCI specification defines this register to record status in f ormation for PCI rela ted ev ents.
AMD Geode™ SC1200/SC1201 Processor Data Book 285 Core Logic Module - USB Controller Registers - PCIUSB 32579B Index 14h-2Bh Reserved Reset V alue: 00h Index 2Ch-2Dh Subsystem V endor ID (RO) Reset V.
286 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - USB Con tr oller Registers - PCIUSB 32579B 7:6 HostControllerFunctionalState . This field sets the HC state. The HC ma y force a state change from UsbSuspend to UsbResume after detecting resume signaling from a downstream por t.
AMD Geode™ SC1200/SC1201 Processor Data Book 287 Core Logic Module - USB Controller Registers - PCIUSB 32579B Offset 10h-13h HcInterruptEnable Register (R/W) Reset V alue = 00000000h 31 MasterInterruptEnable. This bit is a global interrupt enable. A write of 1 allows interrupts to be enabled via the specific enable bits listed abov e.
288 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - USB Con tr oller Registers - PCIUSB 32579B 2 StartOfF rameEnable. 0: Ignore. 1: Disable interrupt generation due to Star t of F rame. 1 WritebackDoneHeadEnable. 0: Ignore. 1: Disable interrupt generation due to Writeback Done Head.
AMD Geode™ SC1200/SC1201 Processor Data Book 289 Core Logic Module - USB Controller Registers - PCIUSB 32579B Offset 38h-3Bh HcFrameRemaining Register (RO) Reset V alue = 00000000h 31 FrameRemainingT oggle (Read Only). Loaded with Fr ameInter v alT oggle wh en F rameRemaining is load ed.
290 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - USB Con tr oller Registers - PCIUSB 32579B Offset 4Ch-4Fh HcRhDescrip torB Re gister (R/W) Reset V alue = 00000000h 31:16 Po r t Po w e rC on t r ol M a s k . Global-power s witching.
AMD Geode™ SC1200/SC1201 Processor Data Book 291 Core Logic Module - USB Controller Registers - PCIUSB 32579B Offset 54h-57h Hc RhP ortStatus[1] Register (R/W) Reset V alue = 00000000h 31:21 Reserved. Read/Wr ite 0s . 20 P ortResetStatusCha nge. This bit indicates that the por t reset signal has comple ted.
292 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - USB Con tr oller Registers - PCIUSB 32579B 1 Read: PortEnableStatus. 0: P or t disabled. 1: P or t enabled. Write: SetP or tEnab le. Writin g a 1 sets P ortEna b leStatus. Writing a 0 has no effect.
AMD Geode™ SC1200/SC1201 Processor Data Book 293 Core Logic Module - USB Controller Registers - PCIUSB 32579B 3 Read: Po r tOverCurrentIndicator . This bit reflects the state of the O VRCUR pi n dedicated to this por t. This field is only valid if NoOverCurrentProtection is cleared and Ov erCurrentProtectionMode is set.
294 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - USB Con tr oller Registers - PCIUSB 32579B 8 Read: Po r tP owerS tatus. This bit reflects the power state of the por t regardless of the pow er switching mode . 0: P or t power is off .
AMD Geode™ SC1200/SC1201 Processor Data Book 295 Core Logic Module - USB Controller Registers - PCIUSB 32579B Offset 100h-103h HceControl Register (R/W) Reset V alue = 0000000 0h 31:9 Reserved. Read/Wr ite 0s . 8 A20State. Indicate s current state of Gate A20 on k eyboard c ontroller .
296 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32579B 6.4.7 ISA Legacy Register Space The ISA Legacy registers reside in the ISA I/O address space in the address range from 000h to FFFh and are accessed through typical input/ output instructions (i.
AMD Geode™ SC1200/SC1201 Processor Data Book 297 Core Logic Mo dule - ISA Leg acy Regist er Space 32579B 2 Channel 2 T erminal Count. Indicates if TC was reached. 0: No . 1: Y es . 1 Channel 1 T erminal Count. Indicates if TC was reached. 0: No . 1: Y es .
298 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32579B I/O Port 00Bh DMA Channel Mode Register , Channels 3:0 (WO) 7:6 T ransfer Mode. 00: Demand. 01: Single. 10: Bloc k. 11: Cascade. 5 Address Direction.
AMD Geode™ SC1200/SC1201 Processor Data Book 299 Core Logic Mo dule - ISA Leg acy Regist er Space 32579B I/O Port 0D0h (R/W) Read DMA Status Register , Channels 7:4 Note: Channels 5, 6, and 7 are not suppor ted. 7 Channel 7 Request. Indicates if a request is pending.
300 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32579B I/O Port 0D2h Software DMA Request Register , Channels 7:4 (W) Note: Channels 5, 6, and 7 are not suppor ted. 7:3 Reserved. Must be set to 0. 2 Request T ype.
AMD Geode™ SC1200/SC1201 Processor Data Book 301 Core Logic Mo dule - ISA Leg acy Regist er Space 32579B I/O Port 0DEh D MA Write Mask Register Command, Channels 7:4 (W) Note: Channels 5, 6, and 7 are not suppor ted. T able 6-43. D MA Channel Cont r ol Registers (Cont inued) Bit Description T able 6 -44.
302 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32579B T able 6-45. P r ogrammable Interval Timer Re gisters Bit Description I/O Port 040h Write PIT Timer 0 Counter 7:0 Counte r V alue. Read PIT Timer 0 Status 7 Counter Ou tput.
AMD Geode™ SC1200/SC1201 Processor Data Book 303 Core Logic Mo dule - ISA Leg acy Regist er Space 32579B I/O Port 042h Write PIT Timer 2 Counter (Speaker) 7:0 Counte r V alue. Read PIT Timer 2 Status (Spea ker) 7 Counter Ou tput. State of counter output signal.
304 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32579B T able 6-4 6. Programmab le Interrupt Contr oller Register s Bit Description I/O Po r t 020h / 0A0h Master / Slave PIC ICW1 (WO) 7:5 Reserved. Must be set to 0.
AMD Geode™ SC1200/SC1201 Processor Data Book 305 Core Logic Mo dule - ISA Leg acy Regist er Space 32579B 1 IRQ1 / IRQ9 Mask. 0: Not Masked. 1: Mask. 0 IRQ0 / IRQ8 Mask. 0: Not Masked. 1: Mask. I/O Port 020h / 0A0h Master / Slave PIC OCW2 (WO) 7:5 Rotate/EOI Codes.
306 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32579B 1 IRQ1 / IRQ9 Pending. 0: Y es . 1: No . 0 IRQ0 / IRQ8 Pending. 0: Y es . 1: No . Interrupt Service Reg ister 7 IRQ7 / IRQ15 In-Service . 0: No . 1: Y es .
AMD Geode™ SC1200/SC1201 Processor Data Book 307 Core Logic Mo dule - ISA Leg acy Regist er Space 32579B T able 6 -47. Keyboa rd Contr oller Register s Bit Description I/O Port 060h External Keyboar d Controller Data Register (R/W) Keyboar d Controller Data Register .
308 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32579B T able 6- 48. Real-Time Cloc k Register s Bit Description I/O Po r t 070h RTC Address Register (WO) This register is shadowed within the Core Logic module and is read through the RTC Shadow Register (F0 Inde x BBh).
AMD Geode™ SC1200/SC1201 Processor Data Book 309 Core Logic Mo dule - ISA Leg acy Regist er Space 32579B 2:0 Reserved . Must be set to 0. I/O Port 4D1h Interrupt Edge/Level Select Register 2 (R/W) Reset V alue: 00h Notes: 1. If ICW1 - bit 3 in the PIC is set a s le v el, it ov er ri des the setting for bits 7:6 and 4:1 in this register .
310 AMD Geode™ SC1200/SC1201 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32579B.
AMD Geode™ SC1200/SC1201 Processor Data Book 311 7 Video Processor Module 32579B 7.0 Video Processor Module The Video Processor module co ntains a high perf or mance video back-end accelerator , a v.
312 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module 32579B Display Modes • CRT modes: — 640x480x16 bpp at 60-85 Hz vert ical refresh rates — 800x600x16 bpp at 60-85 Hz vert.
AMD Geode™ SC1200/SC1201 Processor Data Book 313 Video Processor Module 32579B 7.2 Functional Description T o understand why the Video Processo r functions as it does, it is first impor tant to understa nd the diff erence between video and graphics.
314 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module 32579B Figure 7-2. NTSC 525 Lines, 60 Hz, Odd Field Figure 7-3. NTSC 525 Lines, 60 Hz, Even Field V er tical Retrace - Logical.
AMD Geode™ SC1200/SC1201 Processor Data Book 315 Video Processor Module 32579B 7.2.1 Video Inp ut P ort (VIP) The VIP block is designed to interface the SC1200/SC1201 processor with external video processors (e.g., Philips PNX1300 or Sigma Designs EM84 00) or e xter nal TV decoders (e.
316 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module 32579B 7.2.1.1 Direct Video Mode As stated pre viously , Direct Video mode is on by def ault so no registers need to be programmed to suppor t this mode other than to select the direct video data at the video mux.
AMD Geode™ SC1200/SC1201 Processor Data Book 317 Video Processor Module 32579B Bob The Bob method d ispla ys the odd frame follow ed by the ev en frame . If a full-scale image is display ed, each line in the odd and ev en field must be v er tically doubled (see Sec- tion 7.
318 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module 32579B We av e The Wea ve method assemb les the odd fie ld and ev en field together to form the complete frame, and then renders the “wea ved” frames to the displa y device .
AMD Geode™ SC1200/SC1201 Processor Data Book 319 Video Processor Module 32579B Figure 7-6. Capture Video Mode W eave Example Using T wo Video Frame Buff ers 7.2.1.4 Capture VBI Mode There are three types of VBI data defined by the CCIR-656 protocol: T ask A d ata, T ask B data, and An cillar y data.
320 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module 32579B 7.2.2 Video Block The Video block receives video data from the VIP bloc k or the GX1 module’ s video frame buff er . Th e video data is f or- matted and scaled and then sent to the Mixer/Blender .
AMD Geode™ SC1200/SC1201 Processor Data Book 321 Video Processor Module 32579B 7.2.2.2 Horizontal Downscal er with 4 -T ap Filtering The Video Processor implements up to 8:1 hor izontal downscaling with 4-tap filter ing for horizontal inter polation.
322 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module 32579B 7.2.2.3 Line Buffer s After the data has been option ally horizontally downscaled the video data is stored in a 3- line b uffer . Each line is 36 0 D WORDs , which means a line width of up to 720 pixels can be stored.
AMD Geode™ SC1200/SC1201 Processor Data Book 323 Video Processor Module 32579B 7.2.3 Mixer/Blende r Block The Mixer/Blender bloc k of the Video Processor module perf or ms all the necessar y functions to proper ly mix/bl end the video data and the graphics data.
324 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module 32579B The video data can be in progressive or inter laced f or mat, while the graphics data is alwa ys in the progressiv e format. The Mixer/Blender can mix/blend either format of video data with graphics data.
AMD Geode™ SC1200/SC1201 Processor Data Book 325 Video Processor Module 32579B 7.2.3.1 YUV to RGB CSC in Video Data Path If the video data is in the YUV color space and RGB mix- ing/blending is desired, this CSC must be enabled. The CSC_FOR_VIDEO bit, F4BAR0+Memo ry Offset 4Ch[10], controls this CSC .
326 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module 32579B Graphics Window The graphics window is defined in the GX1 module’ s dis- pla y controller and is always the full screen resolution. Video Windo w The video window tells th e Mix er/Blender where the video window is and its size.
AMD Geode™ SC1200/SC1201 Processor Data Book 327 Video Processor Module 32579B Mixing/Blendin g Operation T able 7-3 on page 327 shows the truth ta b le used to create th e flow diagram, Figure 7-12 on page 328, that the Mixer/ Blender logic uses to deter mine each pix els disposition.
328 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module 32579B Figure 7-12. Color Ke y and Alpha Blending Logic Color register enabled f or this window “Graphics 2 inside Video” .
AMD Geode™ SC1200/SC1201 Processor Data Book 329 Video Processor Module 32579B 7.2.4 TV OUT Block The TV OUT bloc k provides a full-featured TV output signal. NTSC TV and P AL TV f ormats are both supp orted. A YUV progressiv e scan image is d eliv ered to the TVOUT b lock from the Mix er/Blender block.
330 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module 32579B Flicker Filter , Progressive Video and YUV or RGB Mixing/Blending If RGB mixing/blending is enabl ed, then the flic ker filter’ s ½, 1, ½ coefficients in the Mi xer/Blender b lock can not be used.
AMD Geode™ SC1200/SC1201 Processor Data Book 331 Video Processor Module 32579B The TV interface consists of a set of f our D ACs. • Nor mally , two D A Cs dr iv e the composite TV outp ut, and two other D A Cs drive S-Video TV output.
332 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module 32579B 7.2.8 Integrated PL L The integrated (CR T) PLL can generate frequencies up to 135 MHz from a single 27 MHz source. The clock fre- quency is programmab le using two registers.
AMD Geode™ SC1200/SC1201 Processor Data Book 333 Video Processor Module - Register Summary 32579B 7.3 Register Descriptions The register space for accessing and configur ing the Video Processor is located in the Co re Logic Chipset Register Space (F0-F5).
334 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - Register Summary 32579B 28h-2Bh 32 R/W Miscellaneous Register 00001400h P age 342 2Ch-2Fh 32 R /W PLL2 Clock Select Register.
AMD Geode™ SC1200/SC1201 Processor Data Book 335 Video Processor Module - Register Summary 32579B TV OUT Co nfiguration Register s 800h-803h 32 R /W Horizontal Timing Register 00000000h Page 352 804.
336 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32579B 7.3.2 Video Processo r Register s - Function 4 The register space design ated .
AMD Geode™ SC1200/SC1201 Processor Data Book 337 Video Processor Module - Video Processor Registers - Function 4 32579B Index 3Dh Interrupt Pin Register (R/W) Reset Value: 03h This register selects which interrupt pin the device uses. VIP uses INTC# after reset.
338 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32579B 7.3.2.1 Video Proc essor Support Registe rs - F4B A R0 F4 Index 10h, Base Address Re gister 0 (F4BAR0) sets th e base address that allows PCI access to the Video Proces- sor suppor t registers, not including VIP .
AMD Geode™ SC1200/SC1201 Processor Data Book 339 Video Processor Module - Video Processor Registers - Function 4 32579B 0 VID_EN (Video Enable). Enables video acceleration hardware .
340 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32579B 8 CRT_HSYNC_POL (CRT Horizontal Synchronization Polarity). Selects CRT horizontal sync polarity . 0: CR T horiz ontal sync is normally lo w , and is set hig h during sync interval.
AMD Geode™ SC1200/SC1201 Processor Data Book 341 Video Processor Module - Video Processor Registers - Function 4 32579B 10:0 VID_Y_ST ART (Video Y Start Position).
342 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32579B Offset 1Ch-1Fh Palette (Gamma Correction RA M) Address Register (R/W) Reset V alue: xxxxxxxxh 31:8 Reserved. 7:0 P AL_ADDR (Palette Address).
AMD Geode™ SC1200/SC1201 Processor Data Book 343 Video Processor Module - Video Processor Registers - Function 4 32579B 19:16 CLK_SEL (Clock Select). Selects frequency (in MHz) of the display cloc k. 0000: 25.175 0100: 50 1000: 65 1100: 108 0001: 31.
344 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32579B Offset 44h-47h CRC Signat ure Register (R/W) Reset V alue: xxxxx100h Signature values stored in this regi ster can be read b y the host.
AMD Geode™ SC1200/SC1201 Processor Data Book 345 Video Processor Module - Video Processor Registers - Function 4 32579B 13 GV_SEL (GV Select). Selects input video f orm at. 0: YUV f ormat. 1: RGB f ormat. Note: Mixing and blending configurations are created using bits [13, 11:9] of this register .
346 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32579B Offset 50h-53h Cursor Color Ke y Register (R/W) Reset V alue: 00000000h 31:29 Reserved. 28:24 COLOR_REG_OFFSET (Cursor Color Register Offs et).
AMD Geode™ SC1200/SC1201 Processor Data Book 347 Video Processor Module - Video Processor Registers - Function 4 32579B Offset 68h-6Bh Alpha Window 1 Color Register (R/W) Reset V alue: 00000000h 31:25 Reserved. 24 ALPHA1_COLOR_REG_EN (Alpha Win dow 1 Color Register Enable).
348 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32579B Offset 78h-7Bh Alpha Window 2 Color Register (R/W) Reset V alue: 00000000h 31:25 Reserved. 24 ALPHA2_COLOR_REG_EN (Alpha Win dow 2 Color Register Enable).
AMD Geode™ SC1200/SC1201 Processor Data Book 349 Video Processor Module - Video Processor Registers - Function 4 32579B Offset 88h-8Bh Alpha Window 3 Colo r Register (R/W) Reset V alue: 00000000h 31:25 Reserved. 24 ALPHA3_COLOR_REG_EN (Alpha Win dow 3 Color Register Enable).
350 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32579B 30 Video FIFO OverFlow (Full). 0: No overflo w has occurred. 1: Overflow has occurred. Write 1 to reset this b it. 29 VBI FIFO Underflow (Empty).
AMD Geode™ SC1200/SC1201 Processor Data Book 351 Video Processor Module - Video Processor Registers - Function 4 32579B Offset 414h-417h VBI Horizontal Cont rol Register (R/W) Reset V alue: 00000000h 31:27 Reserved. 26:16 VBI_H_END (VBI Horizontal End).
352 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32579B 1 CT_GENLOCK_EN (Ena ble Continuous GenLock Function). 0: The continuous GenLock function is disabled. 1: Enable locking (i.e ., synchronization) of the GX1 VSYNC wit h the VIP VSYNC on e very VSYNC (i.
AMD Geode™ SC1200/SC1201 Processor Data Book 353 Video Processor Module - Video Processor Registers - Function 4 32579B Offset 80Ch-80Fh Display Line E nd Register (R/W) Reset V alue: 00000000h 31:28 Reserved. 27:16 H_DISP_END (Horizontal Display End).
354 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32579B 10 HOR_INTP (Horizontal Interp olation). 0: Disables inter polation. Pix el replic ation is enabled f or pre-encoder scaler . 1: Enables inter polation in pre-encoder scaler .
AMD Geode™ SC1200/SC1201 Processor Data Book 355 Video Processor Module - Video Processor Registers - Function 4 32579B 22:21 REFEN[1:0] (Enable FrameRef). Enables the e xternally provided F rameRef to initializ e the horizontal and vertical counters and/or the inter nal frame counter .
356 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32579B Offset C08h-C0Bh Timing & Encoder Control 3 Register Reset V alue: 00000000h 31:5 Reserved. 4:3 TV D A C Mode Bits [ 1:0]. Determines signal order of the TV DA C outputs.
AMD Geode™ SC1200/SC1201 Processor Data Book 357 Video Processor Module - Video Processor Registers - Function 4 32579B 15:10 Reserved. 9:0 DISPWIDTH (Displ a y Width). Defines the width of the displayed video in 13.5 MHz cloc k periods. If “F rame_Width” is the displa yed frame width in pix els, the number prog rammed is F rame_Width − 1.
358 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32579B Offset C2Ch-C2Fh D A C Contro l Register Reset V alue: 00000020h 31:7 Reserved. 6 T V _DAC _ T E ST ( T V DAC G l i t ch Tes t ) .
AMD Geode™ SC1200/SC1201 Processor Data Book 359 Video Processor Module - Video Processor Registers - Function 4 32579B 7.3.2.2 VIP Support Registers - F4BAR2 F4 Inde x 18h, Base Address Register 2 (F4 BAR2) points to the base address of where the VIP Configuration registers are located.
360 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32579B 10 Auto-Flip. Video port operation mo de. 0: The video por t automatically detects the e v en and odd fi elds based on the VP_HREF and VP_VSYNC_IN signals or the CCIR-656 control codes.
AMD Geode™ SC1200/SC1201 Processor Data Book 361 Video Processor Module - Video Processor Registers - Function 4 32579B 8 Video Data Captur e Active. (Read Only) 0: Video data is not being stored to memor y . 1: Video data is now being stored to memor y .
362 AMD Geode™ SC1200/SC1201 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32579B Offset 28h-2Bh Video Data Pitch Register (R/W) Reset V alue: 00000000h This register specifies the logical widt h of the video data buff er .
AMD Geode™ SC1200/SC1201 Processor Data Book 363 8 Debu gging and Mo nitoring 32579B 8.0 Deb ugging and Monitori ng 8.1 T estability (JT A G) The T est Access P or t (T AP) allows board le v el interconnec- tion verification and chip production tests.
364 AMD Geode™ SC1200/SC1201 Processor Data Book Debu gging and Mo nitoring 32579B.
AMD Geode™ SC1200/SC1201 Processor Data Book 365 9 Electrical Specifications 32579B 9.0 Electr ical Specifications This chapter provides inf or mation about: • General electrical specificatio ns • DC characteristics • A C characteristics Note: All voltage v alues in this chapter are with respect to V SS unless otherwise noted.
366 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B 9.1.4 Operating Conditions T able 9-3 lists the v arious power supplies of the SC1200/SC1201 processor and provides the device oper ating conditions. Notes: 1) All power sources except V BA T must be connected, even if the function is not used.
AMD Geode™ SC1200/SC1201 Processor Data Book 367 Electrical Specifications 32579B T able 9-4 indicates which power rails are used f or each signal of the SC1200/SC120 1 processor’ s external interface. P ower planes not listed in this table are internal, and are not relate d to signals of the e xter nal interface .
368 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B 9.1.5.3 Definition of Sy stem Conditions f or Measuring On P arameters The SC1200/SC1201 processor’ s current is highly depen- dent on two functional characteristics, DCLK (DO T clock) and SDRAM frequency .
AMD Geode™ SC1200/SC1201 Processor Data Book 369 Electrical Specifications 32579B 9.1.6 Ball Capacitanc e and Inductance T able 9-8 giv es ball capacitance and inductance values.
370 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B 9.1.7 Pull-Up and Pull- Down Resistors The follo wing table lists input balls that are inter nally con- nected to a pull-up (PU) or pull-d o wn (PD) resistor . If these balls are not used, they do not require connection to an e xternal PU or PD resistor .
AMD Geode™ SC1200/SC1201 Processor Data Book 371 Electrical Specifications 32579B 9.2 DC Characteristics T able 9-10 describes the signal buffer types of the SC1200/SC 1201 processor . (See T able 3-2 on page 29 f or each signal’ s buff er type .) The subsections that follo ws provide detailed DC characteristics according to buff er type.
372 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B 9.2.1 IN AB DC Characteristics 9.2.2 IN BTN DC Characteristics 9.2.3 IN PCI DC Characteristics Note that the b uffer type for PCICLK (ball A7) is IN T - not IN PCI . Symbol P arameter Min Max Unit Comments V IH Input Hi gh V oltage 1.
AMD Geode™ SC1200/SC1201 Processor Data Book 373 Electrical Specifications 32579B 9.2.4 IN STRP DC Characteristics 9.2.5 IN T DC Characteristics 9.2.6 IN TS DC Characteristics 9.2.7 IN TS1 DC Characteristics Symbol P arameter Min Max Unit Comments V IH Input Hi gh V oltage 0.
374 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B 9.2.8 IN USB DC Characteristics Figure 9-1. Differential Input Sensitivity f or Common Mode Range 9.2.9 O AC9 7 DC Characterist ics 9.2.10 OD n DC Characteristics Symbol P arameter Min Max Unit Comments V IH Input Hi gh V oltage 2.
AMD Geode™ SC1200/SC1201 Processor Data Book 375 Electrical Specifications 32579B 9.2.11 OD PCI DC Ch aracteristics 9.2.12 O p/n DC Characterist ics 9.2.13 O PCI DC Characteristics 9.2.14 O USB DC Characteristics 9.2.15 TS p/n DC Characteri stics 9.
376 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B 9.3 A C Characteristics The tables in this section list the following A C characteris- tics: • Output delays • I.
AMD Geode™ SC1200/SC1201 Processor Data Book 377 Electrical Specifications 32579B 9.3.1 Memor y Controller Interf ace The minimum input setup and hold ti mes described in Figure 9- 3 (legend C and D) define the sma llest acceptable sampling window during which a synchronous in put signal must be stable to ensure correct o peration.
378 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B T able 9-12. Memory C ontr oller Timing P arameters Symbol P arameter Min Max Unit Comments t 1 Control output valid from SDCLK[3:0] -3.0 + (x * y) 0.1 + (x * y) ns Note 1, Note 2 t 2 MA[12:0], BA[1.
AMD Geode™ SC1200/SC1201 Processor Data Book 379 Electrical Specifications 32579B Figure 9-4. Memory Contr oller Output V alid Timing Diagra m Figure 9-5.
380 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B 9.3.2 Video P o rt (VP ) Interface Figure 9-6. Video Input P or t Timing Diagram T able 9-13 .
AMD Geode™ SC1200/SC1201 Processor Data Book 381 Electrical Specifications 32579B Figure 9-7. Video Output P ort Timing Diagram T able 9-14. V ideo Output Port Timin g P arameters Symbol P arameter .
382 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B 9.3.3 CRT and TFT I nterface T able 9-15 and Figure 9-8 describe the timing of the digital CRT interf ace of the SC1200/SC1201 processor . All mea- surement points in this table are identical to the v oltage measurement lev els described in T able 9-11 on page 376.
AMD Geode™ SC1200/SC1201 Processor Data Book 383 Electrical Specifications 32579B T able 9-16. C R T VESA Compatible D A C (RED, GREEN, and BLUE Outputs) Symbol P arameter (Note 1) Min Max Unit Comments V FR Full range output voltage 0.6 0.72 V SETRES = 470 R L = 37.
384 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B 9.3.4 TV Interfac e T able 9-17. TV DA C (4 Outputs: CVBS, SVY/TVR , SVC/TVB, CVBS/TV G) Symbol Parameter Min Max Unit Comments RES D A C Resolution 10 bits V FR Full range output voltage 182 IRE TVRSET to GND = 1140 Ω R L = 37.
AMD Geode™ SC1200/SC1201 Processor Data Book 385 Electrical Specifications 32579B 9.3.5 ACCESS.b us Interface The f ollow ing tab les describe the timing f or the A CCESS .b us signals . Notes: 1) All ACCESS.b us timing is not 100% tested . 2) In this table tCLK = 1/24MHz = 41 .
386 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B Figure 9-9. A CB Signals: Risi ng and Falling Timing Dia gram Figure 9-10.
AMD Geode™ SC1200/SC1201 Processor Data Book 387 Electrical Specifications 32579B Figure 9 -11. A CB Star t Condit ion TIming Diagr am Figure 9-12. A CB Data Bit Timing Diagram t CSTRsi t DHCsi Star.
388 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B 9.3.6 PCI Bus The SC1200/SC1201 processor i s compliant with PCI bus v2.1 specification. Relev ant information from the PCI bus specification is provided below . All parameters in T able 9-20 are not 100% tested.
AMD Geode™ SC1200/SC1201 Processor Data Book 389 Electrical Specifications 32579B Figure 9-14. V/I Curves for PCI Output Signals Pull-Up Pull-Down T est P oint V IO 0.9 V IO DC Drive P oint AC Drive P oint 0.3 V IO 0.6 V IO 0.1 A C Drive P oint DC Drive P oint T est P oint V IO Equation A fo r V IO >V OUT >0.
390 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B Figure 9-15. PCICLK Timing and Measurement P oints T able 9-21. P CI Clock P arameters Symbol Parameter Min Max Unit.
AMD Geode™ SC1200/SC1201 Processor Data Book 391 Electrical Specifications 32579B Figure 9-16. Load Circuits f or PCI Maxim um Time Measurements T able 9-22.
392 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B 9.3.6.1 Measurement and T est Conditions Figure 9-17. P CI Output Timing Measurement Conditions T able 9-23. Measurement Condition P arameter s Symbol V alue Unit Comments V TH 0.
AMD Geode™ SC1200/SC1201 Processor Data Book 393 Electrical Specifications 32579B Figure 9-18. PCI Input Timing Measuremen t Conditions Figure 9-19. PCI Reset Timing V TEST V TEST Input V alid t SU .
394 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B 9.3.7 Sub-ISA Int erface All output timing is guaranteed for 50 pF load, unless otherwi se specified. The ISA Clock divisor (defined in F0 Index 50h[2:0] of the Core Logic module) is 011.
AMD Geode™ SC1200/SC1201 Processor Data Book 395 Electrical Specifications 32579B t RD Y A2 IOCHRD Y valid after IOR#/MEMR#/ RD#/DOCR# /IO W#/MEMW#/W R#/ DOCW# F E 8 M, I/O 366 9-20 9-21 t IOCSA IOC.
396 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B Figure 9-20. Sub-ISA Read Operation Timing Diagr am t RDx t ARx Valid Valid Valid Data t RCUx t RA t RVDS t RDH t HZ.
AMD Geode™ SC1200/SC1201 Processor Data Book 397 Electrical Specifications 32579B Figure 9-21. Sub-ISA Writ e Operation Timing Diagram t WRx t AWx Valid Valid Valid Data t WCUx t WA t DH A[23:0]/BHE.
398 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B 9.3.8 LPC Interface Figure 9-22. LPC Output Timing Diagram Figure 9-23.
AMD Geode™ SC1200/SC1201 Processor Data Book 399 Electrical Specifications 32579B 9.3.9 IDE Interfa ce Timing Figure 9-24. IDE Reset Timing Dia gram T able 9-26. IDE Genera l Timing P arameters Symbol Parameter Min Max Unit Comments t IDE_F ALL IDE signals f all time (from 0.
400 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B T able 9-27. IDE Register T ransfer to/fr om Device Timing P arameter s Symbol P arameter Mode Unit Comments 01235 t.
AMD Geode™ SC1200/SC1201 Processor Data Book 401 Electrical Specifications 32579B Figure 9-25. Register T ransf er to/fr om Device Timing Diag ram ADDR valid 1 WRITE READ t 0 t 1 t 2 t 9 t 2i t 3 t .
402 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B T able 9-28. IDE PIO Data T ran sfer to/fr om Device Timing Parameters Symbol P arameter Mode Unit Comments 01234 t .
AMD Geode™ SC1200/SC1201 Processor Data Book 403 Electrical Specifications 32579B Figure 9- 26. PIO Data T ran sfer to/from De vice Timin g Diagram ADDR valid 1 WRITE IDE_DATA[15:0] READ IDE_DATA[15.
404 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B T able 9-29. IDE Multiw or d DMA Data T ransfer Timing P arameter s Symbol P arameter Mode Unit Comments 012 t 0 Cyc.
AMD Geode™ SC1200/SC1201 Processor Data Book 405 Electrical Specifications 32579B Figure 9-27. Multiwor d DMA Data T ransfer Timing Diagr am t M t N t L t j t K t D t I t E t Z t F t G t G t H t 0 I.
406 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B T able 9-30. IDE UltraDMA Data Bur st Timing P arameters Symbol P arameter Mode 0 Mode 1 Mode 2 Unit Comments Min Ma.
AMD Geode™ SC1200/SC1201 Processor Data Book 407 Electrical Specifications 32579B All timing parameters are measured at the connector of the d e vice to which the parameter ap plies. F or e xample, the sender stops generating STROBE edges t RFS after the negation of DMARD Y .
408 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B Figure 9-29. Sustained UltraDMA Data In Burst Timing Diagram t DS t DH t DS t DH t DH t DVH t DVS t DVH t DVS t DVH .
AMD Geode™ SC1200/SC1201 Processor Data Book 409 Electrical Specifications 32579B Figure 9-30. Host P ausing an UltraDMA Data In Burst Timing Dia gram t RP IDE_D A T A[15:0] (de vice) t RFS t SR IDE.
410 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B Figure 9-31. Device T erminating an Ultr aDMA Da ta In Burst Timing Diagr am IDE_D A T A[15:0] (de vice) IDE_CS[0:1].
AMD Geode™ SC1200/SC1201 Processor Data Book 411 Electrical Specifications 32579B Figure 9-32. Host T erminat ing an UltraDMA Data In Bur st Timing Diag ram IDE_D A T A[15:0] (de vice) IDE_CS[0:1]# .
412 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B Figure 9-33. Initiating an UltraDMA Data Out Bur st Timing Diagram IDE_D A T A[15:0] (de vice) IDE_CS[0:1]# IDE_ADDR.
AMD Geode™ SC1200/SC1201 Processor Data Book 413 Electrical Specifications 32579B Figure 9-34. Sustained UltraDMA Data Out Burst Timing Dia gram t DS t DH t DS t DH t DH t DVH t DVS t DVH t DVS t DV.
414 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B Figure 9 -35. Device Pausing an Ult raDMA Data O ut Burst Timing D iagram t RP IDE_D A T A[15:0] (host) t RFS t SR I.
AMD Geode™ SC1200/SC1201 Processor Data Book 415 Electrical Specifications 32579B Figure 9-36. Host T erminating an UltraDMA Data Out Bur st Timing Diagram IDE_D A T A[15:0] (host) IDE_CS[0:1]# IDE_.
416 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B Figure 9-3 7. Device T ermin ating an UltraDMA Data Out Burst Timing Diagram IDE_D A T A[15:0] (host) IDE_CS[0:1]# I.
AMD Geode™ SC1200/SC1201 Processor Data Book 417 Electrical Specifications 32579B 9.3.10 Universal Serial Bus (USB) T able 9-31. USB Timing Parameters Symbol P arameter Min Ma x Unit Fig ure Comment.
418 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B t USB_DJU22 Source diff erential dr iv er jitter for paired transactions –150 15 0 ns 9-39 Function (downstream), Note 4 t USB_SE2 Source EOP width 1.
AMD Geode™ SC1200/SC1201 Processor Data Book 419 Electrical Specifications 32579B Figure 9-38. USB Data Signal Ris e and F all Timing Diagram Figure 9-39.
420 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B Figure 9-40. USB EOP Width Timing Diagram Figure 9-41. U SB Receiv er Jitter T olerance Timing Diagram EOP Width Dat.
AMD Geode™ SC1200/SC1201 Processor Data Book 421 Electrical Specifications 32579B 9.3.11 Serial P or t (U ART) Figure 9-42. U ART , Sharp-IR, SIR, and C onsu mer Remote Contr ol Timing Diagram T able 9-3 2.
422 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B 9.3.12 F ast IR Port Tim ing Figure 9-43. Fast IR Timing (MIR and FIR) Diagram T able 9-33.
AMD Geode™ SC1200/SC1201 Processor Data Book 423 Electrical Specifications 32579B 9.3.13 P arallel Port Timin g Figure 9-44. Standard P arallel Port T ypical Data Exchange Timing Diagram T able 9-34.
424 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B Figure 9-45. Enhanced Parallel P ort Timing Diagram T able 9-35. Enhanced P arall el P ort Timing P arameter s Symbol P arameter Min Max EPP 1.
AMD Geode™ SC1200/SC1201 Processor Data Book 425 Electrical Specifications 32579B 9.3.13.1 Extended Capabili ties P or t (ECP) Timing Figure 9-46. ECP Forward Mode Timing Dia gram T able 9-3 6.
426 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B Figure 9-47. ECP Rever se Mode Timing Dia gram T able 9 -37. ECP Reverse Mod e Timing P arameter s Symbol P arameter.
AMD Geode™ SC1200/SC1201 Processor Data Book 427 Electrical Specifications 32579B 9.3.14 A udio Interfac e Timing (A C97) Figure 9-48. A C97 Reset Timing Dia gram Figure 9-49. A C97 Sync Timing Diagram T able 9-38. AC Reset Timing Parameters Symbol P arameter Min T yp Max Unit Comments t RST_LO W A C97_RST# active lo w pulse width 1.
428 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B Figure 9-50. A C97 Cloc ks Diagram T able 9-40. A C97 Clocks P arameters Symbol P arameter Min T yp Max Unit Comments F BIT_CLK BIT_CLK frequency 12.288 MHz t CLK_PD BIT_CLK period 81.
AMD Geode™ SC1200/SC1201 Processor Data Book 429 Electrical Specifications 32579B Figure 9-51. A C97 Data TIming Diagr am T able 9-41. A C97 I/O Timin g P arameters Symbol Parameter Min T y p Max Unit Comments t AC 97_S Input setup to falling edge of BIT_CLK 15.
430 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B Figure 9-52. A C97 Rise and F all Timing Dia gram T able 9-42. A C97 Signal Rise and F all Timing P arameter s Symbo.
AMD Geode™ SC1200/SC1201 Processor Data Book 431 Electrical Specifications 32579B Figure 9-53. AC97 L ow P o wer Mode Timing Dia gram T able 9-43. A C97 Lo w P ower Mode Timing P arameters Symbol Parameter Min T yp Max Unit Comments t s2_pdow n End of Slot 2 to BIT_CLK, SD A T A_IN low 1.
432 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B 9.3.15 P ower Manage ment LED# Cycle time: 1 s ± 0.1 s, 40%-60% duty cycle . Figure 9-54. PWRBTN# T rigger and ONCTL# Timing Diagram Figure 9-55. GP WIO and ONCTL# Timing Diagram T able 9-44.
AMD Geode™ SC1200/SC1201 Processor Data Book 433 Electrical Specifications 32579B 9.3.16 P ower-Up Sequen cing Figure 9-56. P ower -Up Sequenci ng With PWRBTN# Timing Dia gram T able 9-4 6.
434 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B Figure 9-57. P ower -Up Sequencing Wit hout PWRBTN# Timing Diagram A CPI is non-functional and a ll A CPI outputs are unde fined when the power-up sequence does not include us ing the pow er button.
AMD Geode™ SC1200/SC1201 Processor Data Book 435 Electrical Specifications 32579B 9.3.17 JT A G Interface Figure 9-58. TCK Measurement P oints and Timing Diagram T able 9-48.
436 AMD Geode™ SC1200/SC1201 Processor Data Book Electrical Specifications 32579B Figure 9-59. JT A G T est Timing Diagram TCK t 8 Input Output TDO TDI, t 11 t 13 t 9 t 7 t 6 t 12 t 10 TMS Signals S.
AMD Geode™ SC1200/SC1201 Processor Data Book 437 10 Pac kage Specifications 32579B 10.0 P ac kage Specifications 10.1 Thermal Characteristics The junction-to-case ther mal resistance ( θ JC ) of th e pack- ages shown in T ab le 10-1 can be us ed to calculat e the junction (die) temperature under any given circumstance.
438 AMD Geode™ SC1200/SC1201 Processor Data Book Pac kage Specifications 32579B 10.1.1 Heatsink Considerations T able 10-2 on page 437 shows the maximum allowed ther- mal resistance of a heatsink for par ticular operating envi- ronments.
AMD Geode™ SC1200/SC1201 Processor Data Book 439 Pac kage Specifications 32579B 10.2 Ph ysical Dimensions The figures in this section provide the mechanical package outlines for the BGU481 (481-T erminal Ball Grid Arra y Ca vity Up) package. Figure 10-2.
440 AMD Geode™ SC1200/SC1201 Processor Data Book Pac kage Specifications 32579B Figure 10-3. BGU481 Pac kage - Bottom Vie w.
AMD Geode™ SC1200/SC1201 Processor Data Book 441 Appendix A: Suppor t Documentation 32579B Appendix A Suppor t Documentation A.1 Or der Information A.2 Macr ovision Pr oduct Notice The SC1201 processor is pro tected b y U.S . patent number s 4,631,603, 4,577,216, and 4, 819,098 and other intellectu al proper ty rights.
442 AMD Geode™ SC1200/SC1201 Processor Data Book Appendix A: Data Bo ok Revision History 32579B A.3 Data Book Re vision History This section is a repor t of th e re vi sion/creation process of th e data book fo r the AMD Geode™ SC1200/SC1 201 processor .
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Een belangrijk punt na aankoop van elk apparaat AMD SC1201 (of zelfs voordat je het koopt) is om de handleiding te lezen. Dit moeten wij doen vanwege een paar simpele redenen:
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In een situatie waarin je al een beziter van AMD SC1201 bent, maar toch heb je de instructies niet gelezen, moet je het doen voor de hierboven beschreven redenen. Je zult dan weten of je goed de alle beschikbare functies heb gebruikt, en of je fouten heb gemaakt die het leven van de AMD SC1201 kunnen verkorten.
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