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329366-001 Intel ® Core™ i7 Processor Family for LGA2011 Socket Datasheet – Volume 1 of 2 Supporting Desktop Intel ® Core™ i7-4960X Extreme Edition Processor Series for the LGA2011 Socket Supp.
2 Datasheet INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH Intel ® PRODUCTS. NO LICENSE, Express* OR IMPLIED, BY EST OPPEL OR O THERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DO CUMENT .
Datasheet 3 Table of Contents 1 Introduction .............................................................................................................. 8 1.1 Processor Feature Details ...............................................................
4 Datasheet 4.2 Processor Core / Package Power Management ...................................................... 32 4.2.1 Enhanced Intel ® SpeedStep ® Technology ................................................. 32 4.2.2 Low-Power Idle States ......
Datasheet 5 Figures 1-1 Processor Platform Block Diagram Example ............................................................. 9 1-2 PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) .................. 12 2-1 PCI Express* Layering Diagram .
6 Datasheet 7-10 Voltage Specifications ........................................................................................ 63 7-11 Current Specifications........................................................................................ 65 7-12 V CC Overshoot Specifications .
Datasheet 7 Revision History § Revision Number Description Date 001 • Initial release September 2013.
Introduction 8 Datasheet 1 Introduction The Intel ® Core™ i7 processor family for LGA2011 socket are the next gener ation of 64-bit, multi-core desktop processors built on 22-nanometer process technology .
Datasheet 9 Introduction 1.1 Processor Feature Details • Up to 6 execution cores • Each core supports two threads (Intel ® Hyper- Threading T echnology), up to 12 threads per socket • 32KB inst.
Introduction 10 Datasheet 1.2 Supported Technologies • Intel ® Virtualization T echnology (Intel ® VT) • Intel ® Virtualization T echnology (Intel ® VT) for Directed I/O (Intel ® VT -d) • Intel ® Virtualization T echnology (Intel ® VT) Processor Extensions • Intel ® 64 Architecture • Intel ® Streaming SIMD Extensions 4.
Datasheet 11 Introduction 1.3.2 PCI Express* • The PCI Express* port(s) are fully-compliant with the PCI Express* Base Specification , Revision 3.0 (PCIe 3.0) • Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s) • Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express* devices at PCIe* 3.
Introduction 12 Datasheet 1.3.3 Direct Media Interface Gen 2 (DMI2) • Serves as the chip-to-chip interface to the PCH • The DMI2 port supports x4 link width and only operates in a x4 mode when in DMI2 • Operates at PCI Express* 1.
Datasheet 13 Introduction 1.3.4 Platform Environment Control Interface (PECI) The PECI is a one-wire interface that provides a communication channel between a PECI client (the processor) and a PECI master (the PCH).
Introduction 14 Datasheet 1.6 Package Summary The processor socket type is noted as LGA2011. The processor package is a 52.5 x 45 mm FC-LGA package (L GA2011). Refer to the Processor Thermal Mechanical Specification and Design Guide (see Related Documents section) for the package mechanical specifications.
Datasheet 15 Introduction Intel ® VT -d Intel ® Virtualization T echnology (Intel ® VT) for Directed I/O. Intel VT -d is a hardware assist, under system software (Virtual Machine Manager or operating system) control, for enabling I/O device virtualization.
Introduction 16 Datasheet 1.8 Related Documents Refer to the following documents for additional information. TSOD Thermal Sensor on DIMM UDIMM Unbuffered Dual In-line Module Uncore The portion of the processor comprising the shared cache, IMC, HA, PCU, and UBox.
Datasheet 17 Introduction § Table 1-3. Public Specifications Document Document Number / Location Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info PCI Local Bus Specification 3.0 http://www.pcisig.com/specifications PCI Express Base Specification - Revision 2.
Interfaces 18 Datasheet 2 Interfaces This chapter describes the functional behaviors supported by the processor . T opics covered include: • System Memory Interface • PCI Express* Interface • Direct Media Interface 2 (DMI2) / PCI Express* Interface • Platform Environment Control Interface (PECI) 2.
Datasheet 19 Interfaces 2.2 PCI Express* Interface This section describes the PCI Express* 3.0 interface capabilities of the processor . See the PCI Express* Base Specification for details of PCI Express* 3.
Interfaces 20 Datasheet 2.2.1.1 Transaction Layer The upper layer of the PCI Express* architecture is the T ransaction Layer . The T ransaction Lay er's primary responsibility is the assembly and disassembly of T ransaction Lay er Pack ets (TLPs).
Datasheet 21 Interfaces 2.3 Direct Media Interface 2 (DMI2) / PCI Express* Interface Direct Media Interface 2 (DMI2) connects the processor to the Platform Controller Hub (PCH). DMI2 is similar to a four-lane PCI Express* supporting a speed of 5 GT/s per lane.
Technologies 22 Datasheet 3 Technologies This chapter covers the following technologies: • Intel ® Virtualization T echnology (Intel ® VT) • Security T echnologies • Intel ® Hyper- Threading .
Datasheet 23 Technologies 3.1.2 Intel ® VT-x Features The processor core supports the following Intel VT - x features: • Extended Page T ables (EPT) — hardware assisted page table virtualization. — eliminates VM exits from guest operating system to the VMM for shadow page- table maintenance.
Technologies 24 Datasheet 3.1.3.1 Intel ® VT-d Features Supported The processor supports the following Intel VT -d features: • Root entry , context entry , and default context • Support for 4-K p.
Datasheet 25 Technologies 3.2 Security Technologies 3.2.1 Intel ® Advanced Encryption Standard New Instructions (Intel ® AES-NI) Instructions These instructions enable fast and secure data encryption and decryption, using the Advanced Encryption Standard (Intel AES-NI) which is defined by FIPS Publication number 197.
Technologies 26 Datasheet 3.4 Intel ® Turbo Boost Technology Intel T urbo Boost T echnology is a feature that allows the processor to opportunistically and automatically run faster than its rated oper ating frequency if it is operating below power , temperature, and current limits.
Datasheet 27 Technologies 3.6 Intel ® Advanced Vector Extensions (Intel ® AVX) Intel Advanced V ector Extensions (Intel A VX) is a new 256-bit vector SIMD extension of Intel Architecture. The introduction of Intel A VX started with the 2nd Generation Intel ® Core™ processor family .
Technologies 28 Datasheet • Compatibility – Intel A VX is backward compatible with previous ISA extensions including Intel SSE4: — Existing Intel SSE applications/libr ary can: • Run unmodifie.
Datasheet 29 Power Management 4 Power Management This chapter provides information on the following power management topics: • Advanced Configur ation and P ower Interface (ACPI) States Supported .
Power Management 30 Datasheet Notes: 1. Package C7 is not supported. 2. All package states are defined to be "E" states – such that the states always exit back into the LFM point upon execution resume 3.
Datasheet 31 Power Management 4.1.3 Integrated Memory Controller (IMC) States 4.1.4 Direct Media Interface Gen 2 (DMI2) / PCI Express* Link States Note: L1 is only supported when the DMI2/PCI Express* port is operating as a PCI Express* port. Table 4-4.
Power Management 32 Datasheet 4.1.5 G, S, and C State Combinations 4.2 Processor Core / Package Power Management While executing code, Enhanced Intel SpeedStep ® T echnology optimizes the processor frequency and core voltage based on workload. Each frequency and voltage operating point is defined by ACPI as a P-State.
Datasheet 33 Power Management 4.2.2 Low-Power Idle States When the processor is idle, low-power idle states (C -states) are used to save power . More power savings actions are taken for numerically higher C -States. However , higher C-states ha ve longer exit and entry latencies.
Power Management 34 Datasheet Note: 1. If enabled, the core C-state will be C1E if all actives cores ha ve also resolved a core C1 state or higher . 4.2.3 Requesting Low-Power Idle States The core C-state will be C1E if all activ es cores have also resolved a core C1 state or higher .
Datasheet 35 Power Management 4.2.4 Core C-states The following are general rules for all core C -states, unless specified otherwise: • A core C-state is determined by the lowest numerical thread state (such as, Thread 0 requests C1E while Thread 1 requests C3, resulting in a core C1E state).
Power Management 36 Datasheet 4.2.4.6 Delayed Deep C-States The Delayed Deep C -states (DDCst) feature on this processor replaces the “C-state auto-demotion” scheme used in the previous processor generation. Deep C -states are defined as CC3 through CC7 (refer to T able 4-3 for supported deep C-states).
Datasheet 37 Power Management There is also a concept of Execution Allowed (EA). When EA status is 0, the cores in a socket are in C3 or a deeper state; a socket initiates a request to enter a coordinated package C-state. The coordination is across all sock ets and the PCH.
Power Management 38 Datasheet 4.2.5.2 Package C1/C1E State No additional power reduction actions are taken in the package C1 state. However , if the C1E substate is enabled, the processor automatically transitions to the lowest supported core clock frequency , followed by a reduction in voltage.
Datasheet 39 Power Management 4.2.5.5 Package C6 State A processor enters the package C6 low-power state when: • At least one core is in the C6 state. • The other cores are in a C6 or lower power state, and the processor has been granted permission by the platform.
Power Management 40 Datasheet 4.3.1 CKE Power-Down The CKE input land is used to enter and exit different power-down modes. The memory controller has a configurable activity timeout for each r ank. When no reads are present to a given rank for the configured interv al, the memory controller will transition the rank to power -down mode.
Datasheet 41 Power Management 4.3.2.2 Self-Refresh Exit Self-refresh exit can be either a message from an external unit (PCU in most cases, but also possibly from any message-channel master) or as reaction for an incoming transaction. Here are the proper actions on self-refresh exit: • CK is enabled, and four CK cycles driven.
Thermal Management Specifications 42 Datasheet 5 Thermal Management Specifications The processor requires a thermal solution to maintain temperatures within oper ating limits. Any attempt to operate the processor outside these limits may result in permanent damage to the processor and potentially other components within the system.
Datasheet 43 Signal Descriptions 6 Signal Descriptions This chapter describes the processor signals. The signals are arranged in functional groups according to their associated interface or category .
Signal Descriptions 44 Datasheet 6.2 PCI Express* Based Interface Signals Note: PCI Express* Ports 1, 2, and 3 signals are receive and tr ansmit differential pairs. Table 6-2. Memory Channel Miscellaneous Signal Name Description DDR_RESET_C01_N DDR_RESET_C23_N System Memory Reset: Reset signal from processor to DRAM devices on the DIMMs.
Datasheet 45 Signal Descriptions PE2B_TX_DN[7:4] PE2B_TX_DP[7:4] PCIe Transmit Data Output PE2C_TX_DN[11:8] PE2C_TX_DP[11:8] PCIe Transmit Data Output PE2D_TX_DN[15:12] PE2D_TX_DP[15:12] PCIe Transmit Data Output Table 6-5.
Signal Descriptions 46 Datasheet 6.3 Direct Media Interface Gen 2 (DMI2) / PCI Express* Port 0 Signals 6.4 Platform Environment Control Interface (PECI) Signal 6.5 System Reference Clock Signals 6.6 Joint Test Action Group (JTAG) and Test Access Point (TAP) Signals Table 6-7.
Datasheet 47 Signal Descriptions 6.7 Serial Voltage Identification (SVID) Signals 6.8 Processor Asynchronous Sideband and Miscellaneous Signals TDO Test Data Out: This signal transfers serial test data out of the processor . TDO provides the serial output needed for JT AG specification support.
Signal Descriptions 48 Datasheet PROCHOT_N Processor Hot: PROCHOT_N will go activ e when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled.
Datasheet 49 Signal Descriptions TXT_AGENT Intel ® Trusted Execution Technology (Intel ® TXT) Agent: This is a strap signal: 0 = Default. The socket is not the Intel ® TXT Agent.
Signal Descriptions 50 Datasheet 6.9 Processor Power and Ground Supplies § § § § Table 6-14. Power and Ground Signals Signal Name Description VCC V ariable power supply for the processor cores, lowest level caches (LLC), ring interface, and home agent.
Datasheet 51 Electrical Specifications 7 Electrical Specifications This chapter covers the following topics: • Processor Signaling • Signal Group Summary • Power -On Configuration (POC) Options • Absolute Maximum and Minimum Ratings • DC Specifications 7.
Electrical Specifications 52 Datasheet 7.1.4 Platform Environmental Control Interface (PECI) PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitoring devices.
Datasheet 53 Electrical Specifications Clock multiplying within the processor is provided by the internal phase locked loop (PLL) that requires a constant frequency BCLK{0/1}_DP , BCLK{0/1}_DN input, with exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP , BCLK{0/1}_DN inputs are provided in T able 7-15 .
Electrical Specifications 54 Datasheet 7.1.8.2 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low and full power states. This may cause voltages on power planes to sag below their minimum v alues if bulk decoupling is not adequate.
Datasheet 55 Electrical Specifications 7.1.8.3.1 Serial Voltage Identification (SVID) Commands The processor provides the ability to oper ate while transitioning to a new VID setting and its associated processor voltage r ails (V CC, V SA , and V CCD ).
Electrical Specifications 56 Datasheet 7.1.8.3.5 SVID Power State Functions – SetPS The processor has three power state functions and these states will be set seamlessly with the SVID bus using the SetPS command.
Datasheet 57 Electrical Specifications 7.1.8.3.6 SVID Voltage Rail Addressing The processor addresses four different voltage rail control segments within VR12 (V CC , V CCD_01 , V CCD_23 , and V SA ). The SVID data packet contains a 4-bit addressing code.
Electrical Specifications 58 Datasheet Notes: 1. 00h = Off State 2. VID Range HEX 01-32 are not used by the processor . 3. For VID R anges supported, see T able 7-10 . 4. V CCD is a fixed voltage of 1.35V or 1.5V . 7.1.9 Reserved or Unused Signals All Reserv ed (RSVD) signals must not be connected.
Datasheet 59 Electrical Specifications Table 7-5. Signal Groups (Sheet 1 of 3) Differential / Single Ended Buffer Type Signals 1 DDR3 Reference Clocks 2 Differential SSTL Output DDR{0/1/2/3}_CLK_D[N/P.
Electrical Specifications 60 Datasheet PCI Express* Miscellaneous Signals Single ended Analog Input PE_RBIAS_SENSE Reference Input/Output PE_RBIAS PE_VREF_CAP DMI2/PCI Express* Signals Differential DM.
Datasheet 61 Electrical Specifications Notes: 1. Refer to Chapter 6 for signal description details. 2. DDR{0/1/2/3} refers to DDR3 Channel 0, DDR3 Channel 1, DDR3 Channel 2 and DDR3 Channel 3. Notes: 1. Refer to T able 7-17 for details on the R ON (Buffer on Resistance) v alue for this signal.
Electrical Specifications 62 Datasheet 7.4 Absolute Maximum and Minimum Ratings T able 7-8 specifies absolute maximum and minimum ratings. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Datasheet 63 Electrical Specifications Notes: 1. Storage conditions are applicable to storage en vironments only . In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Stor age within these limits will not affect the long-term reliability of the device.
Electrical Specifications 64 Datasheet Notes: 1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on pre-silicon characterization. 2. Individual processor VID values may be calibr ated during manufacturing such that two devices at the same speed may have different settings.
Datasheet 65 Electrical Specifications Notes: 1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on final silicon characterization.
Electrical Specifications 66 Datasheet 7.5.2 Die Voltage Validation Core voltage (V CC ) overshoot ev ents at the processor must meet the specifications in T able 7-12 when measured across the VCC_SENSE and VSS_VCC_SENSE lands. Overshoot events that are < 10 ns in dur ation may be ignored.
Datasheet 67 Electrical Specifications 7.5.3 Signal DC Specifications DC specifications are defined at the processor pads, unless otherwise noted. DC specifications are only valid while meeting specifications for case temper ature, clock frequency , and input voltages.
Electrical Specifications 68 Datasheet Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The voltage rail V CCD which will be set to 1.50V or 1.35V nominal depending on the voltage of all DIMMs connected to the processor .
Datasheet 69 Electrical Specifications Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. These specifications are specifi ed at the processor pad. 2. Crossing V oltage is defined as the instantaneous voltage value when the rising edge of BCLK{0/1}_DN is equal to the falling edge of BCLK{0/1}_DP .
Electrical Specifications 70 Datasheet Note: 1. These signals are measured between V IL and V IH . 2. The signal edge rate must be met or the signal must transition monotonically to the asserted state. Notes: 1. V TT refers to instantaneous V TT . 2. Measured at 0.
Datasheet 71 Electrical Specifications Notes: 1. This table applies to the processor sideband and miscellaneous signals specified in T able 7-5 . 2. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 3. These signals are measured between V IL and V IH .
Electrical Specifications 72 Datasheet 7.5.3.1 PCI Express* DC Specifications The processor DC specifications for the PCI Express* are available in the PCI Express Base Specification, Revision 3.0. This document will pro vide only the processor exceptions to the PCI Express Base Specification , R evision 3.
Datasheet 73 Processor Land Listing 8 Processor Land Listing This chapter provides the processor land lists. T able 8-1 is a listing of all processor lands ordered alphabetically by land name. T able 8-2 is a listing of all processor lands ordered by land number .
74 Datasheet Processor Land Listing Table 8-1. Land List by Land Name (Sheet 1 of 42) Land Name Land No. Buffer Type Direction BCLK0_DN CM44 CMOS I BCLK0_DP CN43 CMOS I BCLK1_DN BA45 CMOS I BCLK1_DP A.
Datasheet 75 Processor Land Listing DDR0_DQ[31] CF10 SSTL I/O DDR0_DQ[32] CE31 SSTL I/O DDR0_DQ[33] CC31 SSTL I/O DDR0_DQ[34] CE35 SSTL I/O DDR0_DQ[35] CC35 SSTL I/O DDR0_DQ[36] CD30 SSTL I/O DDR0_DQ[.
76 Datasheet Processor Land Listing DDR0_ODT[2] CH28 SSTL O DDR0_ODT[3] CF28 SSTL O DDR0_ODT[4] CB24 SSTL O DDR0_ODT[5] CC27 SSTL O DDR0_PAR_ERR_N CC21 SSTL I DDR0_RAS_N CE29 SSTL O DDR0_WE_N CN29 SST.
Datasheet 77 Processor Land Listing DDR1_DQ[50] CR41 SSTL I/O DDR1_DQ[51] CU41 SSTL I/O DDR1_DQ[52] CT36 SSTL I/O DDR1_DQ[53] CV36 SSTL I/O DDR1_DQ[54] CT40 SSTL I/O DDR1_DQ[55] CV40 SSTL I/O DDR1_DQ[.
78 Datasheet Processor Land Listing DDR2_CLK_DN[2] W21 SSTL O DDR2_CLK_DN[3] W23 SSTL O DDR2_CLK_DP[0] AB24 SSTL O DDR2_CLK_DP[1] AB22 SSTL O DDR2_CLK_DP[2] AA21 SSTL O DDR2_CLK_DP[3] AA23 SSTL O DDR2.
Datasheet 79 Processor Land Listing DDR2_DQS_DN[08] AB28 SSTL I/O DDR2_DQS_DN[09] W39 SSTL I/O DDR2_DQS_DN[10] AC39 SSTL I/O DDR2_DQS_DN[11] T32 SSTL I/O DDR2_DQS_DN[12] AB34 SSTL I/O DDR2_DQS_DN[13] .
80 Datasheet Processor Land Listing DDR3_DQ[03] E37 SSTL I/O DDR3_DQ[04] F40 SSTL I/O DDR3_DQ[05] D40 SSTL I/O DDR3_DQ[06] F38 SSTL I/O DDR3_DQ[07] A37 SSTL I/O DDR3_DQ[08] N39 SSTL I/O DDR3_DQ[09] L3.
Datasheet 81 Processor Land Listing DDR3_DQS_DP[09] E39 SSTL I/O DDR3_DQS_DP[10] M38 SSTL I/O DDR3_DQS_DP[11] D34 SSTL I/O DDR3_DQS_DP[12] N31 SSTL I/O DDR3_DQS_DP[13] E11 SSTL I/O DDR3_DQS_DP[14] K12.
82 Datasheet Processor Land Listing PE1B_RX_DP[5] K54 PCIEX3 I PE1B_RX_DP[6] J57 PCIEX3 I PE1B_RX_DP[7] K56 PCIEX3 I PE1B_TX_DN[4] K46 PCIEX3 O PE1B_TX_DN[5] L47 PCIEX3 O PE1B_TX_DN[6] K48 PCIEX3 O PE.
Datasheet 83 Processor Land Listing PE3A_TX_DP[1] J51 PCIEX3 O PE3A_TX_DP[2] R47 PCIEX3 O PE3A_TX_DP[3] P48 PCIEX3 O PE3B_RX_DN[4] AB50 PCIEX3 I PE3B_RX_DN[5] AB52 PCIEX3 I PE3B_RX_DN[6] AC53 PCIEX3 I.
84 Datasheet Processor Land Listing RSVD BM44 RSVD BM46 RSVD BN47 RSVD BP44 RSVD BP46 RSVD BR43 RSVD BR47 RSVD BT44 RSVD BU43 RSVD BY46 RSVD C53 RSVD CA45 RSVD CD44 RSVD CE43 RSVD CF44 RSVD CG11 RSVD .
Datasheet 85 Processor Land Listing VCC AN3 PWR VCC AN5 PWR VCC AN7 PWR VCC AN9 PWR VCC AP10 PWR VCC AP12 PWR VCC AP14 PWR VCC AP16 PWR VCC AP2 PWR VCC AP4 PWR VCC AP6 PWR VCC AP8 PWR VCC AU1 PWR VCC .
86 Datasheet Processor Land Listing VCC BG9 PWR VCC BH10 PWR VCC BH12 PWR VCC BH14 PWR VCC BH16 PWR VCC BH2 PWR VCC BH4 PWR VCC BH6 PWR VCC BH8 PWR VCC BJ1 PWR VCC BJ11 PWR VCC BJ13 PWR VCC BJ15 PWR V.
Datasheet 87 Processor Land Listing VCC_SENSE BW3 O VCCD_01 CD20 PWR VCCD_01 CD22 PWR VCCD_01 CD24 PWR VCCD_01 CD26 PWR VCCD_01 CD28 PWR VCCD_01 CJ19 PWR VCCD_01 CJ21 PWR VCCD_01 CJ23 PWR VCCD_01 CJ25.
88 Datasheet Processor Land Listing VSS A7 GND VSS AA11 GND VSS AA29 GND VSS AA3 GND VSS AA31 GND VSS AA39 GND VSS AA5 GND VSS AA55 GND VSS AA9 GND VSS AB14 GND VSS AB36 GND VSS AB42 GND VSS AB6 GND V.
Datasheet 89 Processor Land Listing VSS A T12 GND VSS A T14 GND VSS A T16 GND VSS AT2 GND VSS AT4 GND VSS A T46 GND VSS A T52 GND VSS AT6 GND VSS AT8 GND VSS AU45 GND VSS AU47 GND VSS AU49 GND VSS AU5.
90 Datasheet Processor Land Listing VSS BR57 GND VSS BT46 GND VSS BT48 GND VSS BT50 GND VSS BT52 GND VSS BT54 GND VSS BT56 GND VSS BU45 GND VSS BU51 GND VSS BW1 GND VSS BW11 GND VSS BW13 GND VSS BW15 .
Datasheet 91 Processor Land Listing VSS CH48 GND VSS CH50 GND VSS CH52 GND VSS CH54 GND VSS CH6 GND VSS CJ11 GND VSS CJ17 GND VSS CJ29 GND VSS CJ3 GND VSS CJ43 GND VSS CJ45 GND VSS CJ47 GND VSS CJ51 G.
92 Datasheet Processor Land Listing VSS CW35 GND VSS CW37 GND VSS CW39 GND VSS CW5 GND VSS CW51 GND VSS CW53 GND VSS CW55 GND VSS CW57 GND VSS CW7 GND VSS CY10 GND VSS CY12 GND VSS CY16 GND VSS CY2 GN.
Datasheet 93 Processor Land Listing VSS H34 GND VSS H38 GND VSS H40 GND VSS H52 GND VSS H54 GND VSS H8 GND VSS J11 GND VSS J27 GND VSS J31 GND VSS J33 GND VSS J39 GND VSS J41 GND VSS J5 GND VSS J55 GN.
94 Datasheet Processor Land Listing VSS W51 GND VSS W53 GND VSS W9 GND VSS Y10 GND VSS Y12 GND VSS Y28 GND VSS Y30 GND VSS Y32 GND VSS Y36 GND VSS Y38 GND VSS Y40 GND VSS Y42 GND VSS Y56 GND VSS_VCC_S.
Datasheet 95 Processor Land Listing Table 8-2. Land List by Land Number (Sheet 1 of 42) Land No. Land Name Buffer Type Direction A11 DDR3_DQ[33] SSTL I/O A13 DDR3_MA[13] SSTL O A15 DDR3_WE_N SSTL O A1.
96 Datasheet Processor Land Listing AC41 DDR2_DQ[12] SSTL I/O AC43 PE3D_TX_DP[14] PCIEX3 O AC45 PE3D_TX_DN[12] PCIEX3 O AC47 PE3C_TX_DN[9] PCIEX3 O AC49 PE3A_RX_DN[3] PCIEX3 I AC5 DDR2_DQS_DP[16] SSTL.
Datasheet 97 Processor Land Listing AF54 VSS GND AF56 VSS GND AF58 PE2B_RX_DN[7] PCIEX3 I AF6 VSS GND AF8 DDR2_DQ[42] SSTL I/O AG1 VSS GND AG11 DDR2_DQ[34] SSTL I/O AG13 VSA_SENSE O AG15 VSA PWR AG17 .
98 Datasheet Processor Land Listing AL15 VCC PWR AL17 VCC PWR AL3 VCC PWR AL43 VSS GND AL45 VSS GND AL49 VSS GND AL5 VCC PWR AL51 VSS GND AL53 VSS GND AL55 RSVD AL57 PE2C_RX_DN[10] PCIEX3 I AL7 VCC PW.
Datasheet 99 Processor Land Listing A T44 BPM_N[1] ODCMOS I/O A T46 VSS GND A T48 BIST_ENABLE CMOS I A T52 VSS GND A T54 PE2B_TX_DN[7] PCIEX3 O A T56 PE2D_RX_DN[13] PCIEX3 I A T58 PE2D_RX_DP[12] PCIEX.
100 Datasheet Processor Land Listing B38 DDR3_DQS_DN[00] SSTL I/O B40 DDR3_DQ[00] SSTL I/O B42 DMI_TX_DP[0] PCIEX O B44 DMI_TX_DP[2] PCIEX O B46 RSVD B48 DMI_RX_DP[1] PCIEX I B50 DMI_RX_DP[3] PCIEX I .
Datasheet 101 Processor Land Listing BE51 VSS GND BE7 VCC PWR BE9 VCC PWR BF10 VCC PWR BF12 VCC PWR BF14 VCC PWR BF16 VCC PWR BF2 VCC PWR BF4 VCC PWR BF42 VSS GND BF44 VSS GND BF46 RSVD BF48 PEHPSDA O.
102 Datasheet Processor Land Listing BM16 VSS GND BM2 VSS GND BM4 VSS GND BM42 VTTD PWR BM44 RSVD BM46 RSVD BM6 VSS GND BM8 VSS GND BN1 VCC PWR BN11 VCC PWR BN13 VCC PWR BN15 VCC PWR BN17 VCC PWR BN3 .
Datasheet 103 Processor Land Listing BW11 VSS GND BW13 VSS GND BW15 VSS GND BW17 VSS GND BW3 VCC_SENSE O BW43 TDI CMOS I BW5 VSS GND BW7 VSS GND BW9 DDR0_DQ[28] SSTL I/O BY10 DDR0_DQ[24] SSTL I/O BY12.
104 Datasheet Processor Land Listing CB2 DDR0_DQ[08] SSTL I/O CB20 DDR01_RCOMP[2] Analog I CB22 MEM_HOT_C01_N ODCMOS I/O CB24 DDR0_ODT[4] SSTL O CB26 DDR0_CS_N[6] SSTL O CB28 DDR0_CS_N[3] SSTL O CB30 .
Datasheet 105 Processor Land Listing CF12 VSS GND CF14 VSS GND CF16 DDR0_DQS_DN[17] SSTL I/O CF20 DDR0_CKE[4] SSTL O CF22 DDR0_CLK_DN[3] SSTL O CF24 DDR0_CLK_DN[0] SSTL O CF26 DDR0_CS_N[5] SSTL O CF28.
106 Datasheet Processor Land Listing CJ5 DDR0_DQ[11] SSTL I/O CJ51 VSS GND CJ7 DDR0_DQ[06] SSTL I/O CJ9 VSS GND CK10 VSS GND CK12 DDR0_DQ[16] SSTL I/O CK14 DDR0_DQS_DP[02] SSTL I/O CK16 DDR0_DQ[18] SS.
Datasheet 107 Processor Land Listing CN57 VSS GND CN7 VSS GND CN9 VSS GND CP10 DDR1_DQ[19] SSTL I/O CP12 VSS GND CP14 DDR1_DQS_DN[12] SSTL I/O CP16 VSS GND CP18 DDR0_CKE[3] SSTL O CP2 DDR1_DQ[01] SSTL.
108 Datasheet Processor Land Listing CU27 DDR1_ODT[4] SSTL O CU29 DDR1_DQ[36] SSTL I/O CU3 VSS GND CU31 DDR1_DQS_DP[13] SSTL I/O CU33 DDR1_DQ[38] SSTL I/O CU35 VSS GND CU37 DDR1_DQ[49] SSTL I/O CU39 D.
Datasheet 109 Processor Land Listing D10 DDR3_DQS_DP[04] SSTL I/O D12 DDR3_DQ[32] SSTL I/O D14 DDR3_ODT[4] SSTL O D16 DDR3_CS_N[8] SSTL O D18 DDR3_MA[10] SSTL O D2 VSS GND D20 DDR3_MA[04] SSTL O D22 D.
110 Datasheet Processor Land Listing DC9 DDR1_DQS_DN[01] SSTL I/O DD10 VSS GND DD12 VSS GND DD14 VSS GND DD18 VCCD_01 PWR DD20 VCCD_01 PWR DD22 VCCD_01 PWR DD24 VCCD_01 PWR DD26 VCCD_01 PWR DD32 DDR1_.
Datasheet 111 Processor Land Listing F28 DDR3_DQS_DP[17] SSTL I/O F32 DDR3_DQ[19] SSTL I/O F34 DDR3_DQ[17] SSTL I/O F36 VSS GND F38 DDR3_DQ[06] SSTL I/O F4 DDR3_DQ[60] SSTL I/O F40 DDR3_DQ[04] SSTL I/.
112 Datasheet Processor Land Listing J37 DDR3_DQS_DP[01] SSTL I/O J39 VSS GND J41 VSS GND J43 PE1A_TX_DP[1] PCIEX3 O J45 PE1A_TX_DP[3] PCIEX3 O J47 PE1B_TX_DP[5] PCIEX3 O J49 PE1B_TX_DP[7] PCIEX3 O J5.
Datasheet 113 Processor Land Listing M38 DDR3_DQS_DP[10] SSTL I/O M4 DDR3_DQS_DP[07] SSTL I/O M40 DDR3_DQ[12] SSTL I/O M42 VSS GND M44 VSS GND M46 VSS GND M48 RSVD M50 VSS GND M52 VSS GND M54 PE1B_RX_.
114 Datasheet Processor Land Listing R49 PE3B_TX_DP[7] PCIEX3 O R5 VSS GND R51 PE3B_TX_DP[5] PCIEX3 O R53 PRDY_N CMOS O R55 VSS GND R7 VSS GND R9 DDR2_DQ[54] SSTL I/O T10 DDR2_DQ[50] SSTL I/O T12 DDR2.
Datasheet 115 Processor Land Listing § W11 DDR2_DQS_DP[06] SSTL I/O W13 VSS GND W15 RSVD W17 DDR2_CS_N[8] SSTL O W19 DDR2_ODT[1] SSTL O W21 DDR2_CLK_DN[2] SSTL O W23 DDR2_CLK_DN[3] SSTL O W25 DDR2_MA.
Package Mechanical Specifications 116 Datasheet 9 Package Mechanical Specifications The processor is in a Flip-Chip Land Grid Array (FCL GA12) package that interfaces with the baseboard using an LGA2011-0 socket. The package consists of a processor mounted on a substrate land-carrier .
Datasheet 117 Boxed Processor Specifications 10 Boxed Processor Specifications 10.1 Introduction Intel boxed processors are intended for system integr ators who build systems from components available through distribution channels.
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