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Reference Number: 32677 0 Mobile 3rd Generation Intel ® Core™ Processor Family Specification Update September 2013 Revision 015.
2 Specification Update INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WI TH INTEL PRODUCTS. NO LICENSE, EXP RESS OR IMPLIED, BY ESTOPPEL OR OTHER WISE, TO ANY INTELLECTUAL PROPERTY RI GHTS IS GRANTED BY THIS DOCUMENT .
Contents Specification Update 3 Contents Revision History ................ ............ ................. ............. ............ ................. ............ ............ 5 Preface .................. ............. ................ ............. .
Contents 4 Specification Update.
Specification Update 5 Revision History Revision Description Date 001 • Initial Release. April 2012 002 • Added Errata BU69–BU85 • Updated Proc essor Identi fication T able May 2012 003 • Ad.
6 Specification Update Preface This document is an update to the specifications contained in the Affected Documents table below . This document is a compilation of device and documentation errata, specification clarifications and changes.
Specification Update 7 Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and softw are designed to b e used with any giv en stepping must assume that all errata documented for that stepping are present on all devices.
8 Specification Update Summary Tables of Changes The following tables indicate the errata , specification changes, specification clarifications, or documentation changes which apply to the processor .
Specification Update 9 BU7 XX N o F i x General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted BU8 XX N o F i x LBR, BTS, BTM May Report a Wrong Address when an Excepti.
10 Specification Update BU34 XX N o F i x Processor May Fail to Acknowledge a TL P Request BU35 XX N o F i x An Unexpected PMI May Occur After Writing a Large V alue to IA32_FIXED_CT R2 BU36 XX N o F .
Specification Update 11 BU63 XX N o F i x PCIe* Root-port Initiated Compliance S tat e T r ansmitter Equalization Settings May be Incorrect BU64 XX N o F i x PCIe* Controller May Incorrectly Log Error.
12 Specification Update BU94 X X No Fix Instruction Fetches Page-T able Walks Ma y be Made S peculatively to Uncacheable Memory BU95 X X No Fix The Processor May Not Properly Execute Cod e Modified Us.
Specification Update 13 § §.
14 Specification Update Identification Information Component Identification us ing Programmin g Interface The processor stepping can be identified by the following register contents: Notes: 1.
Specification Update 15 Component Marking Information The processor stepping can be identified by the following component markings. Table 1. Processor Identif ication (Sheet 1 of 6) Number Processor Number Stepping Processor Signature Core Frequency (GHz) / DDR3 (MH z) / Processor Graphics Frequency Max Intel ® Turbo Boost Technology 2.
16 Specification Update SR0MX i5-3320M L -1 000306 A9h 2.6 / 1600 / 650 4 core: 0 3 core: 0 2 core: 3.1 1 core: 3.3 3 2,3,4,5,6 SR0MY i5-3320M L -1 000306A9h 2.6 / 16 00 / 650 4 core: 0 3 core: 0 2 core: 3.1 1 core: 3.3 3 2,3,4,5,6 SR0MZ i5-3210M L -1 000306 A9h 2.
Specification Update 17 SR0X7 i5-3380M L -1 00 0306A9h 2.9 /1600 /650 2 core: 3.4 1 core: 3.6 3 2,3,4,5,6 SR0X9 i5-3380M L -1 00 0306A9h 2.9 /1600 /650 2 core: 3.4 1 core: 3.6 3 2,3,4,5,6 SR0XA i5-3340M L -1 000306A9h 2.7 / 1600 /650 2 core: 3.2 1 core: 3.
18 Specification Update SR0ZN i5-3439Y L-1 000306A9h 1.5 /1600/ 350 2 core: N/A 1 core: 2.3 3 2,3,4,5,6 SR12S i5-3339Y L-1 000306A9h 1.5 /1600/ 350 2 core: N/A 1 core: 2.2 3 2,4,5,6 SR0ZQ i5-3339Y L-1 000306A9h 1.5 /1600/ 350 2 cor e: N/A 1 core: 2.2 3 2,4,5,6 SR12P i3-3229Y L-1 000306A9h 1.
Specification Update 19 SR0ND i7-3612QE E-1 00306A9h 2.3 / 1600/ 650 3/4 Core: 2.8 2 Core: 3.0 1 Core: 3.1 6 2,3,4,5,6,8 SR0T5 i 7-3555LE L-1 00306A9h 2.5 / 1600/ 550 4 Core: 0 3 Core: 0 2 Core: 3.0 1 Core: 3.2 4 2,3,4,5,6,8 SR0T6 i7-3517UE L-1 00306A9h 1.
20 Specification Update Notes: 1. This column indic ates max imum I ntel ® T urbo Boost T echnology 2.0 fr equency (GHz) for 4,3, 2 or 1 cores active respectiv ely . 2. Intel ® Hyper- Threading T echnology enabled. 3. Intel ® T rusted Ex ecution T echnology (Intel ® TXT) enabled.
Specification Update 21 Errata BU1. The Processor May Report a #TS Instead of a #GP Fault Problem: A jump to a busy TSS (T ask -State Segment) ma y cause a #TS (inv alid TSS ex ception) instead of a #GP f ault (gener al protection exception). Implication: Operation systems that access a busy T SS may get in valid T SS fault instead of a #GP fault.
22 Specification Update BU4. Performance Monitor SSE Retired Instructions May Return Incorrect Values Problem: Performance Monitoring counter SIMD_INST_RETIRED (Event: C 7H) is used to tr ack retired SSE instructions. Due to this erratum, the processor may also count other types of instructions resulting in higher than expected values.
Specification Update 23 BU8. LBR, BTS, BTM May Repor t a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode Problem: An exception/interrupt ev ent should be transparent to the LBR (Last Branch R ecord), B T S (Branch T race Store) and B TM (Branch T r ace Message) mechanisms.
24 Specification Update BU11. EFLAGS Discrepancy o n Page Faults and on EPT-Induce d VM Exits after a Translation Change Problem: This erratum is regarding the case where pa ging structu res are modifi ed to change a linear address from writable to non-writable without software perfo rming an appropriate TLB inv alidation.
Specification Update 25 BU13. MCi_Status Overflow Bit May Be In correctly Set on a Single Instance of a DTLB Error Problem: A single Data T ranslation Look Aside Buffer (D TLB) error can incorrectly set the Overflow (bit [62]) in the MCi_Status regist er .
26 Specification Update BU17. PEBS Record not Upda ted when in Probe Mode Problem: When a performance monitoring counter is configured for PEBS (Precise Ev e nt Based Sampling), overflows of the counter can result in stor age of a PEBS record in the PEBS buffer .
Specification Update 27 BU21. #GP on Segment Selector Desc riptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code Problem: During a #GP (General Protection Exception), the processor pushes an error code on to the exception handler’s stack.
28 Specification Update BU24. Changing the M emory Type for an In-Use Page Transla t ion Ma y Lead to Memory-Ordering Violations Problem: Under complex microarchitectural conditions, if softw are chan.
Specification Update 29 BU27. Fault Not Reported When Se tting Reserved Bits of Intel ® VT-d Queued Invalidation Descriptors Problem: Reserv ed bits in the Queued Inv alidation descriptors of Intel V.
30 Specification Update BU30. Spurious Inte rrupts May be Generated From the Intel ® VT-d Remap Engine Problem: If software clears the F (F ault) bit 127 of the F ault Recording Register (FRCD_REG at.
Specification Update 31 BU34. Processor May Fail to Acknowledge a TLP Request Problem: When a PCIe root port’s receiver is in R e ceiver L0s power state and the port initiates a Re covery event, it will issue T raining Sets to the link partner . The link partner will respond by initiating an L0s exit sequence.
32 Specification Update BU38. PerfMon Overflow Statu s Ca n Not be Cleared After C ertain Conditions Have Occurred Problem: Under very specific timing conditions, if software tries to disable a P erfMon counter through MSR IA32_PERF_GLOBAL_CTRL (0x38F) or through the per-counter event- select (e.
Specification Update 33 BU41. PCI Express * Differential Peak-Peak Tx Voltage Swing May Violate the Specification Problem: Under certain conditions, including extrem e voltage and temperature, the peak -peak voltage may be higher than the specification.
34 Specification Update BU44. IA32_FEATURE_CON TR OL MSR May be Uninitialized on a Cold Reset Problem: IA32_FEA TURE_CONTROL MSR (3Ah) may have random v alues after RESET (including the reserved and Lock bits), and th e read-mod ify -write of the reserved bits and/or the Lock bit being incorrectly set may cause an unexpected GP fault.
Specification Update 35 BU48. 64-bit REP MOVSB/STOSB May Clea r The Upper 32-bits of RCX, RDI And RSI Before Any Data is Transferred Problem: If a REP MOVSB/STOSB is executed in 64-bit mode with an ad.
36 Specification Update BU52. Instructions Retired Event Ma y Over Count Execution of IRET Instructions Problem: Under certain conditions, the performance monitoring event Instructions Retired (Event C0H, Unmask 00H) may over count the ex ecution of IRET instruction.
Specification Update 37 BU56. PCI Express* Gen3 Receiver Re turn Loss May Exce ed Specifications Problem: The PCIe Base Specification includes a graph that sets requirements for maximum receiver return loss v ersus frequency .
38 Specification Update BU59. PCIe* May Associate Lanes That Are Not Part of Initial Link Training to L0 During Upconfiguration Problem: The processor should not associate any lane s that were not part o f the initial link training in subsequ ent upconfiguration requests from an endpoint.
Specification Update 39 BU63. PCIe* Root-port Initiated Comp liance State Transmitter Equalization Settings May be Incorrect Problem: If the processor is directed to enter PCIe P olling.
40 Specification Update BU67. MSR_PKG_Cx_RESIDENCY MS Rs May Not be Accurate Problem: If the processor is in a package C-state fo r an extended period of time (greater than 40 seconds) with no wak e events, the value in the MSR_PKG_C{2,3,6,7}_RESIDENCY MSRs (60D H and 3F8H–3F AH) will not be accurate.
Specification Update 41 BU72. PCIe* Root Port May No t Initiate Link Speed Change Problem: The PCIe Base specification requires the up stream component to maintain the PCIe link at the target link speed or the highest sp eed supported by both components on the link, whichever is lower .
42 Specification Update BU75. VM Exits Due to “NMI-Window Exit ing” May Not Occur Following a VM Entry to the Shutdown State Problem: If VM entry is made with the “virtual NM Is” and “NMI -w.
Specification Update 43 BU78. PCIe* Controller May Not Enter Loopback Problem: The PCIe controller is expected to enter loo pback if any lane in the link receives two consecutive TS1 ordered sets with the Loopba ck bit set.
44 Specification Update BU82. PCIe* Link May Fail Li nk Width Upconfiguration Problem: The processor supports PCIe Hardware Au tonomous Width management, in which a PCIe link can autonomously vary its width. Du e to this erratum, a link that performs a speed change while in a reduced width may no longer be able to return to a wider link width.
Specification Update 45 BU86. REP MOVSB May Incorrectly Update ECX, ESI, and EDI Problem: Under certain conditions, if the ex ecution of a REP MOVSB instruction is interrupted, the values of ECX, ESI and EDI may contain v alues that represent a later point in the execution of the instruction than the actual interruption point.
46 Specification Update BU89. VEX.L is Not Ignored with VCVT*2SI Instructions Problem: The VEX.L bit should be ignored for the VCVTSS2SI, VCVTSD2SI, VCVTTS S2SI, and VCVT TSD2SI instructions, howev er due to this err atum the VEX.L bi t is not ignored and will cause a #UD.
Specification Update 47 BU93. During Package Power States Repeated PC Ie* and/or DMI L1 Transitions May Cause a System Hang Problem: Under a complex set of internal conditio ns and operating temper at.
48 Specification Update BU97. VM Exit s Due to GETSEC May Save an Inco rrect V alue for “Blocking by STI” in the Context of Probe-Mode Redirect ion Problem: The GETSEC i nstruction caus es a VM exit wh en ex ecuted in VMX n on-root operation.
Specification Update 49 corresponding counter with the same number on the physical core’ s other thread rather than the thread experiencing the ev ent. Proc essors with SMT disabled in BIOS are not affected by this err atum. The list of affected memory at-retirement ev ents is as follows: MEM_UOP_RETIRED.
50 Specification Update BU104. Processor May Livelock Duri ng On D emand Clock Modulation Problem: The processor may livelock when (1) a processor thread has enabled on demand clock modulation via bit 4 of the IA32_CLOCK_MODULA TION MSR (19AH) and the clock modulation duty cycle is set to 12.
Specification Update 51 this field. (The processor correctly stores the guest-ph ysical address of the pagi ng- structure entry into the “gue st-ph ysical address” field in the VMC S.) Implication: Software may not be easily able to determin e the page offset of the original memory access that caused the EPT violation.
52 Specification Update processor micro-architectur al eve nts may cause an incorrect ad dress translation or machine check on either logical processor . Implication: This erratum may result in unexpected faul ts, an u ncorrectable TLB error logged in IA32_MCi_ST A TUS.
Specification Update 53 Specification Changes The Specification Changes listed in this section apply to the following documents: •I n t e l ® 64 and IA-32 Architectures Software Developer’s Manua.
54 Specification Update Specification Clarifications The Specification Clarifications listed in this section may apply to the following documents: •I n t e l ® 64 and IA-32 Architectures Software D.
Specification Update 55 Documentation Changes The Documentation Changes listed in this section apply to the following documents: •I n t e l ® 64 and IA-32 Architectures Software Developer’s Manua.
56 Specification Update § § DisplayFamily_Displa yModel DisplayFamily_Display Model DisplayFamily_Displa yModel DisplayFamily_Display Model 0F_xx 06_1C 06_1A 06_1E 06_1F 06_25 06_26 06_27 06_2C 06_2.
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