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Intel ® 82854 Graphics Memory Controller Hub (GMCH) Datasheet Revision 2.0 June 2005 Order Number: D15343-00 3.
2 D15343-003 INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER WISE, T O ANY INTELLECTUAL PROPERTY RI GH TS IS GRANTED BY THIS DOCUMENT .
D15343-003 3 Contents Contents 1.0 Introduction ................ ............. ................ ............. ................ ............. ................ ......... .......... .......... 11 1.1 Overview ......... ................ ............. ....
4 D15343-003 Intel ® 82854 Graphic s Memory Controller Hub (GMCH) 4.8.4 PCI Status Register ..... ................ ............. ................ ................ ............. ................ 53 4.8.5 RID – Register Identification ........... ...
D15343-003 5 Contents 4.10.9 SVID – Subsystem Vendor Identific ation Register....... ................ ................ .......... 97 4.10.10 ID – Subsystem Identifi cation Register ..... ................ ............. ............. ...............
6 D15343-003 Intel ® 82854 Graphic s Memory Controller Hub (GMCH) 6.4.1 3D/2D Instruction Processing ................... ................ ................ ............. .............. 126 6.4.2 3D Engine ... ............. ................ ...........
D15343-003 7 Contents Figures 1 Intel® 854 Chipset system block diagram (Native Graphic mode) ................... .................... ...... 16 2 Configuration Address Register ........................ .......... ............. ................ .....
8 D15343-003 Intel ® 82854 Graphic s Memory Controller Hub (GMCH) 29 Relation of DBI B its to Data Bits ................ ............. ................ ............. ................ ............. ..... ... 123 30 Data Bytes on DDR DIMM Us ed for Programming DRAM Registers .
D15343-003 9 Contents Revision History § § Date Revision Description March 2005 1.0 Initial release of this document. June 2005 2.0 Add support for Genuine Intel® Processor at 1.
10 D15343-003 Intel ® 82854 Graphic s Memory Controller Hub (GMCH).
Introduction D15343-003 11 1.0 Introduction This documen t is the data sheet for the Intel ® 82854 Graphics Memory Controller Hub (GMCH). 1.1 Overview The Intel ® 854 chipset is a combinatio n of the Intel ® 82854 Graphics M emory Controller H ub (GMCH) (Graphics Memory Controller Hub) and ICH4-M (I/O Controller Hub).
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 12 D15343-003 System Interrupt s • Supports Intel 8259 and front side bus interrupt delivery mechanism • Supports interrupts sign aled as upstr.
Introduction D15343-003 13 Display • Analog display sup port — 350-MHz integrated 24-bit RAMDAC that can drive a standa rd progressi ve scan analog monitor with pixel resolution up to 160 0x1200 a.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 14 D15343-003 • 3D graphics engine — 3D setup and render engine — Enhanced Hardware Binning Instruction Set su pported — Zone rendering —.
Introduction D15343-003 15 — Dithering — Line and full-scene anti-aliasing — 16- and 24- bi t Z buffer ing — 16- and 24-bit W buffering — 8-bit Stencil buffering — Double and triple render.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 16 D15343-003 Package 732-pin Micro-FCBGA (37 .5 x 37.5 mm) Figure 1. Intel® 854 Chip set system block diagram (Native Graphic mode ) In te l ® C.
Introduction D15343-003 17 1.2 T erminology T able 1. T erms and Descriptions T erm Description AG TL+ Advanced Gunning Transceiver Logic + (AG TL+) bus BLI Backlight Inverter Core The internal base l.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 18 D15343-003 Intel 82801DBM ICH4-M The component contains the prim ary PCI interface, LPC interface, USB 2.0, A T A-100 , AC’97, and other I/O functions. It communicates with the Intel ® 82854 GMCH over a proprietary interconnect ca lled the Hub interface.
Introduction D15343-003 19 1.3 Reference Document s T able 2. Reference Docume nt s Document Location Intel® Celeron® M Processor Datasheet http://www .intel.com/design/mobile/datashts/300302.htm Ultra Low V oltage Intel(R) Celeron(R) M Processor at 600 MHz Addendum to the Intel(R) Celeron(R) M Processor Datasheet http://developer .
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 20 D15343-003.
Intel ® 82854 GMCH Overview D15343-003 21 2.0 Intel ® 82854 GMCH Overview 2.1 System Architecture The Intel ® 82854 GMCH includes a processor inte rface, DDR SDRAM interface, display interface, and Hub interface.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 22 D15343-003 2.2 Processor Host Interface The Intel ® 82854 GMCH supports the In tel Celeron M Processor, and Genuine Intel Processor . Key features of the front side bus (FSB) are: • Support for a 400-MHz system bus frequency .
Intel ® 82854 GMCH Overview D15343-003 23 The GMCH system memory architect ure is optimized to maintain open pages (up to 16-KB page size) across multiple rows. As a result, up to 16 pages across four ro ws is supported. T o complement this, the GMCH will tend to keep pages open within ro ws, or will only close a single bank on a page miss.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 24 D15343-003 2.6 Hub Interface A proprietary interconnect connects the GMCH to the ICH4-M. All communication between the GMCH and the ICH4-M occurs over the Hub inte rface 1.5. The Hub inte rface runs at 66 MHz (266-MB/s).
Intel ® 82854 GMCH Overview D15343-003 25 2.8 GMCH Clocking The GMCH has the fol lowing clock inpu t/output pin s: • 400-MHz, spread spectrum, low v oltage differential BCLK, BCLK# for front side bus (FSB) • 66-MHz, 3.3-V GCLKIN for Hub interface buf fers • Six pairs of differential output clocks (SC K[5 :0], SCK [5:0]#), 200/266 MHz, 2.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 26 D15343-003 2.9 System Interrupt s The GMCH supports both the legacy Intel 8259 Programm able Interrupt deli very mechanism and the Intel Celeron M processor FSB interrup t delivery mechanism . The serial APIC Interrupt mechanism is not supported .
Signal Description D15343-003 27 3.0 Signal Description This section describes t he Intel ® 82854 GMCH signals. These sign als are arranged in functi onal groups according to their associated interface. The following notatio ns are used to describe the signal type.
Intel ® 854 Graphics Memory Co ntroller Hub (GMCH) 28 D15343-003 3.1 Host Interface Signals T able 5. Host Interface Sig nal De scriptions Signal Name T y pe Description ADS# I/O AG TL+ Ad dress Strobe: The system bus owner asserts ADS# to indicate the first of two cycles of a request phase.
Signal Description D15343-003 29 DRDY# I/O AG TL+ Data Ready: Asserted for each cycle that data is transferred. HA[31:3]# I/O AG TL+ Host Address Bus: HA[31:3]# connects to the CPU address bus. During processor cycles the HA[31:3]# are inputs. The GMCH drives HA[31:3]# during snoop cycles on behalf of H ub interface.
Intel ® 854 Graphics Memory Co ntroller Hub (GMCH) 30 D15343-003 RS[2:0]# O AG TL+ Resp onse St atus: Indicates the type of resp onse according to the following the table: RS[2:0]# Response typ e 000.
Signal Description D15343-003 31 3.2 DDR SDRAM Interface T able 6. DDR SDRAM Interface Descriptions Signal Name T ype Description SCS[3:0]# O SSTL_2 Chip Select: These pins select the particular DDR SDRAM components during the active state. NOTE: There is one SCS# per DDR-SDRAM Physical DDR DIMM device row .
Intel ® 854 Graphics Memory Co ntroller Hub (GMCH) 32 D15343-003 3.3 Hub Interface Signals T able 7. Hub Interface Signals SMAB[5,4,2,1] O SSTL_2 Memory Address Copies: These signals are identical to SMA[5,4,2 ,1] and are used to reduce loading for selectiv e CPC(clock-per-command).
Signal Description D15343-003 33 3.4 Clocks T able 8. Cloc k Signals Signal Name T ype Description Host Processor Clocking BCLK BCLK# I CMOS Differential Host Clock I n: These pins receive a buffered host clock from the external clock synthesizer .
Intel ® 854 Graphics Memory Co ntroller Hub (GMCH) 34 D15343-003 DPMS I DVO Display Power Management Signaling: This signal is used only in mobile systems to act as the DREFCLK in certain power management states (i.e., Display Power Down Mode); DPMS Clock is used to refresh video during S1-M.
Signal Description D15343-003 35 3.5 Internal Graphics Display Signals The IGD has support fo r DVOB/C interfaces, and an Analog CR T port.Digital V ideo Output B (DVOB) Port.
Intel ® 854 Graphics Memory Co ntroller Hub (GMCH) 36 D15343-003 3.5.2 Digit al Video Ou tput C (DVOC) Port T able 10. Digit al Vi deo Output C (DVOC) Port Signal Descriptions Name T ype Descriptio n.
Signal Description D15343-003 37 T able 1 1. DVOB and DVOC Port Common Signal Des criptions 3.5.3 Analog CRT Display T able 12. Analog CRT Display Signal Description s Name T ype De scription DVOBCINTR# I DVO DVOBC Interrupt : This pin is used to signal an interrupt, typically used to indicate a hot plug or unplug of a digital display .
Intel ® 854 Graphics Memory Co ntroller Hub (GMCH) 38 D15343-003 3.5.4 General Purpose Input/Output Signals T able 13. GPIO Signal Descriptions GPIO I/F T otal T ype Comments RSTIN# I CMOS Reset: Primary Reset, Connected to PCIRST# of ICH4-M. PWROK I CMOS Pow e r O K : Indicates that power to GMCH is stable.
Signal Description D15343-003 39 3.6 V olt age References, PLL Power T able 14. V olt age References, PLL Power Signal Name T ype De scription Host Processor HXRCOMP Analog Host RCOMP: Used to calibrate the Host AG TL+ I/O buffers. HYRCOMP Analog Host RCOMP: Used to calibrate the Host AG TL+ I/O buffers.
Intel ® 854 Graphics Memory Co ntroller Hub (GMCH) 40 D15343-003 Hub Interface HLRCOMP Analog Hub Interface RCOMP : This signal is co nnected to a reference re sistor in order to calibrate the buffers. PSWING Analog RCOMP reference volt age : This is connected to the RCOMP buffer differential amplifier and is used to calibrate the buffers.
Register Descriptio n D15343-003 41 4.0 Register Description 4.1 Conceptual Overview of the Plat form Configuration St r u c t u r e The GMCH and ICH4-M are physically connect ed by a Hub interface. From a configuration standpoint, the Hub interface is logically PCI bu s #0.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 42 D15343-003 4.2 Nomenclature fo r Access Attributes Ta b l e 1 6 provides the nomenclature for the access attributes. T able 16. Nomenclature for Acces s Attributes A physical PCI Bus #0 does not exist.
Register Descriptio n D15343-003 43 4.3 S t andard PCI Bus Configuration Mechanism The PCI Bus defines a slot based “configuration space” that allows each de vice to contain up to eight functions with each function containing up to 256, 8-bi t configuration re gisters.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 44 D15343-003 4.4.2 Primary PCI and Downstr eam Configuration Mechanism If the Bus Number in the CONFIG_ADDRESS is non-zero, the GMCH will generate a T ype 1 Hub interface Configuration Cycle. A[1:0] of the Hub interface request packet for the T ype 1 configuration cycle will be “01”.
Register Descriptio n D15343-003 45 system initializati on soft ware (usually BI OS) to properly determ ine the DDR SDRAM configurations, operating parameters, and optio nal system features that are applicable and to program the GMCH registers accordingly .
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 46 D15343-003 Bit Descriptions 31 Configuration Enable (CFGE): When this bit is se t to 1, accesses to PCI Configuration Sp ace are enabled. If this bit is Reset to 0, access es to PCI Configuratio n S pace are disabled.
Register Descriptio n D15343-003 47 4.6.2 CONFIG_DA T A – Conf iguration Dat a Register CONFIG_DA T A is a 32-bit Read/W rite window into Configur ation Space. The portion of Configuration Space that is referenced by CO NFIG_DA T A is determined by the contents of CONFIG_ADDRESS.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 48 D15343-003 4.7 VGA I/O Mapped Registers If Native Graphics mode is strapped, and Device #2 is enabled, and Function #0 wi thi n Device #2 is enabled for VGA, and IO_EN is set within Functio n #0 then GMCH claims a set of I/O regi sters for legacy VGA function.
Register Descriptio n D15343-003 49 4.8 Intel 854 GMCH Host-Hub Inte rface Bridge Device Registers (Device #0, Function #0) T able 5 summarizes th e configuration space for Device #0, Function#0.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 50 D15343-003 Aperture T ranslation T able Base A T TBASE B8 BB 00000000h RO, R/W Host Error Control/S tatus/ Obs HEM F0 F3 00000000h RO, R/W.
Register Descriptio n D15343-003 51 4.8.1 VID – V endor Id entification Register The VID Register contains the vendor id enti fication number . This 16 -bit register , combined with the Device Identification Register, uniquely identif ies any PCI device.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 52 D15343-003 4.8.3 PCICMD – PCI Command Register Since GMCH Device #0 does not physically resi de on PCI_A m a ny of the bits are not implemented.
Register Descriptio n D15343-003 53 4.8.4 PCI St atus Register PCISTS is a 16-bit status regi ster that reports the occurrence of error events on Device #0's PCI Interface. Bit 14 is Read/W rite Clear . All other bits are Read Only . Since GMCH Device #0 does not physically reside on PCI_A many of the bits are not implement ed.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 54 D15343-003 4.8.5 RID – Register Identification This regist er contains the revision n umber of the GMCH Device #0. These bits are read only and writes to this regist er have no effect. 4.8.6 SUBC – Sub Class Code Register This register contains the Sub-Class Code for the GMCH Device #0.
Register Descriptio n D15343-003 55 4.8.7 BCC – Base Cl ass Code Register This register contains the Base Class code of the GMCH Device #0. This code is 06h indicating a Bridge device. 4.8.8 HDR – Header T ype Register This register identifies the header layout of the configuration space.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 56 D15343-003 4.8.10 SID – Subsystem Identification Register This value is used to id entify a partic ul ar subsystem. 4.8.1 1 CAPPTR – Cap abiliti es Pointer Register The CAPP TR provides the offset that is the pointer to the location of the first device capability in the capability li st.
Register Descriptio n D15343-003 57 4.8.12 CAPID – Cap abilities Identi fication Register (Device #0) The Capability Identificat ion Register un iquely identifies chipset capabilities as defined in the table below . The bits in th is register are intended to define a capability cei ling for each feature, not a capability select.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 58 D15343-003 4.8.13 GMC – GMCH Misce llaneous Control Re gister (Device #0) Address Offset: Default V alue: Access: Size: 50-51h 0000h Read/Write 16 bits Bit Descriptions 15:10 Reserved 9 Reserved 8 RRBAR Access Enable—R/W : 1: Enables the RRBAR space.
Register Descriptio n D15343-003 59 4.8.14 GGC – GMCH Graphics C ontrol Register (Device #0) Address Offset: Default V alue: Access: Size: 52-53h 0030h Read/Write 16 bits Bit Descriptions 15:7 Reser.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 60 D15343-003 4.8.15 DAFC – Device and Function Control Register (Device #0) This 16-bit register control s the visibility of devices and functions wi thi n the GMCH to configurati on software. 4.
Register Descriptio n D15343-003 61 4.8.17 PAM(6:0) – Programmable Attr ibute Map Register (Device #0) The GMCH allows programmable DDR SDRAM attributes on 13 Legacy system memory segments of various sizes in the 640 kB -1 MB address range. Seven Programmable Attrib ute Map (P AM) registers are used to suppor t these features.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 62 D15343-003 As an example, consider a BIOS that is im plemented on the Expansion bus. During the initialization process, the BIOS can be shadowed in main system memory to increase the system performance.
Register Descriptio n D15343-003 63 T able 21. P AM Registers and Associate d System Memory Segment s For details on overall syst em add ress mapping sche me see the Address Decoding section of this document. DOS Application Area (00000h-9FFFh ) The DOS area is 640 kB in si ze and it is further divi ded into two parts.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 64 D15343-003 Extended System BIOS Area (E0000h-EFFFFh) This 64-kB area is divided into four 16-kB segments that can be assigned wi th different attributes via P AM Cont rol register as defined in Figu re 4 and Ta b l e 2 1 .
Register Descriptio n D15343-003 65 4.8.19 ESMRAMC – Extended System Management RAM Control (Device #0) The Extended SMRAM register controls the configuration of Extended SMRAM Space. The Extended SMRAM (E_SMRAM) Memory provides a Write-Back cacheable SMRAM Memory Space that is above 1 MB.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 66 D15343-003 4.8.20 ERRSTS – Error Stat us Register (Device #0) This register is used to report various error conditions via Hub Interface Special cycles.
Register Descriptio n D15343-003 67 4.8.21 ERRCMD – Error Comm and Register (Device #0) This register enables various errors to genera te a SERR Hub Interface Sp ecial cycle. Since the GMCH does not have a SERR# signal, SERR messag es are passed from the GMCH to the ICH4 -M over Hub interface.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 68 D15343-003 4.8.22 SMICMD – SMI Error Co mmand Register (Device #0) This register enables various errors to generate an SMI Hub Interface Special cycle.
Register Descriptio n D15343-003 69 4.8.23 SCICMD – SCI Error Co mmand Register (Device #0) This register enables various errors to generate a SCI Hub Interface Special cycle.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 70 D15343-003 4.8.24 SHIC – Secondary Host Interf ace Control Regist er (Device #0) Address Offset: Default V alue: Access: Size: 74-77h 00006010.
Register Descriptio n D15343-003 71 4.8.25 HEM – Host Error Control, St atus, and Observation (Device #0) Address Offset: Default V alue: Access: Size: F0-F3h 00000000h Read Only , Read/Write 32 bits Bit Description 31 Detected HADSTB1# Glitch ( ASTB1GL ): This bit is set when the GMCH has detected a glitch on address strobe HADSTB1#.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 72 D15343-003 4.9 I ntel 854 GMCH Main Memory Control, Memory I/O Control Registers (Device #0, Function #1) The following table shows the GMCH Configuration Space for Device #0, Function #1. See “Nomenclature for Access Attributes” on page 42 for access nomenclature.
Register Descriptio n D15343-003 73 4.9.1 VID – V endor Id entification Register The VID Register contains the vendor id enti fication number . This 16-bit register com bin ed with the Device Identification Register uniqu ely identif ies any PCI device.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 74 D15343-003 4.9.3 PCICMD – PCI Command Register Since Intel chipset Device #0 does not physi cally reside on PCI_A, many of the bits are not implemented.
Register Descriptio n D15343-003 75 4.9.4 PCISTS – PCI St atus Register PCISTS is a 16-bit status regi ster that reports the occurrence of error events on Device #0's PCI Interface. Bit 14 is Read/W rite Clear . All other bits are Read Only . Since GMCH Device #0 does not physically reside on PCI_A, many of the bits are not implem ented.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 76 D15343-003 4.9.5 RID – Revision Id entification Register This regist er contains the revision n umber of the I n tel ® 82854 GMCH Device #0. These bits are Read Only and W rites to this register have no effect.
Register Descriptio n D15343-003 77 4.9.8 HDR – Header T ype Register This register identifies the header layout of the configuration space. No physical register exists at this location. 4.9.9 SVID – Subsystem V endor Identification Register This value is used to identify the vendor of the subsystem.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 78 D15343-003 4.9.1 1 CAPPTR – Cap abili ties Pointer Register The CAPP TR provides the offset that is the pointer to the location of the first device capability in the capability li st.
Register Descriptio n D15343-003 79 4.9.13 DRA – DRAM Row Attri bute Register (Device #0) The DDR SDRAM Row Attribute Register defines the page sizes to be used when accessing different pairs of Rows. Each Nibble of information in the DRA registers describes the page size of a pair of Rows: Row 0, 1: 50h Row 2, 3: 51h 52h-5Fh: Reserved.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 80 D15343-003 4.9.14 DRT – DRAM Timi ng Register (Device #0) This register controls the timing of the DDR SDRAM controller . Address Offset: Default V alue: Access: Size: 60-63h 18004425h Read/Write 32 bits Bit Description 31 DDR Internal Write to Read Comman d delay (tWTR) : The tWTR is a std.
Register Descriptio n D15343-003 81 27:26 Back T o Back Read-Write commands spacing (DDR, same or differen t Rows/Bank): This field determines the RD-WR command spacing, in terms of common clocks based on the following formula: CL + 0.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 82 D15343-003 1 1 Activate to Precharge delay (tRAS), MA X : This bit controls the maximum number of clocks that a DDR S DRAM bank can remain open. Af ter this time period, the system memory Controller will guara ntee to pre-charge the bank.
Register Descriptio n D15343-003 83 4.9.15 PWRMG – DRAM Controller Po wer Management Control Register (Device #0) Address Offset: Default V alue: Access: Size: 68-6Bh 00000000h Read/Write 32 bits Bi.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 84 D15343-003 10 Reserved . 9:1 Reserved 0 Power St ate S1/S3 Refres h Control : 0 = Normal Operation, Pending refresh es are not completed before entering Self Refresh for S1/ S3. 1 = All Pending Refreshes plus one extra is per formed before entering Self Refr esh for S1/S3.
Register Descriptio n D15343-003 85 4.9.16 DRC – DRAM Controller Mode Register (Device #0) Address Offset: Default V alue: Access: Size: 70-73h 00000081h RO, Read/Write 32 bits Bit Description 31:30 Revision Number ( REV): Reflects the revision number of the format used for DDR SDRAM register definition (Read Only).
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 86 D15343-003 9:7 Refresh Mode Select (R MS) : This field determines whether Refr esh is enabled and, if so, at what rate Refreshes will be executed. 000: Refresh disabled 001: Refresh enabled. Refresh inter val 15.
Register Descriptio n D15343-003 87 6:4 Mode Select (SMS). These bits select the special operational mode of the DDR SDRAM Interface. The special modes are intended for initialization at power up. 000: Post Reset S tate – When the GMCH exits Re set (power-up or otherwise ), the mode select field is cleared to 000.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 88 D15343-003 4.9.17 DTC – DRAM Throttling Control Register (Device #0) Throttling is indepen dent for system me mory banks, GM CH W rites, an d Thermal Sensor Trips. Read and W rite Bandwidth is meas ured independently for each ba nk.
Register Descriptio n D15343-003 89 Bit Description 31:28 DDR SDRAM Throttle Mode (TMODE) : Four bits control which mechanisms for Throttling are enabled in an “ OR” fashion. Counter- based Throttling is lower priority than Thermal Trips Throttling when both are enabled and T ripped.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 90 D15343-003 27:24 Read Counter Based Power Throttle Control (RCTC): These bits select the Counter based Power Throttle Bandwidth Limits for Read operatio ns to system memory . R/W , RO if Throttle Lock.
Register Descriptio n D15343-003 91 15:12 Write Thermal Based Power Throttle C ontrol (WTTC): These bits select the Thermal based Power Throttle Bandwidth Limits for Write operations to system memory .
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 92 D15343-003 4.10 Intel 854 GMCH Configuration Process Registers (Device #0, Function #3) See “Nomenclature for Access Attributes” on page 42 for access nomenclature. T able 23 summarizes all Device#0, Function #3 registers.
Register Descriptio n D15343-003 93 4.10.2 DID – Device Id entification Register This 16-bit register combined with the V endor Id entification register uniquely iden tifies any PCI device.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 94 D15343-003 4.10.3 PCICMD – PCI Command Register Since the Intel ® 82854 GMCH Device #0 does not physically reside on PC I_A many of the bits are not implemented.
Register Descriptio n D15343-003 95 4.10.4 PCISTS – PCI St atus Register PCISTS is a 16-bit status regi ster that reports the occurrence of error events on Device #0's PCI Interface. Bit 14 is Read/W rite clear . All other bits are Read Only . Since GMCH Device #0 does not physically reside on PCI_A many of the bits are not implement ed.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 96 D15343-003 4.10.5 RID – Revision Id entification Register This regist er contains the revision n umber of the I n tel ® 82854 GMCH. These bits are Read Only and W rites to this register hav e no effec t.
Register Descriptio n D15343-003 97 4.10.8 HDR – Header T ype Register This register identifies the header layout of the configuration space. No physical register exists at this location. 4.10.9 SVID – Subsystem V endor Identification Register This value is used to identify the vendor of the subsystem.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 98 D15343-003 4.10.1 1 CAPPTR – Cap ab ili ties Pointer Register The CAPP TR provides the offset that is the pointer to the location of the first device capability in the capability li st.
Register Descriptio n D15343-003 99 T able 24. Intel ® 82854 GM CH Conf igurations an d Some Resolution Examples: Native Graphics Mode Stra ps Re ad Through HPLLCC[2:0]: D0:F3:Register Offset C0-C1h,.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 100 D15343-003 4.11 Intel ® 82854 GMCH Integrated Gr aphics Device Registers (Device #2, Function #0) This section contains the PCI configuration regist ers listed in order of ascending offset address.
Register Descriptio n D15343-003 101 4.1 1.1 VID – V endor Identifi cation Register (Device #2) The VID Register contains the vendor id enti fication number . This 16-bit register com bin ed with the Device Identification Register uniqu ely identif ies any PCI device.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 102 D15343-003 4.1 1.3 PCICMD – PCI Co mmand Register (Device #2) This 16-bit register provide s basic control over the IGD 's ability to respond to PCI cycles. The PCICMD register in the IGD disables the IGD PCI compliant master accesses to main system memory .
Register Descriptio n D15343-003 103 4.1 1.4 PCISTS – PCI S tat us Register (Device #2) PCISTS is a 16-bit status regi ster that reports the occurrence of a PCI compliant master abort and PCI compliant target abor t. PCISTS also indicates the DEVSEL# timing that has been set by the IGD.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 104 D15343-003 4.1 1.6 CC – Class Code Register (Device #2) This register contains the devi ce programming interface information related to the Sub-Class code and Base Class code definition for the IGD.
Register Descriptio n D15343-003 105 4.1 1.9 HDR – Header T ype Register (Devic e #2) This register contains th e Header T ype of the IGD. 4.1 1.10 GMADR – Graphics Memory Range Address Register (Device #2) IGD graphics system memory base addr ess is specified in this register .
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 106 D15343-003 4.1 1.1 1 MMADR – Memory Mapped Range Address Register (Device #2) This register requests allocation for the IGD registers and instruction ports. The allocation is for 512-kB and the base address is defined by bits [31:19].
Register Descriptio n D15343-003 107 4.1 1.13 SVID – Subsystem V endor Id entification Register (Device #2) 4.1 1.14 SID – Subsystem Identi fication Register (Device #2) 4.1 1.15 ROMADR – V ideo BIOS ROM Base Address Registers (Device #2) The IGD does not use a separate BIOS ROM, th erefore this register is hardwired to 0's.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 108 D15343-003 4.1 1.16 INTRLINE – Interrupt Line Register (Device #2) 4.1 1.17 INTRPIN – Interrupt Pin Reg ister (Device #2) 4.
Register Descriptio n D15343-003 109 4.1 1.19 MAXLA T – Maximum Late ncy Register (Device #2) 4.1 1.20 PMCAP – Power Management Cap abilities Register (Device #2) Address Offset: Default V alue: Access: Size: 3Fh 00h Read Only 8 bits Bit Description 7:0 Maximum Latency V alue : Bits[7:0]=00h.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 110 D15343-003 4.1 1.21 PMCS – Power Management Cont rol/S tatus Register (Device #2) Address Offset: Default V alue: Access: Size: D4-D5h 0000h .
Intel ® 82854 GMCH System Address Ma p D15343-003 111 5.0 Intel ® 82854 GMCH System Address Map A system based on the GMCH supports 4 GB of addressable system memory space a nd 64 kB+3B of addressable I/O space. The I/O and system memory spaces are di vided by sys tem configuration software into regions.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 112 D15343-003 5.2 D OS Comp atibility Area This compatibi li t y region is divided into the followi n g addr ess reg ions: • 0 - 640 kB DOS Area.
Intel ® 82854 GMCH System Address Ma p D15343-003 113 T able 26. System Memory Segmen t s and Their Attributes DOS Area (000000h-0 9FFFFh) The DOS area is 640 kB in size an d is always mapped to the main system memory contr oll e d b y the GMCH.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 114 D15343-003 Monochrome Display Adapt er (MDA) Range (0B00 00h - 0B7FFFh) Monochrome Display Adapter ranges is accessible when the Intel® 854 Chipset is strapped into Native Graphics mode. Legacy support req uires the ability to have a second graphics con tro ller (monochrome) in the system.
Intel ® 82854 GMCH System Address Ma p D15343-003 115 5.4 Main System Memory Addr ess Range (0010_0000h to T op of Main Memory) The address range from 1 MB to the top of main system memory is map ped to main DDR SDR AM address range controlled by th e GMCH.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 116 D15343-003 5.4.2.1 Extended SMRAM Address Range (HSEG and TSEG) The HSEG and TSEG SMM transact ion address spaces reside in th is extended system memory area. 5.4.2.2 H SEG SMM mode CPU accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh.
Intel ® 82854 GMCH System Address Ma p D15343-003 117 5.4.2.5 PCI Memory Addres s Range (T op of Main System Memory to 4 GB) The address range from the top of main DDR SDRAM to 4-GB (top of physical system memory space supported by the GMCH) is normally mapped via the Hub interface to PCI.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 118 D15343-003 5.4.3 System Management Mode (SMM) Memory Range The GMCH supports the use of main system me mory as System Management RAM (SMM RAM) enabling the use of System Management mo de.
Intel ® 82854 GMCH System Address Ma p D15343-003 119 T able 28. SMM Sp ace T ransaction Handling 5.4.4 System Memory Shadowing Any block of system memory that can be designated as Read-Only or W rite-Only can be "shadowed" into GMCH DDR SDRAM.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 120 D15343-003 5.4.5.1 PCI I/O Add res s Ma p pi ng The GMCH can be programmed to direct non-memory (I/O) acces ses to the PCI bus interface when CPU initiated I/O cycle addres ses are within the I/O address ra nge.
Intel ® 82854 GMCH System Address Ma p D15343-003 121 5.4.7 Hub Interface Decode Rules The GMCH accepts accesses from Hub interf ace to the following address ranges: • All Memory Read and W rite ac.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 122 D15343-003 5.4.7.2 Interface Deco d e Ru le s Cycles Initiated Using PCI Protocol The GMCH does not suppo rt any PCI access targeting Hub interface. The GMCH will claim PCI initiated memory read and write transactions decoded to the main DDR SDRAM range.
Functional Description D15343-003 123 6.0 Functional Description 6.1 Host Interface Overview The GMCH front side bus uses source synchron ous transfer for the address and data signals. The address signals are doubl e pumped and two addr esses can be generated every bus clock.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 124 D15343-003 MSI is dependent on the address of the interrupt Memory Write. The GMCH forwards inbound Hub interface memory writes to address 0FEEx_xxxxh , to the system bus as Interrupt Message transactions.
Functional Description D15343-003 125 series of I/O cycles to the south bridge. The BI OS needs to determine the size and type of system memory used for each of the rows of system me mory in order to properly configure the GMCH system memory interface.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 126 D15343-003 6.4 Integrated Graphics Overview The Intel ® 82854 GMCH provides a hi ghly integrated graphics accelerator and PCI set while allowing a flexible Integrated System Graphics solution. High bandwidth access to data is provided throu gh the system memory po rt.
Functional Description D15343-003 127 6.4.2 3D Engine The 3D engine of the GMCH has been designed with a deeply pipeli ned architecture, where performance is maximized by allo wing each stage of the pipelin e to simultaneously operate on different primitives or portions of the same primitive.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 128 D15343-003 The scissor rectangle accelerates th e clipping process by allowing th e driver to clip to a bigger region than the hardware renders to. The scissor rectangle is pixe l accurate, and independent of line and point widt h.
Functional Description D15343-003 129 6.4.2.10 T exture Chromakey Chromakey is a method for removing a specific color or range of colors fro m a texture map be fore it is applied to an object.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 130 D15343-003 Maps. T rilinear MIP Mappi ng is used minimize the visibility of LOD transitio ns across the polygon. • Anisotropic MIP Nearest (An isotropic filtering): Th is filter can be used when textured object pixels map back t o significantly non-square reg i ons of the texture (e.
Functional Description D15343-003 131 6.4.3.1 T exture Map Blending Multiple textures can be blended together in an iterative process and applied to a primitive. Th e GMCH allows up to four distinct or shared text ure co ordinates and t extur e maps to be specified onto the same polygon.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 132 D15343-003 The GMCH supports both types of fog operations, vertex and per pixel. If fog is disabled, the incoming color intensities are passe d un changed to the destination blend u nit.
Functional Description D15343-003 133 reasonably accurate depth buf fering within inches of the eye point. The selection of depth buf fer size is relatively independ ent of the color bu ffer . A 16-bit Z/W or 24-bit Z/W buffer can be selected with a 16-bit color buffer .
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 134 D15343-003 Data is horizontally and vertically aligned at the desti nation. If the destination for the BL T overlaps with the source system memory loc ati on, the GMCH can specif y which area in system memory to b egin the BL T transfer .
Functional Description D15343-003 135 6.4.6.1 Cur sor Color For mats Color data can be in an indexed format or a tru e color format. Indexed data uses the entries in the four-entry cursor palette to convert the two-bit inde x to a true col or format bef ore being pas sed to the blenders.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 136 D15343-003 6.4.7.5 Color Con trol Color control provides a method of changing the color characteristics of the pixel data. It is appl ied to the data while in YUV form at and uses input para meters such as brightness, saturation, hue (tint ) and contrast.
Functional Description D15343-003 137 6.4.8 V ideo Functionality The GMCH supports MPEG-2 decod ing hardware, sub-picture support and DTV . 6.4.8.1 MPEG-2 Decoding The GMCH MPEG2 D ecoding su pports Hardware Mot ion Compensation (HWM C).
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 138 D15343-003 6.5 Internal Graphic Display Interface The GMCH has three dedicated disp lay port s: an An al og CR T port and two Digital displ ay ports, DVOB and DVOC.
Functional Description D15343-003 139 6.5.1.1 ARIB Support Please refer to the ARIB TR-B15 Operational Guid elin es for Digital Satellite Broadcasting (detailed Implementation guideline for receiver) for an exha ustive coverage of this topic ( http://www .
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 140 D15343-003 6.5.1.3 HSYNC/VSYNC Fiel d Timing The interlace timing is pro vid ed on the timing generator associated with Display Pipe A. When data is being driven out of the device, HSYNC and VSYNC accompanies or frames the data.
Functional Description D15343-003 141 Following conditions should be met for the sync (HSYNC, VSYNC) and blank (HBLANK, VBLANK) signals: • Start of H(V)SYNC can not coin cide with start of H(V)BLANK • H(V)SYNC should always start after H(V)BLANK starts.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 142 D15343-003 6.5.3.2 ARIB 960 X 540 su ppo r t In order to support the conversion of a 960x540 or a 960x1080 Pl ane A buffer to 1920x1080i, the GMCH supports pixe l doub ling in the horizontal directi on and field replication in the vertical direction.
Functional Description D15343-003 143 6.5.4 Interlace support for Video Overlay Window In interlace mode, suppo rt fo r Field1 and Field2 timin g generation is supported by th e V ideo Overlay . The V ideo Overlay makes use of the DPODPfieldID signal generated by the Pipe A timing generator to synchro nize the field timing.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 144 D15343-003 Figure 1 1 shows how the timing registers switch while the bu ffer 0 and buffer 1 are scanned out. As shown in th e above figure, buffer switching in Multi-display mode occurs on VBLANK.
Functional Description D15343-003 145 6.5.5 Analog Display Port Characteristics The Analog display port provides an RGB signal output along with an HSYNC an d VSYNC signal. There is an associated DDC signal pair th at is implemented using GPIO pins dedicated to the analog port.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 146 D15343-003.
Power and Thermal Management D15343-003 147 7.0 Power and Thermal Management The Intel ® 82854 GMCH is int ended to be compliant with the following specificatio ns and technologies: • APM Rev 1.2 • PCI Power Management Rev 1.0 • PC'99, Rev 1.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 148 D15343-003 7.1 General Description of Supported CPU St ates C0 (Full On) : This is the only state that runs soft ware. All clocks are running, STPCLK is deasserted, and the processor core is active.
Power and Thermal Management D15343-003 149 7.3 Internal Thermal Sensor This section describes t he new on-die Thermal sensor capability . 7.3.1 Overview The Thermal sensor functions are provided below: Catastrophic T rip Point : This trip point is programmed through the BIOS durin g ini tial ization.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 150 D15343-003 7.4 External Thermal Sensor Input An External Thermal sensor wi th a serial interface may be placed next to DDR SDRAM DIMM (or any o.
Intel ® 82854 GMC H Strap Pins D15343-003 151 8.0 Intel ® 82854 GMCH Strap Pins 8.1 Strapping Configuration T able 33. S t rapping Signals and Configuration Note: All strap signals are sampled with resp ect to the leading edge of the Intel ® 82854 GMC H PWROK In signal.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 152 D15343-003 T able 34. Intel ® 82854 GMCH S trap s for Frequency/CPU Configuration GST[2:0] LCLKCTLB CPU FSB Freq DD R Freq Gfx Freq Core Vcc 000 0 Intel Celeron M Processor Family , Genuine Intel Processor 400MHz 266MHz 200MHz 1.
Ballout and Package Inf ormation D15343-003 153 9.0 Ballout and Package Information Figure 12. Intel ® 82854 GMC H Ballout Di agram (T op View) 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 154 D15343-003 9.1 VCC/VSS V oltage Group s T able 35. V oltage Lev els and Ball Out for V olta ge Gr oup s Name V oltage Level Ball out VCC 1.5 H14,J15,N14,N16,P13,P15,P17,R14,R16,T13,T15, T17,U14,U16,W21,AA15,AA17,AA19 VCCADAC 1.
Ballout and Package Inf ormation D15343-003 155 T able 36. Ballout T able Row Co lumn Signal Name Row Column Signal Name Row Colu mn Signal Name E 5 ADDID[0] AA 22 DPWR# G 3 DVOCD[1 1] F 5 ADDID[1] N .
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 156 D15343-003 Row Column Signal Name Row Column Signal Name Ro w Colum n Signal Name Y 25 HA[21]# F 25 HD[16]# B 23 HD[43]# AA 27 H A[22]# F 26 HD.
Ballout and Package Inf ormation D15343-003 157 Row Co lumn Signal Name Row Column Signal Name Row Colu mn Signal Name K 27 HDSTBP[0]# H 10 HSYNC T 7 MDDCDA T A D 26 HDSTBP[1]# M 25 HTRDY# N 7 MDVICLK.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 158 D15343-003 Row Column Signal Name Row Column Signal Name Ro w Colum n Signal Name AD 28 RSTIN# AB 4 SCK[5]# AF 4 SDQ[2] F 12 RSVD AC 7 SCKE[0] .
Ballout and Package Inf ormation D15343-003 159 Row Co lumn Signal Name Row Column Signal Name Row Colu mn Signal Name AG 22 SDQ[47] AG 2 SDQS[0] AC 21 SRAS# AE 23 SDQ[48] AH 5 SDQS[1] AD 25 SWE# AH 2.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 160 D15343-003 Row Column Signal Name Row Column Signal Name Ro w Colum n Signal Name B 14 VCC1_5 AJ 6 VCCQSM AB 6 VCCSM J 13 VCC1_5 AG 29 VCCSM AA.
Ballout and Package Inf ormation D15343-003 161 Row Co lumn Signal Name Row Column Signal Name Row Colu mn Signal Name AJ 26 VSS U 22 VSS AA 18 VSS AB 26 VSS R 22 VSS J 18 VSS W 26 VSS N 22 VSS F 18 V.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 162 D15343-003 Row Column Signal Name Row Column Signal Name Ro w Colum n Signal Name AB 13 VSS L 9 VSS K 4 VSS U 13 VSS E 9 VSS G 4 VSS R 13 VSS A.
Ballout and Package Inf ormation D15343-003 163 Row Column Si gnal Name H2 2 V T T L F U2 1 V T T L F R2 1 V T T L F N2 1 V T T L F L2 1 V T T L F H2 0 V T T L F A2 0 V T T L F J1 9 V T T L F H1 8 V T.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 164 D15343-003 9.2 Package Mechanical Information Figure 13 through Figure 1 5 provide detail on the package in format ion and dimensions of the Intel ® 82854 GMCH. The Intel ® 82854 GMCH come s in a Micro-FCB GA package, which is similar to the mobile processors.
Ballout and Package Inf ormation D15343-003 165 Figure 14. Intel ® 82854 GMCH Micro-FCBGA Pack age Dimensions (Side V iew).
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 166 D15343-003 Figure 15. Intel ® 82854 GMCH Micr o-FCBGA Package Dimensions ( Bo ttom View).
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