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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design Application Note - Rev 1.0, 3/20/20 02 Order Num ber: 27839 3-001.
Application Note Informati on in this do cument is prov ided in connect ion wi th Intel ® products. No licen se, express or imp lied, by estoppe l or otherwi se, to any intellectu al property rights is grante d by this docume nt.
Application Note iii IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Contents 1.0 Int roduct ion ....... ............. ............. ............. ................... ............. ............. ............. ....
iv Application Note IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 3.7.2 CRC-32 C hecke r and G enerator Hig h Lev el Algorit hm............ ............. . 29 3.7.3 CRC-32 C omputation ............ ............ ..
Application Note v IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design 4.8.2.2 Counter Inde x ........ ...... ...... ....... ...... ....... ...... ....... ...... ....... ...... .... 4 7 4.8.2.3 Global Counter E nable an d Flags .
vi Application Note IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design Figures 1 IP ove r ATM Encap sulation Format ... ............ ............. ............. ............. ................ 9 2 Frame a nd PDU Leng th vs.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 7 Modifi ed on: 3/ 20/02, 1.0 Int roduc tion Intel develops examp le software to demons trate the capabilities of the IX P1200 Network Process or Family .
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 8 Application Note Modified on: 3/20/02, 1.2.1 Supported / Not Implemented Functions The following identifies the A TM, Ethernet, and StrongARM sup ported functions, as well as those func t ion s tha t a re no t sup port ed.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 9 Modifi ed on: 3/ 20/02, 1.3.2 Frame and PDU Length vs. IP Packet Length Figur e 2 shows the relationship between IP Packet Length ( X axis), Ethernet Frame Length, and AAL5 PDU length (Y axis).
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 10 Application Note Modified on: 3/20/02, PDUs because 8-bytes of LLC /SNAP plus 8 b ytes of AA L5 trailer push them over the 48 byte payload capacity of a s ingle A TM cell.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 11 Modifi ed on: 3/ 20/02, A 33-byte IP pack et overflows into 2 cells, requiring 53 mo re bytes on the inpu t wire.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 12 Application Note Modified on: 3/20/02, Figur e 4 shows h ow data stream PDUs can be created in the W orkb ench fo r A TM, Ethernet, IP , and other protocol data streams.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 13 Modifi ed on: 3/ 20/02, . 1.4.2 Hardwar e The README.txt file contained in the vxworks subdirectory of the project so urce code des cribes how to bui l d an d ru n t he pr oje ct on hard war e usi ng Vx W or ks ® .
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 14 Application Note Modified on: 3/20/02, The StrongARM core shares access to SRAM and DRAM with the microengin es, and thus can manage the VC and I P tables.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 15 Modifi ed on: 3/ 20/02, 2.3 Software Partiti oning The following figures show how the microcode functional blocks are partiti oned on IXP12xx hardware for the three system configu rations.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 16 Application Note Modified on: 3/20/02, In the OC-12 configu ration, there are two mes sage queues (MSGQs) in s cratchpad RAM, one for PDUs from each Ethern et Receive microengine.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 17 Modifi ed on: 3/ 20/02, 2.4 Data Flow 2.4.1 A TM to Ethernet Data Flow Figur e 10 outlines the processing to receive A TM cells and forward them to Ethernet ports.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 18 Application Note Modified on: 3/20/02, syndrome is updated ap propriately . The VC T able Entry also contains an AAL type f iel d. Currently , this example design su pports only classical IP over A TM, where the AAL type can be either 0 or 5.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 19 Modifi ed on: 3/ 20/02, 2.4.2 Ether ne t to A TM Data Flo w Figur e 11 outlines the sequence of events that takes place when processing incoming Ethernet packets.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 20 Application Note Modified on: 3/20/02, 3. Run the IXP12 00 Develope r ’ s W orkbench debug library , and connects it to a r emote system host via the PCI Eth ernet NIC to download and debug IXP1240 microcode.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 21 Modifi ed on: 3/ 20/02, 3.1.2 High Level Algorithm In all conf igurations, each Receive thr ead gets its own RFIFO element, as assigned by port_r x_init( ) .
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 22 Application Note Modified on: 3/20/02, 3.2 A TM T ransmit Microengine The A TM T ransmit microengine is an AAL5 U.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 23 Modifi ed on: 3/ 20/02, 3.3 IP-Router Microengine The IP Router micro engine consumes packets from the A TM receive microengine via a message queue, and routes them to the app ropriate Ethernet transmit packetq.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 24 Application Note Modified on: 3/20/02, • For A T M destinations, enqu eue to the A TM Transmit microengine, or for software C RC, to the appropriat e AAL5 CR C-32 generati on queues.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 25 Modifi ed on: 3/ 20/02, 3.5.1 Ethernet T ransmit Struc tur e The Ethernet T ran smit microengine contain s three fill thr eads and one trans mi t sch eduler thread .
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 26 Application Note Modified on: 3/20/02, Quadwords 1-5 are tra ns ferred by an sdram_crc[r_fifo_rd, 5] instruction. Quadwor d 6 contains "Data 1 1" -- the eleventh 32-bit longword of the cell.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 27 Modifi ed on: 3/ 20/02, • Upon reception of the f i rst cell, data11 is s aved in th e VC cach e/table en try .
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 28 Application Note Modified on: 3/20/02, The hardware byte aligner operates on the data b efore the CRC computation h ardware.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 29 Modifi ed on: 3/ 20/02, 3.7.2 CRC -32 Checker and Generator High Level Algorithm The PDUs within each VC on each port are enq ueued on the outpu t in the same order that they were dequeued fr om the input.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 30 Application Note Modified on: 3/20/02, The OC-12 conf iguration uses a VC T able Cache in co njunction with the VC table, however the description of the backing VC tab le in this section applies with or with out the presence of a VC Cache.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 31 Modifi ed on: 3/ 20/02, When atm_vc_table_entry _create() attempts to add an entry to the tabl.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 32 Application Note Modified on: 3/20/02, The project defaults to s upport a 64K-entry VC table - independent of th e number of ports. It d oes this with eight si gnificant VCI bits, and eight more bits split betw een VPI and ports.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 33 Modifi ed on: 3/ 20/02, Entry Description Nex t Address of the next entry in t he chain of entries that hash to the same row . 0 indicates no next entry .
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 34 Application Note Modified on: 3/20/02, 4.2 Virtual Ci rcuit Lookup T able Cache 4.2.1 VC Cache Function 4.2.1.1 OC-12 Configuration The intent of the VC cache is not to reduce aver age latency but to account for back to back cells from the same VC.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 35 Modifi ed on: 3/ 20/02, 4.2.3 VC Cache API There is no interaction between the StrongARM core and the VC Cache.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 36 Application Note Modified on: 3/20/02, 4.3.3 IP T able Management API The route table is mana ged by the Route T able Manager (R TM), which may b e used from both T ransactor Scripts and VxW orks.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 37 Modifi ed on: 3/ 20/02, 4.3.3.4 enet_route_add() Adds a route with Ethernet destination to the route table.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 38 Application Note Modified on: 3/20/02, 4.4 SRA M Buffer Descriptors and DRAM Data Buffers SRAM Buffer Descr iptors and DRAM Data Buf f ers are a fundamental componen t of this design.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 39 Modifi ed on: 3/ 20/02, Both descriptors and buf fers are stored i n arrays. The ar ray index is u sed to associate a un ique DRAM Data Buffer with each SRAM Descriptor: 4.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 40 Application Note Modified on: 3/20/02, 4.4.2 DRAM Da ta Buffe r Format Packet payloads are s tored in DRAM data bu ffers . Depending on if the d ata was received o n an A TM or Ethernet port, the p ayload will land in a dif ferent place within the data buf fer .
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 41 Modifi ed on: 3/ 20/02, 4.4.3 System Li mit on Pack et Buffe rs Several factors are involved in the number of p acket buff ers the system can support: • The Ethernet transmitter uses packetqs ( packetq.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 42 Application Note Modified on: 3/20/02, 4.5.2 Usa ge Mo del The following model is d escribed by an analogy to waiting in line at a baker y:.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 43 Modifi ed on: 3/ 20/02, 4.6.1 MSGQ_HANDLE Parameters The following parameters make up MSGQ_HANDLE and are common to all macr os in msgq.uc : 4.6.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 44 Application Note Modified on: 3/20/02, msgq_send(io_message, MSGQ_HANDLE , RAM_OPTION ) 4.6.5 m sgq_receive () Receives a message fr om the queue. msgq_receive(i o_xfer, MSGQ_HANDLE ) 4.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 45 Modifi ed on: 3/ 20/02, 4.7 Buffer Descri ptor Queues - bdq.uc This design uses a generi c buffer descriptor queu ing subsystem to pass data between micro engines.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 46 Application Note Modified on: 3/20/02, For the synchro nous empty->non -empty queue n otification feature to be u sed, only one microengine can be ass igned to dequeu e from each queu e.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 47 Modifi ed on: 3/ 20/02, • On hardware, counters .c is compiled into the atm_util s.o VxW orks-loadable mo dule to provide counters at the VxW orks console.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 48 Application Note Modified on: 3/20/02, 4.8.2.3 Global Counter Enabl e and Flags Global Counter Enable and Flags COUNTERS_ENABLE_MASK is the global counter enable and is set via a #define s tatement in syste m_c onf ig.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 49 Modifi ed on: 3/ 20/02, 4.8.3 counters.uc 4.8.3.1 counter_reset() Resets the specified coun ter to zero. counter_reset( in_counter_base, in_counter_offset, IN_ENABLE_FLAGS ) 4.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 50 Application Note Modified on: 3/20/02, port_counter_inc() Algorithm #if (IN_ENABLE_FLAGS & COUNTERS_ENABLE_MA.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 51 Modifi ed on: 3/ 20/02, 4.8.4 counters.c 4.8.4.1 counters_init() Initializes al l counters. 4.8.4.2 counters_print() Prints the names and values o f all coun ters.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 52 Application Note Modified on: 3/20/02, 237:[42]: 0 ETHER_RX_PACKET_ENQUEUE_ETHER 238:[43]: 1805817712 ATM_TX_CRC_.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 53 Modifi ed on: 3/ 20/02, // sram[read, $foo], ordered, ctx_swap 4.10 Mutex V ectors Mutex vectors are an extension to criti cal sectio ns that allows multiple criti cal sectio ns to be contained within a single ab solute register .
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 54 Application Note Modified on: 3/20/02, 4.1 1 Inter-Thread Signalling Inter-thr ead signals are used in four ways: • Initializatio n, as d etailed in the “ Microengine Initialization ” section.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 55 Modifi ed on: 3/ 20/02, // Define DEBUG to enable all the counters and run-time checking. // Disable for maximum performance. // #define DEBUG // Define COUNTERS_ENABLE_MASK to all 1’s to enable every system counter.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 56 Application Note Modified on: 3/20/02, 7.0 Sim ulation Support (Scripts, etc.
IXP120 0 Network Proces sor Family A T M OC-3/12/ Et hernet I P Router Example Design Application Note 57 Modifi ed on: 3/ 20/02, 10.0 Document Con ventions In illustrations of 3 2-bit registers, or d ata structures in memor y; smaller addresses appear toward the top of the fig ure, - as they would appear in a memory dump o n the screen.
IXP1200 Netw ork Processor Fa mily A TM OC-3/ 12/Ether net IP Router Example Design 58 Application Note Modified on: 3/20/02, 12.0 Related Docume nts PDU P rotocol Data Unit Rosetta Intel IXB8055 IX B.
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