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318589-005 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet August 2008.
2 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL ® PRODUCTS. NO LIC ENSE, EXPRESS OR IMPLIED , BY ESTOPPEL OR O THERWISE, TO ANY INTELLECTUAL PROPER TY RIGHTS IS GRANTED BY THIS DOCUMENT .
Quad-Core Intel® Xeon® Processor 5400 Series Datasheet 3 Contents 1I n t r o d u c t i o n ......... ............. ............... ............ ............... ............. .............. ............. ...... 9 1.1 Terminology ........... .........
4 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet 6.2.1 Intel ® Thermal M onitor Features ................. ............... .............. ............... .. 90 6.2.2 On-Demand Mod e ......... ............... ............. ............... ..
Quad-Core Intel® Xeon® Processor 5400 Series Datasheet 5 Figures 2-1 Input Device Hy steresis ............ .............. ............... ............... ............... .............. 25 2-2 Quad-Core Intel® Xe on® Processor X5482 Load Current versus Time .
6 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet Tables 1-1 Quad-Core Intel® X eon® Processor 5400 Series . ................... ................ ...............10 2-1 Core Frequency to FSB Multiplier Configuration .... .............. .....
Quad-Core Intel® Xeon® Processor 5400 Series Datasheet 7 Revision History § Revision Description Date 001 Initial release November 2007 002 Added product information fo r the Quad-Core Intel® X eon® Processor L5408. March 2008 003 Added product information fo r the Quad-Core Intel® X eon® Processor L5400 Series.
8 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet.
9 1 Introduction The Quad-Core Intel® X eon® Proce ssor 5400 Se ries is a server/workstation processor utilizing four 45-nm Hi-k next generation Intel® Core™ microarchitecture cores.
10 solutions. Intel Virtualization T echnology is used in conjunction with Virtual Machine Monitor software enabling multiple, independent softw are environments inside a single platform. Further details on Intel Virtualization T echnology can be found at http://developer .
11 Commonly used terms are explained here for clarification : • Quad-Core Intel® Xeon® Processor 5400 Series - Intel 64-bit microprocessor intended for dual processor servers and workstations based on Intel’ s 45 nanometer process, in the PC-LGA 771 pack age with four processor cores.
12 • Processor core – Processor core with integrated L1 cache. L2 cache and system bus interface are shared between the two core s on the die. All AC timing and signal integrity specifications are at the pads of the system bus interface. • Front Side Bus (FSB) – The electrical interface that connects the processor to the chipset.
13 • VRM (Volt age Regulato r Module) – DC-DC converter built onto a module that interfaces with a card edge socket and supplies the correct voltage and cu rrent to the processor based on the logic state of the processor VID bits.
14.
15 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 2 Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications 2.1 Front Side Bus and GTLREF Most Quad-Core Intel® X eon® Processor 5400 Series FSB signals use Assisted Gunning T ransceiver Logic (AGTL+) signalin g technology .
Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 16 2.2 Power and Ground Lands For clean on-chip processor core power distribution, the processor has 223 V CC (power) and 267 V SS (ground) inputs.
17 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core freque ncy of the processor .
Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 18 2.4.2 PLL Power Supply An on-die PLL filter solution is implemented on the Quad-Core Intel® Xeon® Processor 5400 Series. The V CCPLL input is used for this configuration in Quad-Cor e Intel® Xeon® Processor 5400 Series-based platforms.
19 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications The Quad-Core Intel® Xeon® Processor 5400 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (V CC ). This will represent a DC shift in the load line.
Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 20 Notes: 1. When the “111111” VID pattern is observed, th e voltage regulator output should be disabled. 2. Shading denotes the expected VID range of the Quad-Core Intel® Xeon® Processor 5400 Series .
21 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Note: The LL_ID[1:0] si gnals are used to select t he correct loadline s lope for the proces sor . Note: The MS_ID[1:0] signals are provided to indicate the Market Segment for the processor an d may be used for future processor co mpatibi lity or for keying.
Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 22 The TESTHI signals must use individual pull-up resistors as detailed below .
23 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Notes: 1. Refer to Chapter 5 for signal descriptions. 2. These signals ma y be driven simultane ous ly by multiple agents (Wired-OR). Ta b l e 2 - 7 outline s the signals which include on-die termination (R TT ).
Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 24 2.8 CMOS Asynchronous and Open Drain Asynchronous Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI# , and STPCLK# utilize CMOS input buffers. Legacy output sign al s such as FERR#/PBE#, IERR#, PROCHOT#, and THERMTRIP# utilize open drain output bu ffers.
25 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Note: 1. V TT supplies the PECI interface. PECI behavior does not affect V TT min/max specifications. 2. The leakage specification applies to p owered devices on the PECI bus.
Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 26 2.11 Mixing Processors Intel supports and validates dual proce ssor configurations only in which both processors operate with the same FSB frequency , core frequency , power segments, and have the same internal cache siz es.
27 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Notes: 1. For functio nal operation, all processor electri cal, sign al quality , mechanical and thermal specifications must be satisfied. 2. Overshoot and u ndershoot volta ge guidelines for input, output, an d I/O signals a re outlined in Chapter 3 .
Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 28 Table 2-12. Voltage and Current Sp ecifications (Sheet 1 of 2) Symbol Parameter Min Typ Max Unit Notes 1, 11 VID VID range 0.
29 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Notes: 1. Unless otherwise noted, all specifications in this table are based on final silic on characterization data. 2. These voltages are targets only . A variable vo ltage source should exist on syste ms in the event that a different voltage is required.
Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 30 3. The voltage spec ification requirem ents are meas ured ac ross the VCC_D IE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE _SE NSE2 lands with an osci lloscope set to 100 MHz bandwidth, 1.
31 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Notes: 1. Processor or V oltage Regulator thermal protec tion circuitry should not trip for load cur rents greater than I CC_TDC . 2. Not 100% tested. Specified by design characterization.
Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 32 Notes: 1. Processor or V oltage Regulator thermal protectio n circ uitry should not trip for load currents greater than I CC_TDC . 2. Not 100% tested. Specified by design characterization.
33 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Notes: 1. The V CC_MIN and V CC_MA X loadlines represent stati c and transient limits. Please see Section 2.13.2 for V CC over shoot specification s. 2. This table is intended to ai d in reading discre te points on Figure 2-7 .
Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 34 Notes: 1. The V CC_MIN and V CC_MAX loadlines represent static an d transient limits. Please see Section 2.13.2 for V CC overshoot specifications. 2. This table is intended to ai d in reading discrete points on Figure 2-8 and Figure 2-9 .
35 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Figure 2-7. Qu ad-Core Intel® Xeon® Processor X5482 V CC Static and Transient Tolerance Load Lines VI D - 0.00 0 VI D - 0.05 0 VI D - 0.10 0 VI D - 0.15 0 VI D - 0.20 0 VI D - 0.
Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 36 Figure 2-8. Quad-Core Intel® Xe on® Processor X5400 Series V CC Static and Transient Tolerance Load Lines Figure 2-9. Quad-Core Intel® Xe on® Processor E5400 Series V CC Static and Transient Tolerance Load Lines VID - 0.
37 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Notes: 1. The V CC_MIN and V CC_MAX loadlines represent static and transient limits. Pleas e see Section 2.13.2 for VCC over shoot specification s. 2. Refer to Ta b l e 2 - 1 2 for processor VID information.
Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 38 Notes: 1. Unless otherwise noted, all specifications in this table apply to a ll processor freque ncies. 2. The V TT referred to in these specifications refers to ins tantaneous V TT .
39 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications Notes: 1. VOS is the measur ed overshoot voltage. 2. TOS is the measured time duration above VID .
Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 40 The AGTL+ reference voltages (GTLREF _DA T A_MID, GTLREF_DA T A_END, GTLREF_ADD_MID, and GTLREF_ADD_END) must b e generated on the baseboard using high precision voltage divider circuits.
41 Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 7. Threshold R egion is defined as a region entered aroun d the crossi ng point voltag e in which the differential receiver sw itches. I t includes input threshold hysteresis.
Quad-Core Intel® Xeon® Processor 540 0 Series Electrical Specifications 42 § Figure 2-14. Diffe rential Cloc k Crosspoint Specification Figure 2-15.
43 Mechanical Specifications 3 Mechanical Specifications The Quad-Core Intel® Xeon® Processor 5400 Series is packaged in a Flip Chip Land Grid Array (FC -LGA) package that interfaces to the baseboard via a LGA771 socket. The package consists of a processor core mounted on a pinless substrate with 771 lands.
Mechanical Specifications 44 Note: Guidelines on potential IHS flatne ss v ariation with socket load plate actuation and installatio n of the cooling solution are available in the processor Ther ma l/Mechanical Desi gn Guidelines.
45 Mechanical Specifications Figure 3-3. Quad-Core Intel® Xeon® Pr oces sor 5400 Series Package Drawing (Sheet 2 of 3).
Mechanical Specifications 46 Note: The optional dimpl e packing marking highlighted b y Detail F from the above dr awing may only be found on initial processo rs.
47 Mechanical Specifications 3.2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. Decoupling capacitors are typically mounted to either the topside or landside of the package substrate.
Mechanical Specifications 48 3.4 Package Handling Guidelines Ta b l e 3 - 2 includes a list of guidelines on a pa ckage handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experien ced during heatsink removal.
49 Mechanical Specifications Note: 2D matrix is required for engineerin g samples only ( encoded with A TPO-S/N). 3.9 Processor Land Coordinates Figure 3-6 and Figure 3-7 show the top and bottom view of the processor land coordinates, respectively . The coordinates are referred to throughout the document to identify processor lands.
Mechanical Specifications 50 § Figure 3-7. Processor Land Coordinates, Bottom View V TT / Clocks 1 2 3 4 5 6 7 8 9 1 0 1 11 2 1 31 41 51 61 7 1 81 9 2 02 1 2 22 32 42 52 62 72 82 93 0 A B C D E F G H.
51 Land Listing 4 Land Listing 4.1 Quad-Core Intel® Xeon® Processor 5400 Series Pin Assignments This sect ion provid es sorted la nd list in Ta b l e 4 - 1 and Ta b l e 4 - 2 . Ta b l e 4 - 1 is a listing of all proc essor lands ordered alphabetically by land name.
Land Listing 52 BSEL0 G29 CMOS ASync Output BSEL1 H30 CM OS ASync Output BSEL2 G30 CM OS Async Output COMP0 A13 Power/Other Input COMP1 T1 Power/Other Input COMP2 G2 Power/Other Inpu t COMP3 R1 Power/.
53 Land Listing DP2# H16 Common Clk Input/Ou tput DP3# J17 Common Clk Input/Output DRDY# C1 Common Clk Input/Output DSTBN0# C8 Source Sync Input/Output DSTBN1# G12 Source S ync Input/Output DSTBN2# G2.
Land Listing 54 RESERVED G24 RESERVED F24 RESERVED F26 RESERVED F25 RESERVED G25 RESERVED W3 RESERVED AM2 RESET# G23 Common Clk Input RS0# B3 Common Clk Input RS1# F5 Common Clk Input RS2# A3 Common C.
55 Land Listing VCC AG30 Power/Other VCC AG8 Power/Oth er VCC AG9 Power/Oth er VCC AH11 Power/Other VCC AH12 Power/Other VCC AH14 Power/Other VCC AH15 Power/Other VCC AH18 Power/Other VCC AH19 Power/O.
Land Listing 56 VCC AN8 Power/Other VCC AN9 Power/Other VCC J10 Power/Other VCC J11 Power/Other VCC J12 Power/Other VCC J13 Power/Other VCC J14 Power/Other VCC J15 Power/Other VCC J18 Power/Other VCC .
57 Land Listing VCC W8 Power/Other VCC Y23 Power/Other VCC Y24 Power/Other VCC Y25 Power/Other VCC Y26 Power/Other VCC Y27 Power/Other VCC Y28 Power/Other VCC Y29 Power/Other VCC Y30 Power/Other VCC Y.
Land Listing 58 VSS AF29 Power/Other VSS AF3 Power/Ot her VSS AF30 Power/Other VSS AF6 Power/Ot her VSS AG10 Power/Other VSS AG13 Power/Other VSS AG16 Power/Other VSS AG17 Power/Other VSS AG20 Power/O.
59 Land Listing VSS B11 Power/Other VSS B14 Power/Other VSS B17 Power/Other VSS B20 Power/Other VSS B24 Power/Other VSS B5 Power/Other VSS B8 Power/Other VSS C10 Power/Oth er VSS C13 Power/Oth er VSS .
Land Listing 60 VSS L7 Power/Other VSS M1 Power/Other VSS M7 Power/Other VSS N3 Power/Other VSS N6 Power/Other VSS N7 Power/Other VSS P23 Power/Other VSS P24 Power/Other VSS P25 Power/Other VSS P26 Po.
61 Land Listing 4.1.2 Land Listing by Land Number Table 4-2. Land Listin g by Land Number (Sheet 1 of 20) Pin No. P in Name Signal Buffe r Type Directio n A10 D08# Source Sync Input/Output A11 D09# So.
Land Listing 62 AD26 VCC P ower/Other AD27 VCC P ower/Other AD28 VCC P ower/Other AD29 VCC P ower/Other AD3 BINIT# Common Clk Input/Outp ut AD30 VCC P ower/Other AD4 VSS Power/Other AD5 ADSTB1# Source.
63 Land Listing AG18 VCC Power/Other AG19 VCC Power/Other AG2 BPM3# Comm on Clk Input/Output AG20 VSS Power/Other AG21 VCC Power/Other AG22 VCC Power/Other AG23 VSS Power/Other AG24 VSS Power/Other AG.
Land Listing 64 AJ9 VCC P ower/Other AK1 RESERVED AK10 VSS Power/Othe r AK11 VCC Power/Oth er AK12 VCC Power/Oth er AK13 VSS Power/Othe r AK14 VCC Power/Oth er AK15 VCC Power/Oth er AK16 VSS Power/Oth.
65 Land Listing AM26 VCC Power/Other AM27 VSS Power/Other AM28 VSS Power/Other AM29 VCC Power/Other AM3 VID2 CMOS Async Output AM30 VCC Power/Other AM4 VSS Power/Oth er AM5 VID6 CMOS Async Output AM6 .
Land Listing 66 C2 BNR# Common Clk Input/O utput C20 DBI3# Source Sync Input/Output C21 D58# Source Sync Input/Output C22 VSS P ower/ Other C23 RESERVED C24 VSS P ower/ Other C25 VT T Power/ Other C26.
67 Land Listing F10 VSS Power/Other F11 D23# Source Sync Input/Output F12 D24# Source Sync Input/Output F13 VSS Power/Other F14 D28# Source Sync Input/Output F15 D30# Source Sync Input/Output F16 VSS .
Land Listing 68 H27 VSS Power/Ot her H28 VSS Power/Ot her H29 VSS Power/Ot her H3 VSS Power/Other H30 BSEL1 CMOS Async Output H4 RSP# Common Clk Input H5 BR1# Common Clk Input H6 VSS Power/Other H7 VS.
69 Land Listing M28 VCC Power/Other M29 VCC Power/Other M3 STPCLK# CMOS Async Input M30 VCC Power/Other M4 A07# Source Sync Input/Output M5 A03# Source Sync Input/Output M6 RE Q2# Source Sync Inpu t/O.
Land Listing 70 § U28 VCC P ower/Other U29 VCC P ower/Other U3 AP1# Common Clk Input/Output U30 VCC P ower/Other U4 A13# Source Sync Input/Output U5 A12# Source Sync Input/Output U6 A10# Source Sync .
71 Signal Definitions 5 Signal Definitions 5.1 Signal Definitions Table 5-1. Signal Definitions (She et 1 of 8) Name Type Description Notes A[37:3]# I/O A[37:3]# (Address) define a 2 38 -byte physical memory address space. In sub-phase 1 of the ad dress phase, these signals transmit the address of a trans action.
Signal Definitions 72 BCLK[1:0] I The differential bus clock pair BCLK[1:0] (Bus Clock) determines the FSB frequency . All processor FS B agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to t he rising edge of BCLK0 crossing V CROSS .
73 Signal Definitions BSEL[2:0] O The BCLK[1:0] frequency select signal s BSEL[2:0] are used to select the proces sor input cl ock freque ncy . Ta b l e 2 - 2 defines the p ossible combinations of the signals and the frequency associated wit h each combination.
Signal Definitions 74 DEFER# I DEFER# is asserted by an agent to indicate that a tr ansaction cannot be guaranteed in-order co mpletion. Assertion of DEFE R# is normally the responsibility of the addressed me mory or I/O agent. This signal must connect the app ropriate pins of all processor FSB agents.
75 Signal Definitions GTLREF_DA TA_MID GTLREF_DA TA_END I GTLREF_DA TA determines the signal reference level for AGTL+ data input lands. GTLREF_DA TA is us ed by the AGTL+ receivers to determine if a signal is a logical 0 or a logical 1. Please refer to Ta b l e 2 - 1 9 and the appropriate p latform design guidelines for additional details.
Signal Definitions 76 MCERR# I/O MCERR# (Machine Check Error ) is asserted to indicate an unrecover able error without a bus pro tocol violation. It may be driv en by all processor FSB agents. MCERR# assertion conditions are configurable at a system lev el.
77 Signal Definitions RSP# I RSP# (Response Parity) is driven by the response agent (the agent responsible for comp letion of the current tr ansaction) during assertion of RS[2:0]#, the si gnals for which RSP# provides parity protection. It must connect to th e appropriate pins of all processor FSB agents.
Signal Definitions 78 Notes: 1. For this pr ocessor land on the Quad-Core Intel® Xeon ® Processor 5400 Series, the maximum number of symmetric agents is one . Maximum number of pr iority agents is zero . 2. For this pr ocessor land on the Quad-Core Intel® Xeon ® Processor 5400 Series, the maximum number of symmetric agents is two.
79 Thermal Specifications 6 Thermal Specifications 6.1 Package Thermal Specifications The Quad-Core Intel® Xeon® Processor 5400 Series requires a the rmal solution to maintain temperatures within its operating limits.
Thermal Specifications 80 Processor Thermal Features). Systems that implement fan speed control must be designed to use this data. Systems that do n ot alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications.
81 Thermal Specifications power dissipation is currently planned. Intel® Thermal Moni to r 1 and Inte l® Thermal Monitor 2 feature must be enable d for the processor to remain within its specifications. Notes: 1. These values are specified at V CC_MAX for all processor frequencies.
Thermal Specifications 82 Table 6-2 . Quad-Core Intel ® Xeon® Processor X549 2 and X5482 (C-step) Thermal Profile Table Power (W ) T CASE_MA X ( ° C) 0 35.0 5 35.9 10 36.9 15 37.8 20 38.7 25 39.7 30 40.6 35 41.5 40 42.5 45 43.0 50 44.4 55 45.3 60 46.
83 Thermal Specifications Notes: 1. These values are specified at V CC_MAX for all processor frequencies. S ystems must be designed to ensure the process or is not to be subjected to an y static V CC and I CC combination wherein V CC exceeds V CC_MAX at specified ICC.
Thermal Specifications 84 Table 6-4. Quad-Core Intel® Xeon® Processor X5400 Series Ther mal Profile A Table Power (W ) T CASE_MA X ( ° C) 0 42.8 5 43.6 10 44.5 15 45.3 20 46.2 25 47.0 30 47.8 35 48.7 40 49.5 45 50.0 50 51.2 55 52.0 60 52.9 65 53.7 70 54.
85 Thermal Specifications Notes: 1. These values are specified at V CC_MAX for all processor frequencies. S ystems must be designed to ensure the processor i s not to be subjected to an y static VCC and ICC combination where in VCC exceeds V CC_MAX at specified ICC.
Thermal Specifications 86 Notes: 1. Please refer to Ta b l e 6 - 7 for discrete points that constitute the thermal profile. 2. Implementation of the Quad-Core Intel® X eon® Pr ocessor 5400 Series Thermal Profile shoul d result in virtually no TCC activ ation.
87 Thermal Specifications Notes: 1. These values are specified at V CC_MAX for all processor frequencies. S ystems must be designed to ensure the processor i s not to be subjected to an y static VCC and ICC combination where in VCC exceeds V CC_MAX at specified ICC.
Thermal Specifications 88 Notes: 1. These values are spec ified at V CC_MA X for all processor frequencies. Syst ems must be designed to en sure the processor is not to be s ubjected to any static VCC and ICC combination where in VCC exceeds V CC_MAX at specified ICC.
89 Thermal Specifications Notes: 1. Please refer to Ta b l e 6 - 1 1 for discrete points that constitute the thermal profile. 2. Implementation of the Quad-Core Intel® X eon® Processor L5408 Thermal Profile should result in virtually no TCC activ ation.
Thermal Specifications 90 6.1.2 Thermal Metrology The minimum and maximum case temper atures (T CASE ) are specified in Ta b l e 6 - 2 , Ta b l e 6 - 4 , Ta b l e 6 - 5 , and Ta b l e 6 - 7 , and Ta b l e 6 - 9 and Ta b l e 6 - 1 1 are measured at the geometric top center of the processo r integr ated heat spreader (IHS).
91 Thermal Specifications needed by modulating (starting and stopping) the internal processor core clocks. The temperature at which the Intel® Thermal Monitor 1 activ ates the thermal control circuit is not user configurable and is not software visible.
Thermal Specifications 92 The second operating po int consists of both a lower operating frequency and v oltage. The lowest operating frequency is determined by the lowest supported bus r atio (1/6 for the Quad-Core Intel® X eon® Processor 540 0 Series).
93 Thermal Specifications Series must not rely on software usage of this mechanism to limit the processor temperature. If bit 4 of the IA32_CLOCK _MODULA TION MSR is set to a ‘1’ , the processor w.
Thermal Specifications 94 6.2.5 THERMTRIP# Signal Regardless of wh ether or not Intel® Thermal Monitor 1 or Intel® Thermal Monitor 2 i s enabled, in the event of a catastrophic c ooling failure, the proce ssor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Ta b l e 5 - 1 ).
95 Thermal Specifications should utilize the relative temperature v alue de livered over PECI in conjunction with the T CONTROL MSR value to control or o ptimize fan speeds.
Thermal Specifications 96 6.3.2 PECI Specifications 6.3.2.1 PECI Device Address The PECI device address for socket 0 is 0x30 and soc ket 1 is 0x31. Please note that each address also supports two domains (Domain0 and Domain1). For more information on PECI domains, please refer to the Platform Environment Con trol Interface (PECI) Specification .
97 Features 7 Features 7.1 Power-On Configuration Options Several configur ation options can be config ured by hardware. The Quad-Core Intel® X eon® Processor 5400 Series samples its hardware configuration at reset, on the active-to-inactive tr ansition of RESET#.
Features 98 7.2.1 Normal State This is the normal operating state for the processor . 7.2.2 HALT or Extended HALT State The Extended HAL T state (C1E) is enabled via the BIOS. The Extended HALT state must be enabled for the process or to remain within its specifications.
99 Features Notes: 1. Processors runn ing in the lowest bus r atio supported as sh own in Ta b l e 2 - 1 , will enter the HAL T State whe n the processor h as executed the HAL T or MWAIT instruction since the proces sor is already operating in th e lowest core frequency and v oltage operating point.
Features 100 7.2.3 Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered no later than 20 bus clocks afte r the response phase of the processor issued Stop Grant Acknowledge special bus cycle.
101 Features While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor , and only serviced when the pr ocessor returns to the Normal state. Only one occurrence of each ev ent will be recognized upon return to the Normal state.
Features 102 Enhanced Intel SpeedStep T echnology creates processor performance states (P-states) or voltage/frequency oper ating points which are lower power capability states within the Normal state (see Figure 7-1 for the Stop Clock State Machine for supported P- states).
103 Boxed Processor Specifications 8 Boxed Processor Specifications 8.1 Introduction Intel box ed processors are intended for system integrators who build systems from components av ailable through distribution channels. The Quad-Core In tel® Xeon® Processor 5400 Series will be offered as an Intel boxed processor .
Boxed Processor Specifications 104 Figure 8-1. Boxed Quad-Core Inte l® Xeon® Processor 5400 Series 1U Passive/3U+ Active Combination Heat Sink (With Removable Fan) Figure 8-2.
105 Boxed Processor Specifications Notes: 1. The heat sinks re presented in these images are for referen ce only , and may not rep resent the final boxed processor heat s inks. 2. The screws, springs, and standoffs will be captive to the heat sink. This image shows all of the components in an exploded view.
Boxed Processor Specifications 106 Figure 8-4. Top Si de Board Keepout Zones (Part 1).
107 Boxed Processor Specifications Figure 8-5. Top Side Board Keepout Zones (Part 2).
Boxed Processor Specifications 108 Figure 8-6. Bottom Side Board Keepout Zones.
109 Boxed Processor Specifications Figure 8-7. Board Mounting-Hole Keepout Zones.
Boxed Processor Specifications 110 Figure 8-8. Volumetric Height Keep-Ins.
111 Boxed Processor Specifications Figure 8-9. 4-Pin Fan Cable Connec tor (For Active CEK Heat Sink).
Boxed Processor Specifications 112 Figure 8-10. 4-Pi n Base Board Fan Header (F or Active CEK Heat Sink).
113 Boxed Processor Specifications 8.2.2 Boxed Processo r Heat Sink Weight 8.2.2.1 Thermal Solution Weight The 1U passive/3U+ active combination heat sink solution and the 2U passive heat sink solution will not exceed a mass of 1050 grams.
Boxed Processor Specifications 114 The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. The fan power head er identification and location must be documented in the suppliers platform documentation, or on the baseboard itself .
115 Boxed Processor Specifications around the heatsink. It is assumed that a 40°C T LA is met. This requires a superior chassis design to limit the T RISE at or below 5°C with an external ambient temper ature of 35°C. These specifications apply to both coppe r and aluminum heatsink solutions.
Boxed Processor Specifications 116 §.
117 Debug Tools Specifications 9 Debug Tools Specifications Please refer to the appropriate platform de sign guidelines for information regarding debug tool specifications.
Debug Tools Specifications 118 9.3.1 Mechanical Considerations The LAI is installed between the processor so cket and the pro cessor . The LAI plugs into the socket, while the processor plugs into a socket on th e LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer .
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Als u nog geen Intel Xeon E5450 heb gekocht dan nu is een goed moment om kennis te maken met de basisgegevens van het product. Eerst kijk dan naar de eerste pagina\'s van de handleiding, die je hierboven vindt. Je moet daar de belangrijkste technische gegevens Intel Xeon E5450 vinden. Op dit manier kan je controleren of het apparaat aan jouw behoeften voldoet. Op de volgende pagina's van de handleiding Intel Xeon E5450 leer je over alle kenmerken van het product en krijg je informatie over de werking. De informatie die je over Intel Xeon E5450 krijgt, zal je zeker helpen om een besluit over de aankoop te nemen.
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Maar de belangrijkste taak van de handleiding is om de gebruiker bij het oplossen van problemen te helpen met Intel Xeon E5450 . Bijna altijd, zal je daar het vinden Troubleshooting met de meest voorkomende storingen en defecten #MANUAl# samen met de instructies over hun opplosinge. Zelfs als je zelf niet kan om het probleem op te lossen, zal de instructie je de weg wijzen naar verdere andere procedure, bijv. door contact met de klantenservice of het dichtstbijzijnde servicecentrum.
