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ARM DUI 0125A ARM Integrator/CM940T User Guide.
ii © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A ARM Integrator/CM940T User Guide © Copyri ght ARM L im ite d 199 9. All rights reserve d. Release information Proprietary notice ARM, the A RM Powe re d lo go, Thumb an d StrongARM are reg istered trad emarks of ARM Limited.
ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. iii Electromagnetic conformity This section contains electromagnetic conformity (EMC) no tices. Federal Communications Commiss ion Notice NOTE: This equipment has been tested and found to comply with the limits for a class A digital device, p ursuant to par t 15 of the FCC r ules.
iv © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A.
ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. v Contents ARM Integrator/CM9 40T Use r Guide Electromagn etic conf ormity ................ ............ ........... ........... ................. ........... ........... ... iii Prefac e About this docume nt .
vi © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.5 Reset c ontroller ..................... ........... ............ ........... ........... ................. ......... 3-8 3.6 System bus br idge ...... ........... ..............
ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. vii Preface This preface introdu ces the ARM Integrator/CM940T co re module and its refer ence documentatio n. It contains the following sections : • About this documen t on page viii • Further r eading on page x • Feedback on page xi.
viii © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A About this document This documen t desc ribes ho w to se t up and u se th e ARM Integrat or/CM9 40T core module.
ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. ix T ypographical conventions The following typo graphical conventio ns are used in this do cument: bold Highlights ARM processor signal names within text, and interface elements such as menu names.
x © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A Further reading This section lis ts related publications by ARM Lim ited and other compan ies th at may provide addit ional in for mation.
ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. xi Feedback ARM Lim ited welcomes feedback both on the ARM Integrator/CM940T co re mod ule and on the do cumentation. Feedback on this document If you hav e any comment s about this docum ent, please send email to errata@arm.
xii © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A.
ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 1-1 Chapter 1 Introduction This chapter introduces the ARM Integrator/CM940T core mo dule.
Introduction 1-2 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 1.1 About the ARM Integrator/CM940T core module The Integrator/CM94 0 T core module provides you with the b asis of a flexible developmen t system whi ch can be used in a number of different ways .
Introduction ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 1-3 Figure 1-1 Inte grator/CM940T l ayout Multi-ICE connector Po w e r connector Processor core Reset button DIMM sock et.
Introduction 1-4 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 1.2 ARM Integrator/CM940T overview The major compo nents on the core mo dule are as follows: • ARM940T m icropr oc.
Introduction ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 1-5 1.2.2 Core module FPGA The FPGA provides system control functions for the core module, enabling it to operate as a standalone development system or attached to a motherboar d.
Introduction 1-6 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A Status and configuration space The status and configuration space co ntains status and configuration registers for the core module.
Introduction ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 1-7 1.2. 5 Mult i - ICE co nnec to r The Multi-ICE conn ector enables JTAG hardwar e debuggin g equipment, such as Multi-ICE, to be con nected to the core module.
Introduction 1-8 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 1.3 Links and indi cators The core modu le provides one link an d four su rface-mounted LEDs. Th ese are illustrated in Figure 1-3. Figure 1-3 Li nks and indicato rs 1.
Introduction ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 1-9 1.3.2 LED indicators The functio ns of the four surface-mo unted LEDs are summarized in Table 1- 1. Table 1-1 LE D funct ional summa ry Name Color Function MISC Green This LED is controll ed via the control regi ster (see CM_C TR L (0x1 00 0000C) on page 4- 1 1).
Introduction 1-10 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 1.4 T est points The core modu le pro vides two gr ound and f ive signal t est poin ts as an aid to debug . These are illustrated in Figure 1-4 . Figure 1-4 T est points The functions of th e test points are summarized in Table 1 -2.
Introduction ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 1-11 1.5 Precautions This section contains safety information and advice on how to avoid damage to the core module. 1.5.1 E nsuring safety Warning To avoid a safety hazard, only Safety Extra Lo w Voltage (SELV) equipment s ho uld be connected to the JTAG interface.
Introduction 1-12 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A.
ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 2-1 Chapter 2 Gett ing Sta r te d This chapter describes how to set up and prepare the ARM Integrato r/CM940T core module for use.
Getting Started 2-2 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 2.1 Setting up a standalone ARM Integrator/CM940T To set up the core module a s a standalone develop ment system: 1. Optionally , fit an SD RAM DIMM. 2. Suppl y po wer .
Getting Started ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 2-3 2.1.3 S upplying power When using the core modul e as a st andalon e de vel opm ent s ys tem, y ou should conn ect a bench power supp ly with 3 .3V and 5V outputs to the p ower connect or, as i llustrated in Figu re 2-1.
Getting Started 2-4 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 2.1.4 Connecting Multi-ICE When you ar e using th e core mod ule as a stan dalone system , Multi-IC E debugg ing equipment can be u sed to download pr ograms. The Mu lti-ICE setup for a standalone cor e modu le is show n in F igur e 2-2 .
Getting Started ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 2-5 2.2 Attaching the ARM Integrator/CM940T to a m otherboard Attach the core modu le onto a moth erboard ( for exampl.
Getting Started 2-6 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 2.2.1 Core module ID The ID of the core module is configured autom atically by the connectors (there are no links.
ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-1 Chapter 3 Hardware Description This chapter describes the on- board hardware. It contains the following sections: • ARM940T micr.
Hardware Description 3-2 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.1 ARM9 40T microproc es sor co re The ARM940T cached pr ocessor macrocell is a member of the ARM9 Thumb family of high- performan ce 32-bit system-on -a-chip pr ocesso rs.
Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-3 3.2 SS RAM co ntroller The SSRAM controller is impl emented in a Xilinx 9572 PLD which enables the SSRAM to achieve single-cycle operation.
Hardware Description 3-4 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.3 Core module FPGA The core modu le FPGA contains five main functional blocks: • SDRAM contr oller on pa.
Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-5 At power-up the FPGA lo ads its co nfigurati on data fr om a flash memory devi ce. Parallel data from the flash is serialized by the Programmable L ogic Device (PLD) into the configu r atio n inputs of the FPGA.
Hardware Description 3-6 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.4 SDRAM controlle r The core modu le pro vides supp ort fo r a single 16, 32, 64, 128, or 25 6MB SDRA M DIMM. 3.4.1 SDRAM operati ng mode The operating mode of the SDRAM devices is controlled with the mode set reg ister within each SDRAM.
Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-7 a 64 x 32-bit area of memor y (CM_SPD) within the SDRAM controller. The SPD flag is set in the SDRAM contro l regis ter (CM_SDRAM) when the SPD data is available.
Hardware Description 3-8 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.5 Rese t controller The core mod ule FPGA incorporates a reset contr oller which enables the co re module to be reset as a standalone uni t or as part of an Integrator de velopment system.
Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-9 3.5.1 Reset si gnals Table 3-1 describes t he external res et signal s. Table 3- 1 Reset signal d escription s Name Description T ype Function BnRES_M Processor r eset Output The BnRES_ M signal is u sed to reset the pr ocessor core.
Hardware Description 3-10 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.5.2 Software r esets The core module FPGA prov ides a software reset which can be trigg ered by writi ng to the reset bit in the CM _CTRL register.
Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-11 3.6 System bus bridge The system bus bridge provides an asynchrono us bus interface between the local system bus and s ystem bu s connect ing the mother board and o ther mo dules.
Hardware Description 3-12 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A Write transactions from the processor to the system bus normally complete o n the local memory bus in a single cycle.
Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-13 3.6.2 Motherboard a ccesses to SDR AM The second FIFO supports read and write accesses by system bus masters on the motherboard a nd other co re modules to the local co re module m emory.
Hardware Description 3-14 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A System bus reads The data routing for sy stem bus reads from SDRAM is illust rated in Figure 3-7.
Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-15 3.6.4 System bus signal routing The core module is mounted onto a motherboar d via the connectors HDRA and HDRB.
Hardware Description 3-16 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A The example in Figure 3-8 illustrates how a group o f four signals (labelled A, B, C, and D) are routed throu gh a group of four con nector pins u p through t he stack.
Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-17 3.7 Clock generators The core modu le provides its own cloc k generators an d operates asynchron ously with the mo therbo ard.
Hardware Description 3-18 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.7.1 Processor core clock (CO RECLK) The frequency of CORECLK is controllable in 1MHz steps in the range 12MHz to 160MHz.
Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-19 3.7.2 Processor bus cloc ks (LCLK and nLC LK) The frequency of the pr ocessor bus clocks LCL K and nLCLK is determined by the frequency of 2XCLK . The clock sign al 2XCLK is div ided by 2 by the SS RAM controller PLD to produce LCLK and nLCLK .
Hardware Description 3-20 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A The LCLK clock si gnal is b uffered b y a 5-ou tput l ow-ske w buf fer PI49F CT3805 to drive five loads. These ar e: • SDRAM_CLK[3:0] •S S R A M _ C L K .
Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-21 3.8 Multi-I CE support The core modu le provi des support for debug using JTAG. It pro vides a Multi -ICE connector and JTAG scan path s around the develo pment syst em.
Hardware Description 3-22 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 3.8.1 JT AG scan path Figure 3 -11 shows a simpli fied di agram of the scan pat h.
Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-23 3.8.2 De bugging modes The core modu le is capable of operating in two modes: • normal debug mode • confi guratio n mode. Normal debug mode During normal operation and software develop ment, the core module operates in debug mode.
Hardware Description 3-24 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A The configuration mod e allows FPGA and PLD code to be updated as follows: • The FPGAs are volatile, bu t load their configuratio n from flash memory .
Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-25 Table 3-4 J TAG signal descriptio n Name Description Function DBGR Q Debu g req ue s t (from JT AG equipment) DBGRQ is a request for the proc essor core to enter th e deb ug state.
Hardware Description 3-26 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A RTCK Return TCK (to JT AG equi pment) Some devi ces samp le TCK (for example a synthesizable core with only on e clock), and th is has the effect of delayin g t he t i me at which a com ponent ac t ually capture s data.
Hardware Description ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 3-27 3.8.4 Debug communications interrupts The ARM940T processo r core incorpo rates EmbeddedICE h ardware and provides a debug commu nications data regi ster which i s used to pass dat a between the processo r and JTAG equipment.
Hardware Description 3-28 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A.
ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-1 Chapter 4 Programmer’s Reference This chapter describes the memory map and the status and control registers.
Programmer’s R eference 4-2 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.1 Memory organization This section d escribes the memory map. Fo r a st and alone core module, the memo ry map is limited to local SS RAM, SD RAM, and core module regis ters.
Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-3 Motherboard detect The nMBDET signal operates as follows: nMBDE T =0 T he core module is attached to a motherboard, and accesses in the address range 0x0 t o 0x3FF FF t o the boot ROM or SS RAM are controlled by the REMAP bit.
Programmer’s R eference 4-4 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.1.3 SDRAM acc esses The Integrator mem ory map prov ides a 256MB addr ess space for SDRAM. When a smaller sized S DRAM DIMM is fitted, it i s mapped repeatedly to fill the 25 6MB space.
Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-5 System bus acc esses to SDRAM If the core mod ule is mounted on a motherboard, the SDRAM is mapped to ap pear at the aliased mo dule memory region of t he combine d Integrator s ystem bus memo ry map.
Programmer’s R eference 4-6 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.2 Exception vect or mapping The convention f or ARM cores is to ma p the exception vector s to begin at add ress 0.
Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-7 4.3 Core m odule regist ers The core modu le status and control r egisters allow the processor to deter mine its environment and to control some core module operations.
Programmer’s R eference 4-8 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.3.1 CM_ID (0x10 000 000) The core module ID register (CM_ID) is a read- only register that identifies the bo ard manufacturer , board type, and r evis ion.
Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-9 4.3.3 CM_OSC (0 x10 000 008) The core module oscillator register (CM_OSC) is a read/write register that controls the frequ ency of the clo cks gene rated by the two clo ck ge nerators (see C lock generato rs on page 3- 17).
Programmer’s R eference 4-10 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 1 1 Reserved Use read-modify-write to preserv e value.
Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-11 4.3.4 CM_CTRL (0x1000 000C) The core modu le control register (CM_CTRL) is a read/write re gister that pro vides control of a nu mber of user-configurable f eatures of the core mo dule.
Programmer’s R eference 4-12 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.3.5 CM_ST A T (0x 10000010) The core modu le statu s re gister (CM_STAT) is a read -on l y r egister that can be read to determine where in a mu lti-core modu le stack this core m odule is positioned.
Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-13 4.3.6 CM_LOCK (0x1 0000014) The core modu le lock register (CM_LOCK) is a read/write register that is used to control access to the CM_OSC register , allowing it to be lo cked and unlocked.
Programmer’s R eference 4-14 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.3.7 CM_SDRAM (0x10 000 020) The SDRAM status and co ntrol register ( CM_SDRAM) is a read/write r egister used to set the configuration parameters fo r the SDRAM DIMM.
Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-15 Note Before the SDRAM is used it is necessary to read the SPD memory and p rogram the CM_SDRAM register with the parameters indicated in Table 4-8. If these valu es are not correctly set then SDRAM accesses may be slow or unreliable.
Programmer’s R eference 4-16 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.3.8 CM_SPD (0x10 0001 00 to 0x100001 FC) This area of memory contain s a copy of the SPD data from the SPD EEPROM on the DIMM.
Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-17 Example 4-1 CM_BASE EQU 0x10000000 ; base address of Core Module registers SPD_BASE EQU 0x10000100 ; ba.
Programmer’s R eference 4-18 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A not64 CMP r5,#0x80 ; is it 128MB? BNE not128 ; if no, move on MOV r6,#0xe ; store size and CAS latency of 2 B writesize not128 ; if it is none of these sizes then it is either 256MB, or ; there is no SDRAM fitted so default to 256MB.
Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-19 4.4 Interrupt register s The core module provides a 3-bit IRQ co ntroller and 3-bit F IQ controller to su pport the debug commu nications channel u sed for passin g informat ion between applicati ons software and the debu gger.
Programmer’s R eference 4-20 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A Figure 4-4 I nterrupt contro l 4.4.1 CM_IRQ_ ST A T (0x10000040 )/CM_FIQ_ST A T (0x1 0000060) The status register con tains the logical AND of the bits in the raw status register and the enable register.
Programme r’s Reference ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. 4-21 4.4.4 CM_IRQ_ENCLR( 0x1000004 C)/CM_FIQ_ENC LR (0x10000 06C) The clear set locations are used to set bi.
Programmer’s R eference 4-22 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A 4.4.6 CM_SOF T_I NTSET (0x10000 050)/CM_SO F T_ INTCL T (0x10000 054) The core module interrupt controller provides a register for controllin g and clearing software interrupts.
ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. A-1 Appendix A Signal Descriptions This index prov ides a summary of signals present on the cor e module main co nnectors. It contains the follo wing secti ons: • HDRA on page A-2 • HDRB on page A-4.
Signal Descriptions A-2 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A A.1 HDRA Figure A-1 shows th e pin number s of th e HDRA plug and s ocket. All pins on the HDRA socket are connected to the correspon ding pins on the HDRA p lug.
Signal Descriptions ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. A-3 The signals presen t on th e pins labeled A[31:0], B[31:0] , and C[31:0] are described in Table A-1. Note Table A-1 s hows signal descr iptio ns for an AMB A ASB bus i mplement ation .
Signal Descriptions A-4 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A A.2 HDRB The HDRB plug an d socket have sli ghtly differ ent pin outs, as des cribed belo w. A.2.1 HDRB socket pinout Figure A-2 s hows the p in numbe rs of th e socket HDRB on the under side of th e core module, viewed from ab ove the core module.
Signal Descriptions ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. A-5 A.2.2 HDRB plug pinout Figur e A-3 shows t he pin number s of th e HDRB plug on the t op of th e core modul e.
Signal Descriptions A-6 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A A.2.3 Through-board signal connections The signals on the pins labeled E[31:0] are cross-connected between the plug and socket so that the signals are rotated through the stack in groups of four.
Signal Descriptions ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. A-7 A.2.4 HDRB signal descriptions Table A-3 des cribes t he sig nals on t he pins labeled E[31:0], F[31: 0], and G[1 5:0].
Signal Descriptions A-8 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A Note Table A-3 shows signal descri ptions for an AMBA ASB bus imp lementati on. G4 TCK JT AG test clock G[3:1] MASTER[2: 0] Master ID. Binary enco ding of the mast er current ly perfo r ming a tra nsfer on th e bus.
ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. B-1 Appendix B Spe cifica tions This appendix contains the specifications fo r the ARM Integrator/CM940 T core module. It contains th e followin g sections: • Electrical sp ecification on page B-2 • T iming specification on page B-3 • Mechanic al d etails on page B-4.
Specifications B-2 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A B.1 Electrical spec ification Table B-1 shows the core module electrical characteristics for the system bus interface. The core modu le uses 3.3V and 5 V source. The 1 2V inputs are supplied by the motherboard b ut not used by the core modu le.
Specifications ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. B-3 B.2 T iming speci ficat ion Table B-2 provides the operating timing characteristics for the system bus interface signals.
Specifications B-4 © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A B.3 Mechanical details The core module i s designed to be stackable on a num ber of different mothe rboards. Its size allows it to be m ounted onto a CompactPC I motherboard while allowin g the motherboard to be installed in a card cage.
ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. Index-i Index The items in this index are listed in alphab etic order, with symbols and numerics appear ing at the end.
Index Index-ii © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A Connect ors HDRA and HDRB 1-3 Multi-ICE 2-4 power 2-3 Contro ller clock 1-6, 3 -17 reset 1-5, 3-8 SDRAM 1-5, 3-6 SSRAM.
Index ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved. Index-iii SDRAM op erating mo de 3-6 SDRAM re pe at mapp ing 4-4 SDRAM st atus and co ntrol regi ster 4 -14 SDRAM, SPD memory 4-.
Index Index-iv © Copyright ARM Limited 1999. All rights res erved. ARM DUI 0125A.
Een belangrijk punt na aankoop van elk apparaat ARM CM940T (of zelfs voordat je het koopt) is om de handleiding te lezen. Dit moeten wij doen vanwege een paar simpele redenen:
Als u nog geen ARM CM940T heb gekocht dan nu is een goed moment om kennis te maken met de basisgegevens van het product. Eerst kijk dan naar de eerste pagina\'s van de handleiding, die je hierboven vindt. Je moet daar de belangrijkste technische gegevens ARM CM940T vinden. Op dit manier kan je controleren of het apparaat aan jouw behoeften voldoet. Op de volgende pagina's van de handleiding ARM CM940T leer je over alle kenmerken van het product en krijg je informatie over de werking. De informatie die je over ARM CM940T krijgt, zal je zeker helpen om een besluit over de aankoop te nemen.
In een situatie waarin je al een beziter van ARM CM940T bent, maar toch heb je de instructies niet gelezen, moet je het doen voor de hierboven beschreven redenen. Je zult dan weten of je goed de alle beschikbare functies heb gebruikt, en of je fouten heb gemaakt die het leven van de ARM CM940T kunnen verkorten.
Maar de belangrijkste taak van de handleiding is om de gebruiker bij het oplossen van problemen te helpen met ARM CM940T . Bijna altijd, zal je daar het vinden Troubleshooting met de meest voorkomende storingen en defecten #MANUAl# samen met de instructies over hun opplosinge. Zelfs als je zelf niet kan om het probleem op te lossen, zal de instructie je de weg wijzen naar verdere andere procedure, bijv. door contact met de klantenservice of het dichtstbijzijnde servicecentrum.
