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User’s Manual Printed in Japan © µ PD78058F , 78058FY Subseries 8-Bit Single-Chip Microcontrollers µ PD78056F µ PD78058F µ PD78P058F µ PD78058F(A) µ PD78056FY µ PD78058FY µ PD78P058FY µ PD78058FY(A) Document No.
2 [MEMO].
3 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
4 The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country.
5 NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.
6 MAJOR REVISIONS IN THIS EDITION Page Major Revision from Previous Edition Throughout The following products have already been developed: µ PD78056FGC- ××× -8BT, 78058FGC- ××× -8BT, 78P058FGC-8BT, 78056FYGC- ××× -8BT, 78058FYGC- ××× -8BT P133 to The block diagrams of the following ports were changed.
7 PREFACE Readers This manual has been prepared for user engineers who want to understand the functions of the µ PD78058F and 78058FY Subseries and design and develop its application systems and programs. Affected versions are each of the versions in the following Subseries.
8 How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. For persons who use this manual as the manual for the µ PD78058F(A) and 78058FY(A), → The µ PD78058F and 78058FY differ from the µ PD78058F(A) and 78058FY(A) only in their quality grades.
9 Chapter Organization This manual divides the descriptions for the µ PD78058F and 78058FY Subseries into different chapters as shown below. Read only the chapters related to the device you use.
10 Differences between µ PD78058F and µ PD78058FY Subseries: The µ PD78058F and µ PD78058FY Subseries are different in the following functions of the serial interface channel 0.
11 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
12 Development Tool Documents (User’s Manuals) Document Name Document No. Japanese English RA78K0 Assembler Package Operation U11802J U11802E Assembly language U11801J U11801E Structured assembler l.
13 Documents for Embedded Software (User’s Manual) Document Name Document No. Japanese English 78K/0 Series Real-Time OS Basics U11537J U11537E Installation U11536J U11536E OS for 78K/0 Series MX78K0 Basics U12257J U12257E Other Documents Document Name Document No.
14 [MEMO].
15 CONTENTS CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) ............................................................................. 35 1.1 Features ......................................................................................................
16 3.2.14 A V SS .............................................................................................................................................. 71 3.2.15 RESET ...........................................................................
17 5.2.1 Control registers ........................................................................................................................... 103 5.2.2 General registers ........................................................................
18 7.4.2 Subsystem clock oscillator ........................................................................................................... 162 7.4.3 Scaler ..........................................................................................
19 CHAPTER 11 WATCHDOG TIMER ..................................................................................................... . 245 11.1 Watchdog Timer Functions ....................................................................................
20 16.4.3 SBI mode operatio n ................................................................................................................ . 305 16.4.4 2-wire serial I/O mode operatio n .............................................................
21 21.2 Interrupt Sources and Configuration ................................................................................. 478 21.3 Interrupt Function Control Registers ...............................................................................
22 26.3.3 PROM read procedur e ........................................................................................................... . 546 26.4 Screening of One-Time PROM Version s ................................................................
23 LIST OF FIGURES (1/8) Figure No. Title Page 3-1 List of Pin Input/Output Circuit .......................................................................................................... 75 4-1 List of Pin Input/Output Circuit ....................
24 LIST OF FIGURES (2/8) Figure No. Title Page 7-4 Oscillation Mode Selection Register Format .................................................................................. ... 159 7-5 Main System Clock W aveform due to Writing to OSMS ...........
25 LIST OF FIGURES (3/8) Figure No. Title Page 8-31 Control Register Settings for One-Shot Pulse Output Operation Using Software T rigger ................ 204 8-32 T iming of One-Shot Pulse Output Operation Using Software T rigger ....................
26 LIST OF FIGURES (4/8) Figure No. Title Page 14-1 A/D Converter Block Diagram ........................................................................................................... 263 14-2 A/D Converter Mode Register Format ...................
27 LIST OF FIGURES (5/8) Figure No. Title Page 16-27 Address T ransmission from Master Device to Slave Device (WUP = 1) .......................................... 325 16-28 Command T ransmission from Master Device to Slave Device .....................
28 LIST OF FIGURES (6/8) Figure No. Title Page 18-5 Automatic Data T ransmit/Receive Interval Specify Register Format ................................................ 395 18-6 3-Wire Serial I/O Mode T imings ...........................................
29 LIST OF FIGURES (7/8) Figure No. Title Page 20-4 Real-time Output Port Mode Register Format ................................................................................. . 474 20-5 Real-time Output Port Control Register Format .................
30 25-1 Block Diagram of ROM Correction ................................................................................................... 527 25-2 Correction Address Registers 0 and 1 Format ..........................................................
31 1-1 Differences Between the µ PD78058F and µ PD78058F(A) .............................................................. 45 1-2 Mask Options of Mask POM V ersions ....................................................................................
32 LIST OF TABLES (2/3) Table No. Title Page 9-10 Square-W ave Output Ranges When 2-Channel 8-Bit T imer/Event Counters (TM1 and TM2) are Used as 16-Bit T imer/Event Counter ................................................................ 234 10-1 Interval T imer Interval T ime .
33 LIST OF TABLES (3/3) Table No. Title Page 20-2 Operation in Real-time Output Buffer Register Manipulation ............................................................ 473 20-3 Real-time Output Port Operating Mode and Output T rigger ...............
34 [MEMO].
35 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) 1.1 Features Compared to the conventional µ PD78054 Subseries, EMI (Electro Magnetic Interference) noise has been reduced.
36 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) 1.2 Applications In the case of the µ PD78056F, 78058F and 78P058F, Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPC’s, fuzzy home appliances, vending machines, etc.
37 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) 1.4 Quality Grade Part Number Package Quality Grade µ PD78056FGC- ××× -3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Standard µ PD78056FGC- ××× -8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
38 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) 1.5 Pin Configuration (Top View) (1) Normal operating mode 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µ PD78056FGC- ××× -3B9, 78058FGC- ××× -3B9, 78058FGC(A)- ××× -3B9, 78P058FGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
39 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) Pin Identifications A8 to A15 : Address Bus AD0 to AD7 : Address/Data Bus ANI0 to ANI7 : Analog Input ANO0, ANO1 : Analog Output ASCK : Asynchronous Seria.
40 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) (2) PROM programming mode 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µ PD78P058FGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) µ PD78P058FGC-8BT Cautions 1. (L) : Connect independently to V SS via a pull-down resistor.
41 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) 1.6 78K/0 Series Expansion The 78K/0 Series expansion is shown below. The names in frames are subseries. Note Under planning PD780964 PD78098 80-pin IEBus controller was added to the PD78054 PD78044F 80-pin Basic subseries for driving FIP.
42 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) The differences between the major functions of each subseries are shown below. Function ROM Timer 8-bit 10-bit 8-bit Serial Interface I/O V DD External Subseries Capacity 8-bit 16-bit Watch WDT A/D A/D D/A MIN.
43 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) 1.7 Block Diagram Remarks 1. The internal ROM and RAM capacities depend on the product. 2. Pin connection in parentheses is intended for the µ PD78P058F.
44 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) 1.8 Outline of Function ROM Mask ROM PROM 48 Kbytes 60 Kbytes 60 Kbytes Note 1 High-speed RAM 1024 bytes 1024 bytes Note 1 Buffer RAM 32 bytes Expansion RAM None 1024 bytes 1024 bytes Note 2 Memory space 64 Kbytes General register 8 bits × 8 × 4 banks With main system clock selected 0.
45 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 KHz, 9.8 kHz (main system clock at 5.0-MHz operation) Vectored Maskable Internal: 13 interrupt External: 7 sources Non-maskable Internal: 1 Software 1 Test input Internal: 1 External: 1 Supply voltage V DD = 2.
46 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) 1.10 Mask Options There are mask options in the mask ROM versions ( µ PD78056F, 78058F). By specifying the mask option when ordering, you can have the pull-up resistors shown in Table 1-2 incorporated on-chip.
47 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) 2.1 Features Compared to the conventional µ PD78054Y Subseries, EMI (Electro Magnetic Interference) noise has been reduced. On-chip high-capacity ROM and RAM Notes 1. The capacities of internal PROM and internal high-speed RAM can be changed by means of the memory size switching register (IMS).
48 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) 2.2 Applications In the case of the µ PD78056FY, 78058FY and 78P058FY, Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc.
49 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) 2.4 Quality Grade Part Number Package Quality Grade µ PD78056FYGC- ××× -3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Standard µ PD78056FYGC- ××× -8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
50 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) 2.5 Pin Configuration (Top View) (1) Normal operating mode 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µ PD78056FYGC- ××× -3B9, 78058FYGC- ××× -3B9, 78058FYGC(A)- ××× -3B9, µ PD78P058FYGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
51 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) Pin Identifications A8 to A15 : Address Bus AD0 to AD7 : Address/Data Bus ANI0 to ANI7 : Analog Input ANO0, ANO1 : Analog Output ASCK : Asynchronous Seri.
52 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) (2) PROM programming mode 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µ PD78P058FYGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) µ PD78P058FYGC-8BT Note Note Under development Cautions 1.
53 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) 2.6 78K/0 Series Expansion The 78K/0 Series expansion is shown below. The names in frames are subseries. Note Under planning PD780964 PD78098 80-pin IEBus controller was added to the PD78054 PD78044F 80-pin Basic subseries for driving FIP.
54 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) The differences between the major functions of each subseries are shown below. Function ROM Serial Interface I/O V DD Subseries Capacity MIN. Value Control µ PD78078Y 48 K to 60 K 3-wire/2-wire/I 2 C : 1 ch 88 1.
55 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) 2.7 Block Diagram Remarks 1. The internal ROM and RAM capacities depend on the product. 2. Pin connection in parentheses is intended for the µ PD78P058FY.
56 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) 2.8 Outline of Function ROM Mask ROM PROM 48 Kbytes 60 Kbytes 60 Kbytes Note 1 High-speed RAM 1024 bytes 1024 bytes Note 1 Buffer RAM 32 bytes Expansion RAM None 1024 bytes 1024 bytes Note 2 Memory space 64 Kbytes General register 8 bits × 8 × 4 banks With main system clock selected 0.
57 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) Vectored Maskable Internal: 13 interrupt External: 7 sources Non-maskable Internal: 1 Software 1 Test input Internal: 1 External: 1 Supply voltage V DD = 2.7 to 6.0 V Operating ambient temperature T A = –40 to +85 ° C Package • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.
58 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) 2.10 Mask Options The mask ROM versions ( µ PD78056FY, 78058FY) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for the device production.
59 Pin Name Input/Output Function After Reset Alternate Function P00 Input Port 0. Input only Input INTP0/TI00 P01 Input/ 8-bit input/output port. Input/output mode can be specified Input INTP1/TI01 P02 output bit-wise. INTP2 P03 If used as an input port, an on-chip INTP3 P04 pull-up resistor can be used by INTP4 P05 software.
60 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) (1) Port pins (2/3) Pin Name Input/Output Function After Reset Alternate Function P30 Input/ Port 3. Input TO0 P31 output 8-bit input/output port. TO1 P32 Input/output mode can be specified bit-wise. TO2 P33 If used as an input port, an on-chip pull-up resistor can be used by TI1 P34 software.
61 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) (1) Port pins (3/3) Pin Name Input/Output Function After Reset Alternate Function P120 to P127 Input/ Port 12. Input RTP0 to RTP7 output 8-bit input/output port. Input/output mode can be specified bit-wise.
62 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) (2) Non-port pins (1/2) Pin Name Input/Output Function After Reset Alternate Function INTP0 Input External interrupt request inputs with specifiable valid edges (rising Input P00/TI00 INTP1 edge, falling edge, both rising and falling edges).
63 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) (2) Non-port pins (2/2) Pin Name Input/Output Function After Reset Alternate Function AD0 to AD7 Input/Output Low-order address/data bus when expandi.
64 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) 3.1.2 PROM programming mode pins (PROM versions only) Pin Name Input/Output Function RESET Input PROM programming mode setting. When +5 V or +12.5 V is applied to the V PP pin or a low level voltage is applied to the RESET pin, the PROM programming mode is set.
65 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) 3.2 Description of Pin Functions 3.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function a.
66 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) 3.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified bit-wise.
67 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) (d) BUSY Serial interface automatic transmit/receive busy input pins (e) STB Serial interface automatic transmit/receive strobe output pins Caution When this port is used as a serial interface pin, the I/O and output latches must be set according to the function the user requires.
68 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) 3.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus. The test input flag (KRIF) can be set to 1 by detecting a falling edge.
69 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 6 (PM6). P60 to P63 are N-ch open drain outputs. Mask ROM version can contain pull-up resistors with the mask option.
70 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) 3.2.9 P120 to P127 (Port 12) These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port. The following operating modes can be specified bit-wise.
71 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) 3.2.13 AV DD This is the analog power supply pin of the A/D converter and the port’s power supply pin. Always use the same voltage as that of the V DD pin even when the A/D converter is not used. 3.
72 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) 3.2.21 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the µ PD78058F Subseries at delivery. Connect it directly to the V SS with the shortest possible wire in the normal operating mode.
73 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) Pin Name Input/Output Input/Output Recommended Connection of Unused Pins Circuit Type P00/INTP0/TI00 2 Input Connect to V SS . P01/INTP1/TI01 8-D Input/output Connect independently via a resistor to V SS.
74 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) Table 3-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/Output Input/Output Recommended Connection of Unused Pins Circuit Type P60 to P63 (Mask ROM version) 13-I Input/output Connect independently via a resistor to V DD .
75 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) Figure 3-1. List of Pin Input/Output Circuit (1/2) IN pull-up enable AV DD P-ch IN/OUT input enable output disable data AV DD P-ch N-ch Type 2 Type 5.
76 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) Figure 3-1. List of Pin Input/Output Circuit (2/2) Type 12-B Type 13-H Type 13-I output disable AV DD N-ch IN/OUT RD medium breakdown input buffer da.
77 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) 4.1 Pin Function List 4.1.1 Normal operating mode pins (1) Port pins (1/3) Pin Name Input/Output Function After Reset Alternate Function P00 Input Port 0. Input only Input INTP0/TI00 P01 Input/ 8-bit input/output port.
78 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) N-ch open drain input/output port. On-chip pull-up resistor can be specified by mask option. (Mask ROM version only). LEDs can be driven directly. (1) Port pins (2/3) Pin Name Input/Output Function After Reset Alternate Function P30 Input/ Port 3.
79 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) (1) Port pins (3/3) Pin Name Input/Output Function After Reset Alternate Function P120 to P127 Input/ Port 12. Input RTP0 to RTP7 output 8-bit input/output port. Input/output mode can be specified bit-wise.
80 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) (2) Non-port pins (1/2) Pin Name Input/Output Function After Reset Alternate Function INTP0 Input External interrupt request inputs with specifiable valid edges (rising Input P00/TI00 INTP1 edge, falling edge, both rising and falling edges).
81 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) (2) Non-port pins (2/2) Pin Name Input/Output Function After Reset Alternate Function AD0 to AD7 Input/Output Low-order address/data bus when expand.
82 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) 4.1.2 PROM programming mode pins (PROM versions only) Pin Name Input/Output Function RESET Input PROM programming mode setting. When +5 V or +12.5 V is applied to the V PP pin or a low level voltage is applied to the RESET pin, the PROM programming mode is set.
83 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) 4.2 Description of Pin Functions 4.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function .
84 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) 4.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified bit-wise.
85 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) 4.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output, and buzzer output. The following operating modes can be specified bit-wise.
86 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) 4.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus. The test input flag (KRIF) can be set to 1 by detecting a falling edge.
87 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) 4.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified bit-wise.
88 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) 4.2.9 P120 to P127 (Port 12) These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port. The following operating modes can be specified bit-wise.
89 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) 4.2.13 AV DD This is the analog power supply pin of the A/D converter and the port’s power supply pin. Always use the same voltage as that of the V DD pin even when the A/D converter is not used. 4.
90 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) V SS IC As short as possible 4.2.21 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the µ PD78058FY Subseries at delivery. Connect it directly to the V SS with the shortest possible wire in the normal operating mode.
91 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) Pin Name Input/Output Input/Output Recommended Connection of Unused Pins Circuit Type P00/INTP0/TI00 2 Input Connect to V SS . P01/INTP1/TI01 8-D Input/output Connect independently via a resistor to V SS.
92 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) Table 4-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/Output Input/Output Recommended Connection of Unused Pins Circuit Type P60 to P63 (Mask ROM version) 13-I Input/output Connect independently via a resistor to V DD .
93 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) Figure 4-1. List of Pin Input/Output Circuit (1/2) IN pullup enable AV DD P-ch IN/OUT input enable output disable data AV DD P-ch N-ch Type 2 Type 5.
94 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) Figure 4-1. List of Pin Input/Output Circuit (2/2) Type 12-B Type 13-H Type 13-I output disable AV DD N-ch IN/OUT RD medium breakdown input buffer d.
95 CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces 64-Kbyte memory spaces can be accessed in the µ PD78058F, 78058FY Subseries. Figures 5-1 to 5-3 show memory maps.
96 CHAPTER 5 CPU ARCHITECTURE Figure 5-2. Memory Map ( µ PD78058F, 78058FY) Note When internal ROM size is 60 Kbytes, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal ROM size to less than 56 Kbytes by the memory size switching register (IMS).
97 CHAPTER 5 CPU ARCHITECTURE Figure 5-3. Memory Map ( µ PD78P058F, µ PD78P058FY) Note When internal PROM size is 60 Kbytes, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal PROM size to less than 56 Kbytes by the memory size switching register (IMS).
98 CHAPTER 5 CPU ARCHITECTURE 5.1.1 Internal program memory space The µ PD78056F and µ PD78056FY are Mask ROM with a 49152 x 8 bit configuration, the µ PD78058F and µ PD78058FY are Mask ROM with a 61440 x 8 bit configuration and the µ PD78P058F and µ PD78P058FY are PROM with a 61440 x 8 bit configuration.
99 CHAPTER 5 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
100 CHAPTER 5 CPU ARCHITECTURE 5.1.5 Data memory addressing The method to specify the address of the instruction to be executed next, or the address of a register or memory to be manipulated when an instruction is executed is called addressing.
101 CHAPTER 5 CPU ARCHITECTURE Figure 5-5. Data Memory Addressing ( µ PD78058F, 78058FY) Note When internal ROM size is 60 Kbytes, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal ROM size to less than 56 Kbytes by the memory size switching register.
102 CHAPTER 5 CPU ARCHITECTURE Figure 5-6. Data Memory Addressing ( µ PD78P058F, 78P058FY) Note When internal PROM size is 60 Kbytes, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal PROM size to less than 56 Kbytes by the memory size switching register (IMS).
103 CHAPTER 5 CPU ARCHITECTURE 5.2 Processor Registers The µ PD78058F and 78058FY Subseries units incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory.
104 CHAPTER 5 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When IE = 0, all interrupts except non-maskable interrupt requests are disabled (DI status). When IE = 1, interrupts are enabled (EI status).
105 CHAPTER 5 CPU ARCHITECTURE RETI and RETB Instruction PSW PC15-PC8 PC15-PC8 PC7-PC0 Register Pair Lower SP SP + 2 SP Register Pair Upper RET Instruction POP rp Instruction SP + 1 PC7-PC0 SP SP + 2 .
106 CHAPTER 5 CPU ARCHITECTURE 5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). Each register can also be used as an 8-bit register.
107 CHAPTER 5 CPU ARCHITECTURE Figure 5-12. General Register Configuration (a) Absolute Name (b) Function Name BANK0 BANK1 BANK2 BANK3 FEFFH FEF8H FEF7H FEE0H RP3 RP2 RP1 RP0 R7 15 0 7 0 R6 R5 R4 R3 R.
108 CHAPTER 5 CPU ARCHITECTURE 5.2.3 Special Function Register (SFR) Unlike a general register, each special-function register has special functions. It is allocated in the FF00H to FFFFH area. The special-function register can be manipulated like the general register, with the operation, transfer and bit manipulation instructions.
109 CHAPTER 5 CPU ARCHITECTURE Address Special-Function Register (SFR) Name Symbol R/W After Reset FF00H Port0 P0 R/W √√ — 00H FF01H Port1 P1 √√ — FF02H Port2 P2 √√ — FF03H Port3 P3 .
110 CHAPTER 5 CPU ARCHITECTURE Address Special-Function Register (SFR) Name Symbol R/W After Reset FF38H Correction address register 0 Note CORAD0 R/W —— √ 0000H FF39H FF3AH Correction address r.
111 CHAPTER 5 CPU ARCHITECTURE IF0L IF0H MK0L MK0H PR0L PR0H Address Special-Function Register (SFR) Name Symbol R/W After Reset FFD0H to External access area Note 1 R/W √√ — Undefined FFDFH FFE.
112 CHAPTER 5 CPU ARCHITECTURE 15 0 PC + 15 0 876 S 15 0 PC α jdisp8 When S = 0, all bits of α are 0. When S = 1, all bits of α are 1. PC indicates the start address of the instruction after the BR instruction. ... 5.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents.
113 CHAPTER 5 CPU ARCHITECTURE 5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
114 CHAPTER 5 CPU ARCHITECTURE 5.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched.
115 CHAPTER 5 CPU ARCHITECTURE 70 rp 07 AX 15 0 PC 87 5.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed.
116 CHAPTER 5 CPU ARCHITECTURE 5.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution.
117 CHAPTER 5 CPU ARCHITECTURE 5.4.2 Register addressing [Function] This addressing accesses a general register as an operand. The general register accessed is specified by the register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an instruction code.
118 CHAPTER 5 CPU ARCHITECTURE 5.4.3 Direct addressing [Function] This addressing directly addresses the memory indicated by the immediate data in an instruction word.
119 CHAPTER 5 CPU ARCHITECTURE 5.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this address is applied is a 256-byte space of addresses FE20H through FF1FH.
120 CHAPTER 5 CPU ARCHITECTURE 15 0 Short Direct Memory Effective Address 1 111111 87 0 7 OP code saddr-offset α [Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data.
121 CHAPTER 5 CPU ARCHITECTURE 15 0 SFR Effective Address 1 111111 87 0 7 OP code sfr-offset 1 5.4.5 Special-Function Register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word.
122 CHAPTER 5 CPU ARCHITECTURE 5.4.6 Register indirect addressing [Function] This addressing addresses the memory with the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specify code in an instruction code.
123 CHAPTER 5 CPU ARCHITECTURE 5.4.7 Based addressing [Function] This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition.
124 CHAPTER 5 CPU ARCHITECTURE 5.4.8 Based indexed addressing [Function] This addressing addresses the memory by adding the contents of the HL register, which is used as a base register, to the contents of the B or C register specified in the instruction word, and by using the result of the addition.
125 CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The µ PD78058F and 78058FY Subseries units incorporate two input ports and sixty-seven input/output ports. Figure 6-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations.
126 CHAPTER 6 PORT FUNCTIONS Pin Name Function Alternate Function P00 Port 0. Input only INTP0/TI00 P01 8-bit input/output port. Input/output mode can be specified INTP1/TI01 P02 bit-wise. INTP2 P03 If used as an input port, an on-chip pull-up INTP3 P04 resistor can be used by software.
127 CHAPTER 6 PORT FUNCTIONS P70 SI2/RxD P71 SO2/TxD P72 SCK2/ASCK P120 to P127 RTP0 to RTP7 P130 and P131 ANO0, ANO1 Table 6-1. Port Functions ( µ PD78058F Subseries) (2/2) Pin Name Function Alternate Function P60 Port 6. N-ch open-drain input/output port.
128 CHAPTER 6 PORT FUNCTIONS Table 6-2. Port Functions ( µ PD78058FY Subseries) (1/2) Pin Name Function Alternate Function P00 Port 0. Input only INTP0/TI00 P01 8-bit input/output port. Input/output mode can be specified INTP1/TI01 P02 bit-wise. INTP2 P03 If used as an input port, an on-chip pull-up INTP3 P04 resistor can be used by software.
129 CHAPTER 6 PORT FUNCTIONS P120 to P127 RTP0 to RTP7 P130 and P131 ANO0, ANO1 P70 SI2/RxD P71 SO2/TxD P72 SCK2/ASCK Table 6-2. Port Functions ( µ PD78058FY Subseries) (2/2) Pin Name Function Alternate Function P60 Port 6. N-ch open drain input/output port.
130 CHAPTER 6 PORT FUNCTIONS Control register 6.2 Port Configuration A port consists of the following hardware: Table 6-3. Port Configuration Item Configuration Port mode register (PMm: m = 0 to 3, 5 .
131 CHAPTER 6 PORT FUNCTIONS P00/INTP0/TI00, P07/XT1 RD Internal bus Figure 6-2. P00 and P07 Block Diagram Figure 6-3. P01 to P06 Block Diagram PUO : Pull-up resistor option register PM : Port mode register RD : Port 0 read signal WR : Port 0 write signal P-ch WR PM WR PORT RD WR PUO AV DD P01/INTP1/TI01.
132 CHAPTER 6 PORT FUNCTIONS 6.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
133 CHAPTER 6 PORT FUNCTIONS 6.2.3 Port 2 ( µ PD78058F Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2).
134 CHAPTER 6 PORT FUNCTIONS Figure 6-6. P22 and P27 Block Diagram PUO : Pull-up resistor option register PM : Port mode register RD : Port 2 read signal WR : Port 2 write signal P-ch WR PM WR PORT RD.
135 CHAPTER 6 PORT FUNCTIONS 6.2.4 Port 2 ( µ PD78058FY Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2).
136 CHAPTER 6 PORT FUNCTIONS Figure 6-8. P22 and P27 Block Diagram PUO : Pull-up resistor option register PM : Port mode register RD : Port 2 read signal WR : Port 2 write signal P-ch WR PM WR PORT RD.
137 CHAPTER 6 PORT FUNCTIONS 6.2.5 Port 3 Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mode in 1-bit units with the port mode register 3 (PM3).
138 CHAPTER 6 PORT FUNCTIONS P40 P41 P42 P43 P44 P45 P46 P47 Falling Edge Detection Circuit KRMK KRIF Set Signal Standby Release Signal 6.2.6 Port 4 Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can specify the input mode/output mode in 8-bit units with the memory expansion mode register (MM).
139 CHAPTER 6 PORT FUNCTIONS 6.2.7 Port 5 Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (PM5).
140 CHAPTER 6 PORT FUNCTIONS 6.2.8 Port 6 Port 6 is an 8-bit input/output port with output latch. P60 to P67 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). This port has functions related to pull-up resistors as shown below.
141 CHAPTER 6 PORT FUNCTIONS Figure 6-13. P60 to P63 Block Diagram PM : Port mode register RD : Port 6 read signal WR : Port 6 write signal Figure 6-14.
142 CHAPTER 6 PORT FUNCTIONS 6.2.9 Port 7 This is a 3-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 7 (PM7). When pins P70 to P72 are used as input port pins, an on-chip pull-up resistor can be used as a 3-bit unit by means of pull-up resistor option register L (PUOL).
143 CHAPTER 6 PORT FUNCTIONS Figure 6-16. P71 and P72 Block Diagram PUO : Pull-up resistor option register PM : Port mode register RD : Port 7 read signal WR : Port 7 write signal P-ch WR PM WR PORT R.
144 CHAPTER 6 PORT FUNCTIONS 6.2.10 Port 12 This is an 8-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 12 (PM12).
145 CHAPTER 6 PORT FUNCTIONS 6.2.11 Port 13 This is a 2-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 13 (PM13).
146 CHAPTER 6 PORT FUNCTIONS 6.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) • Pull-up resis.
147 CHAPTER 6 PORT FUNCTIONS Table 6-5. Port Mode Register and Output Latch Settings When Using Alternate Functions P00 INTP0 Input 1 (Fixed) None TI00 Input 1 (Fixed) None P01 INTP1 Input 1 × TI01 I.
148 CHAPTER 6 PORT FUNCTIONS Figure 6-19. Port Mode Register Format PM0 PM1 PM2 1 PM06 PM03 PM02 PM01 1 76 54 3 21 0 Symbol PM3 PM5 FF20H FF21H FF22H FF23H FF25H FFH FFH FFH FFH FFH R/W R/W R/W R/W R/.
149 CHAPTER 6 PORT FUNCTIONS (2) Pull-up resistor option register (PUOH, PUOL) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been specified with PUOH, PUOL.
150 CHAPTER 6 PORT FUNCTIONS (3) Memory expansion mode register (MM) This register is used to set input/output of port 4. MM is set with a 1-bit or 8-bit memory manipulation instruction.
151 CHAPTER 6 PORT FUNCTIONS KRIF Key Return Signal Detection Flag 0 1 Not Detected Detected (Falling edge detection of port 4) 00 0 0 KRM FFF6H 76 543 2 Symbol 1 0 KRMK KRIF 0 0 KRMK Standby Mode Con.
152 CHAPTER 6 PORT FUNCTIONS 6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
153 CHAPTER 6 PORT FUNCTIONS 6.4.3 Operations on input/output port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again.
154 [MEMO].
155 CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5.
156 CHAPTER 7 CLOCK GENERATOR Figure 7-1. Block Diagram of Clock Generator Subsystem Clock Oscillator Main System Clock Oscillator X2 X1 XT2 XT1/P07 FRC STOP MCC FRC CLS CSS PCC2 PCC1 Internal Bus Sta.
157 CHAPTER 7 CLOCK GENERATOR 7.3 Clock Generator Control Register The clock generator is controlled by the following two registers: • Processor clock control register (PCC) • Oscillation mode sel.
158 CHAPTER 7 CLOCK GENERATOR Figure 7-3. Processor Clock Control Register Format Notes 1. Bit 5 is Read Only. 2. When the CPU is operating on the subsystem clock, MCC should be used to stop the main system clock oscillation. A STOP instruction should not be used.
159 CHAPTER 7 CLOCK GENERATOR The fastest instruction of the µ PD78075F and 78075FY Subseries can be executed in two clocks of the CPU clock. The relationship between the CPU clock (f CPU ) and the minimum instruction execution time is shown in Table 7-2.
160 CHAPTER 7 CLOCK GENERATOR Figure 7-5. Main System Clock Waveform due to Writing to OSMS Caution 2. When writing “1” to MCS, V DD must be 2.7 V or higher before the write execution. Remarks f xx : Main system clock frequency (fx or fx/2) f x : Main system clock oscillation frequency Write to OSMS (MCS 0) f XX Max.
161 CHAPTER 7 CLOCK GENERATOR 7.4 System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator.
162 CHAPTER 7 CLOCK GENERATOR 7.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the main system clock oscillator.
163 CHAPTER 7 CLOCK GENERATOR Figure 7-8. Examples of Resonator with Incorrect Connection (2/2) (c) Changing high current is too near a (d) Current flows through the grounding line signal line of the .
164 CHAPTER 7 CLOCK GENERATOR 7.4.3 Scaler The scaler divides the main system clock oscillator output (f XX ) and generates various clocks. 7.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows.
165 CHAPTER 7 CLOCK GENERATOR 7.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode.
166 CHAPTER 7 CLOCK GENERATOR MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock L L Oscillation does not stop. 7.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting.
167 CHAPTER 7 CLOCK GENERATOR MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock Figure 7-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation 7.
168 CHAPTER 7 CLOCK GENERATOR Table 7-3. Maximum Time Required for CPU Clock Switchover × × ×× 1 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 CSS 0 0 0 0 × PCC0 PCC1 PCC2 1 × 1 PCC0 CSS PCC2 PCC1 0 0 0 0 1 1 0.
169 CHAPTER 7 CLOCK GENERATOR V DD RESET Interrupt Request Signal System Clock CPU Clock Wait (26.2 ms : 5.0 MHz) Internal Reset Operation Minimum Speed Operation Maximum Speed Operation Subsystem Clock Operation f XX f XX f XT f XX High-Speed Operation 7.
170 [MEMO].
171 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Overview of the µ PD78058F and 78058FY Subseries On-Chip Timers This chapter describes the 16-bit timer/event counter and begins with an overview of the on-chip timers and related devices of the µ PD78058F and 78058FY Subseries.
172 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-1. Timer/Event Counter Operation Interval timer 2 channels Note 3 2 channels 1 channel Note 1 1 channel Note 2 External event counter √√ —— Tim.
173 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.2 16-Bit Timer/Event Counter Functions The 16-bit timer/event counter (TM0) has the following functions. • Interval timer • PWM output • Pulse width me.
174 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Square-wave output TM0 can output a square wave with any selected frequency. Table 8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse .
175 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TCL06 TCL05 TCL04 Timer Clock Selection Register 0 3 Internal bus Capture/Compare Control Register 0 CRC02 CRC01 CRC00 Selector TI01/ P01/INTP1 INTTM3 2f XX f .
176 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-2. 16-Bit Timer/Event Counter Output Control Circuit Block Diagram Remark The circuitry enclosed by the dotted line is the output control circuit.
177 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (1) Capture/compare register 00 (CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register 0.
178 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Caution If the valid edge of the TIO0/P00 pin is input while CR01 is read, CR01 does not perform the capture operation and retains the current data. However, the interrupt request flag (PIF0) is set. (3) 16-bit timer register (TM0) TM0 is a 16-bit register which counts the count pulses.
179 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 76 54 32 10 Symbol TCL0 TCL03 TCL02 TCL01 TCL00 00 00 f XT (32.768 kHz) 01 01 f XX f X (5.0 MHz) f X /2 (2.5 MHz) 01 10 f XX /2 f X /2 (2.5 MHz) f X /2 2 (1.25 MHz) 01 11 f XX /2 2 f X /2 2 (1.
180 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6.
181 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 00 00 TMC03 TMC02 TMC01 OVF0 76 54 32 10 Symbol TMC0 FF48H 00H R/W Address After Reset R/W OVF0 16-Bit Timer Register Overflow Detection 0 Overflow not detecte.
182 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 00 00 0 CRC02 CRC01 CRC00 76 54 32 10 Symbol CRC0 FF4CH 04H R/W Address After Reset R/W CRC00 CR00 Operating Mode Selection 0 Operates as compare register 1 Op.
183 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 76 54 32 10 Symbol TOC0 FF4EH 00H R/W Address After Reset R/W TOE0 16-Bit Timer/Event Counter Output Control 0 Output di.
184 CHAPTER 8 16-BIT TIMER/EVENT COUNTER PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 76 54 32 10 Symbol PM3 FF23H FFH R/W Address After Reset R/W PM3n P3n Pin Input/Output Mode Selection (n = 0 to 7) 0 Output mode (output buffer ON) 1 Input mode (output buffer OFF) (5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units.
185 CHAPTER 8 16-BIT TIMER/EVENT COUNTER ES31 ES30 ES21 ES20 ES11 ES10 0 0 76 54 32 10 Symbol INTM0 FFECH 00H R/W Address After Reset R/W ES11 INTP0 Valid Edge Selection ES10 0 Falling edge 0 0 Rising.
186 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 0 0 0 0 0 SCS1 SCS0 76 54 32 10 Symbol SCS FF47H 00H R/W Address After Reset R/W SCS1 SCS0 00 01 10 11 INTP0 Sampling Clock Selection MCS = 1 MCS = 0 f XX /2 N f X /2 7 (39.1 kHz) f XX /2 7 f X /2 8 (19.5 kHz) f X /2 5 (156.
187 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 0 0 0 0 0/1 0/1 0 CRC02 CRC01 CRC00 CRC0 CR00 set as compare register 00 00 11 0 / 1 0 TMC03 TMC02 TMC01 OVF0 TMC0 Clear & start on match TM0 and CR00 8.
188 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 16-Bit Capture/Compare Register 00 (CR00) 16-Bit Timer Register (TM0) Selector f XX /2 2 f XX /2 f XX 2f XX INTTM3 TI00/P00/INTP0 OVF0 Clear Circuit INTTM00 Figure 8-11. Interval Timer Configuration Diagram Figure 8-12.
189 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-6. 16-Bit Timer/Event Counter Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 000.
190 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TOE0 TOC01 LVR0 LVS0 TOC04 OSPE OSPT TOC0 1 0/1 × × × × × 0 TO0 Output Enabled Specifies Active Level CRC00 CRC01 CRC02 CRC0 0 0/1 0/1 0 0 0 0 0 CR00 set as compare register TMC0 0 1 0 0 0 0 0 0 OVF0 TMC01 TMC02 TMC03 PWM mode Figure 8-13.
191 CHAPTER 8 16-BIT TIMER/EVENT COUNTER By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (V AN ) used for D/A conversion with the configuration shown in Figure 8-14 is as follows.
192 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TOC0 1 1 0/1 0/1 1 0 0 0 TOE0 TOC01 LVR0 LVS0 Inversion of output on match of TM0 and CR00 TOC04 OSPE OSPT TO0 Output Enabled Specified TO0 output F/F initial .
193 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TMC0 0 0/1 1 0 0 0 0 0 OVF0 TMC01 TMC02 TMC03 Free-Running Mode CRC0 0 0/1 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as compare register CR01 set as capture register 8.
194 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Selector f XX /2 2 f XX /2 f XX 2f XX INTTM3 16-Bit Timer Register (TM0) 16-Bit Capture/Compare Register 01 (CR01) OVF0 INTP0 Internal Bus TI00/P00/INTP00 Coun.
195 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 1 0 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as capture register Captured in CR00 on valid edge of TI01/P01 Pin CR01 set as capture register TMC0 0 0/1 1 0 .
196 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value INTP0 TI01 Pin Input t CR00 Captured Value INTP1 OVF0 (D1 – D0) × t (10000H – D1 + D2) × t (10000H – D1 + (D2 + 1)) × t (D3 – D2) × t 0000 0001 D0 D1 0000 D3 D2 FFFF D0 D1 D3 D2 D1 Figure 8-21.
197 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 1 1 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as capture register Captured in CR00 on invalid edge of TI00/P00 Pin CR01 set as capture register TMC0 0 0/1 1 .
198 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value CR00 Captured Value INTP0 OVF0 (D1-D0) × t (10000H-D1 + D2) × t (D3-D2) × t D1 D3 D0 D2 D3 D2 0000 FFFF D1 D0 0000 0001 t Figure 8-23.
199 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 1 1 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as capture register Captured in CR00 on invalid edge of TI00/P00 Pin CR01 set as capture register TMC0 0 0/1 0 .
200 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 0 0/1 0/1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as compare register TMC0 0 0/1 1 1 0 0 0 0 OVF0 TMC01 TMC02 TMC03 Clear & start with match of TM0 and CR00 8.
201 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TI00 Pin Input TM0 Count Value CR00 INTTM0 N 0000 0001 0002 0003 0004 0005 N-1 N 0000 0001 0002 0003 16-Bit Capture/Compare Register 00 (CR00) Clear INTTM00 INTP0 16-Bit Timer Register (TM0) 16-Bit Capture/Compare Register 01 (CR01) Internal Bus TI00 Valid Edge OVF0 Figure 8-27.
202 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TOC0 1 1 0/1 0/1 0 0 0 0 TOE0 TOC01 LVR0 OSPT OSPE TOC04 LVS0 TO0 Output Enabled Inversion of output on match of TM0 and CR00 Specified TO0 output F/F initial .
203 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Clock TM0 Count Value CR00 INTTM00 TO0 Pin Output 0000 0001 0002 N-1 N 0000 0001 0002 N-1 N 0000 N Figure 8-30.
204 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TOC0 1 1 0/1 0/1 1 1 0 0 TOE0 TOC01 LVR0 OSPT OSPE TOC04 LVS0 TO0 Output Enabled Inversion of output on match of TM0 and CR00 Specified TO0 output F/F initial .
205 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Clock TM0 Count Value CR01 Set Value CR00 Set Value INTTM01 OSPT INTTM00 TO0 Pin Output 0000 0001 N N+1 0000 N-1 N M-1 M 0000 0001 0002 N M N M N M N M Set 0CH to TMC0 (TM0 count start) Figure 8-32.
206 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 0 0/1 0 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as compare register CR01 set as compare register TOC0 1 1 0/1 0/1 1 1 0 0 TOE0 TOC01 LVR0 LVS0 OSPT OSPE TOC0.
207 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Clock TM0 Count Value CR01 Set Value CR00 Set Value INTTM01 TI00 Pin Input INTTM00 TO0 Pin Output 0000 0001 0000 N N+1 N+2 M–2 M–1 M M+1 M+2 M+3 N M N M N M N M Set 08H to TMC0 (TM0 count start) Figure 8-34.
208 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Pulse CR00 TM0 Count Value X-1 X FFFFH 0000H 0001H 0002H M N Timer Start Count Pulse TM0 Count Value 0000H 0001H 0002H 0003H 0004H 8.
209 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Pulse TM0 Count Value Edge Input Interrupt Request Flag Capture Read Signal CR01 Captured Value Capture Operation Ignored X N+1 N N+1 N+2 M M+1 M+2 (4) C.
210 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Pulse CR00 TM0 OVF0 INTTM00 FFFFH FFFEH FFFFH 0000H 0001H (7) Operation of OVF0 flag OFV0 flag is set to 1 in the following case. The clear & start mode on match between TM0 and CR00 is selected. ↓ CR00 is set to FFFFH.
211 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.1 8-Bit Timer/Event Counter Function The on-chip 8-bit timer/event counters of the µ PD78058F, 78058FY Subseries have two modes: a mode in which the two 8-b.
212 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 9-1. 8-Bit Timer/Event Counter Interval Times Minimum Interval Ti.
213 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output.
214 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals.
215 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output.
216 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.2 8-Bit Timer/Event Counter Configuration The 8-bit timer/event counters 1 and 2 consist of the following hardware.
217 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-1. 8-Bit Timer/Event Counter Block Diagram Note Refer to Figures 9-2 and 9-3 for details of 8-bit timer/event counters 1 and 2 output control circuits 1 and 2, respectively.
218 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS LVR2 LVS2 TOC15 INTTM2 R S INV Level F/F (LV2) f SCK P32 Output Latch PM32 TOE2 TO2/P32 Q LVR1 LVS1 TOC11 INTTM1 R S INV Q P31 Output Latch TOE1 PM31 TO1/P31 Level F/F (LV1) Figure 9-2.
219 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (1) Compare registers 10 and 20 (CR10, CR20) These are 8-bit registers to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value, and th.
220 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.3 8-Bit Timer/Event Counter Control Registers The following four types of registers are used to control the 8-bit timer/event counter.
221 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10 76 54 32 10 Symbol TCL1 FF41H 00H R/W Address After Reset R/W TCL13 TCL12 TCL11 TCL10 0 0 0 0 TI1 falling edge 0 0 0 1 TI1 rising edge 01 10 01 11 f XX /2 f X /2 (2.
222 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 0 1 2 3 4 5 6 7 Symbol TCE1 FF49H 00H R/W Address After Reset R/W TCE2 TMC12 0 0 0 0 0 TMC1 TCE1 8-Bit Timer Register 1 Operation Control 0 Operation stop (TM1.
223 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 0 1 2 3 4 5 6 7 Symbol TOE1 TOC11 LVR1 LVS1 TOE2 TOC15 LVR2 LVS2 TOC1 FF4FH 00H R/W Address After Reset R/W TOE1 8-Bit Timer/Event Counter 1 Outptut Control 0 .
224 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 0 1 2 3 4 5 6 7 Symbol PM30 FF23H FFH R/W Address After Reset R/W PM31 PM32 PM33 PM34 PM35 PM36 PM37 PM3 PM3n P3n Pin Input/Output Mode Selection (n=0 to 7) 0 Output mode (output buffer ON) 1 Input mode (output buffer OFF) (4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units.
225 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.4 8-Bit Timer/Event Counter Operation 9.4.1 8-bit timer/event counter mode (1) Interval timer operations Operates as an interval timer which generates interrupt requests repeatedly with the count values set previously in the 8 bit conveyor registers 10 and 20 (CR10, CR20) as the interval.
226 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Table 9-6. 8-Bit Timer/Event Counter 1 Interval Time Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 000.
227 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Table 9-7. 8-Bit Timer/Event Counter 2 Interval Time Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 000.
228 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS TI1 Pin Input TM1 Count Value INTTM1 CR10 00 01 02 03 04 05 N-1 N 00 01 02 03 N (2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/ P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2).
229 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (3) Operation as a Square Wave Output Operates as a square wave output at the desired frequency with the values set previously in the 8 bit conveyor registers 10 and 20 (CR10, CR20) as the interval.
230 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-10. Square-Wave Output Operation Timing Note The initial value of TO1 output can be set with bits 2 and 3 (LVR1 and LVS1) of the 8-bit timer output control register (TOC1).
231 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-11. Interval Timer Operation Timing Remark Interval time = (N + 1) × t : N = 0000H to FFFFH Caution Even if the 16-bit timer/event counter mode is us.
232 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Table 9-9. Interval Times When 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter Minimum Interval Time Maximum Interval.
233 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS TI1 Pin Input TM1, TM2 Count Value CR10, CR20 INTTM2 0000 0001 0002 0003 0004 0005 N-1 N 0000 0001 0002 0003 N (2) External event counter operations The extern.
234 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (3) Operation as a Square Wave Output Operates as a square wave output at the desired frequency with the values set previously in the 8 bit conveyor registers 10 and 20 (CR10, CR20) as the interval.
235 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-13. Square-Wave Output Operation Timing Count Clock TM1 00H 00H 00H 01H FFH 00H 01H 02H FFH 00H 01H FFH M – 1 00H 00H M 01H N N N M N + 1 TM2 CR10 C.
236 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS TI1, TI2, Input CR10, CR20 TM1, TM2 Count Value TO1, TO2 Interrupt Request Flag 00H 00H 00H 00H 00H Count Pulse TM1, TM2 Count Value 00H 01H 02H 03H 04H Timer Start 9.
237 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Count Pulse CR10, CR20 TM1, TM2 Count Value X-1 X FFH 00H 01H 02H M N (3) Operation after compare register change during timer count operation If the values af.
238 [MEMO].
239 CHAPTER 10 WATCH TIMER 10.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.
240 CHAPTER 10 WATCH TIMER 10.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 10-2. Watch Timer Configuration Item Configuration Counter 5 bits × 1 Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2) 10.
241 CHAPTER 10 WATCH TIMER TMC21 Prescaler Selector INTWT 5-Bit Counter f W 2 14 f W 2 13 INTTM3 To 16-Bit Timer / Event Counter Watch Timer Mode Control Register TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 T.
242 CHAPTER 10 WATCH TIMER TCL27 7 TCL26 6 TCL25 TCL24 4 0 3210 FF42H Address TCL2 Symbol TCL22 TCL21 TCL20 5 00H After Reset R/W R/W 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TCL22 TCL21 TCL20 .
243 CHAPTER 10 WATCH TIMER 0 7 TMC26 6 TMC25 TMC24 4 TMC23 3210 FF4AH Address TMC2 Symbol TMC22 TMC21 TMC20 5 00H After Reset R/W R/W 0 1 TMC23 2 14 /f W (0.4 sec) 2 13 /f W (0.2 sec) Watch Flag Set Time Selection 0 0 0 0 1 1 Other than above 0 0 1 1 0 0 0 1 0 1 0 1 TMC26 TMC25 TMC24 2 4 /f W (410 s) 2 5 /f W (819 s) 2 6 /f W (1.
244 CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation When the 32.768-kHz subsystem clock or 4.19-MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer sets the test input flag (WTIF) to 1 at the constant time interval.
245 CHAPTER 11 WATCHDOG TIMER 11.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (The watchdog timer and interval timer cannot be used at the same time).
246 CHAPTER 11 WATCHDOG TIMER (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Table 11-2. Interval Times Interval Time MCS = 1 CS = 0 2 11 × 1/f XX 2 11 × 1/f X (410 µ s) 2 12 × 1/f X (819 µ s) 2 12 × 1/f XX 2 12 × 1/f X (819 µ s) 2 13 × 1/f X (1.
247 CHAPTER 11 WATCHDOG TIMER Prescaler f XX 2 4 f XX 2 5 f XX 2 6 f XX 2 7 f XX 2 8 f XX 2 9 Selector Watchdog Timer Mode Register Internal Bus Internal Bus TCL22 TCL21 TCL20 f XX /2 3 f XX 2 11 Time.
248 CHAPTER 11 WATCHDOG TIMER 11.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock.
249 CHAPTER 11 WATCHDOG TIMER Figure 11-2. Timer Clock Select Register 2 Format Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3.
250 CHAPTER 11 WATCHDOG TIMER RUM 7 0 6 0 WDTM4 4 WDTM3 3210 FFF9H Address WDTM Symbol 000 5 00H After Reset R/W R/W RUN 0 1 Count stop Counter is cleared and counting starts. WDTM3 × 0 1 Interval timer mode Note 2 (Maskable interrupt request occurs upon generation of an overflow.
251 CHAPTER 11 WATCHDOG TIMER 11.4 Watchdog Timer Operations 11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaway.
252 CHAPTER 11 WATCHDOG TIMER 11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generate interrupt request repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0.
253 CLOE PCL/P35 Pin Output ** CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI.
254 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 12-1. Clock Output Control Circuit Configuration Item Configuration Timer clock select register 0 (TCL0) Port mode register 3 (PM3) Figure 12-2.
255 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT CLOE 7 TCL06 6 TCL05 TCL04 4 TCL03 3210 FF40H Address TCL0 Symbol TCL02 TCL01 TCL00 5 00H After Reset R/W R/W 0 0 0 0 1 1 1 1 1 Other than above 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 TCL03 TCL02 TCL01 f XT (32.
256 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5.
257 Internal Bus f XX /2 9 f XX /2 10 f XX /2 11 TCL27 TCL26 TCL25 3 PM36 Selector Timer Clock Select Register 2 Port Mode Register 3 BUZ / P36 P36 Output Latch CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1.
258 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency.
259 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT TCL27 7 TCL26 6 TCL25 TCL24 4 0 3210 FF42H Address TCL2 Symbol TCL22 TCL21 TCL20 5 00H After Reset R/W R/W 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 .
260 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT PM37 7 PM36 6 PM35 PM34 4 PM33 3210 FF23H Address PM3 Symbol PM32 PM31 PM30 5 FFH After Reset R/W R/W PM3n 0 1 Output mode (output buffer ON) Input mode (o.
261 CHAPTER 14 A/D CONVERTER 14.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result register (ADCR).
262 CHAPTER 14 A/D CONVERTER 14.2 A/D Converter Configuration The A/D converter consists of the following hardware. Table 14-1. A/D Converter Configuration Item Configuration Analog input 8 Channels (.
263 CHAPTER 14 A/D CONVERTER Figure 14-1. A/D Converter Block Diagram Notes 1. Selector to select the number of channels to be used for analog input. 2.
264 CHAPTER 14 A/D CONVERTER (1) Successive approximation register (SAR) The analog input voltage value and the voltage tap (comparative voltage) value from the serial resistance string are compared and the results are stored in this register from the most significant bit (MSB).
265 CHAPTER 14 A/D CONVERTER (7) AV REF0 pin This pin inputs the A/D converter reference voltage. It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AV REF0 and AV SS .
266 CHAPTER 14 A/D CONVERTER Figure 14-2. A/D Converter Mode Register Format Notes 1. Set so that the A/D conversion time is 19.1 µ s or more. 2. Setting prohibited because A/D conversion time is less than 19.
267 CHAPTER 14 A/D CONVERTER (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports.
268 CHAPTER 14 A/D CONVERTER ES71 7 ES70 6 ES61 ES60 4 ES51 3210 FFEDH Address INTM1 Symbol ES50 ES41 ES40 5 00H After Reset R/W R/W ES41 0 0 1 1 ES40 0 1 0 1 Falling edge Rising edge Setting prohibit.
269 CHAPTER 14 A/D CONVERTER 14.4 A/D Converter Operations 14.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter mode register (ADM).
270 CHAPTER 14 A/D CONVERTER SAR ADCR INTAD A / D Converter Operation Sampling Time Sampling A / D Conversion Conversion Time Undefined 80H C0H or 40H Conversion Result Conversion Result Figure 14-5. A/D Converter Basic Operation A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (0) by software.
271 CHAPTER 14 A/D CONVERTER 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 255 254 253 3 2 1 0 A /D Conversion Results (ADCR) Input Voltage/AV REF0 14.
272 CHAPTER 14 A/D CONVERTER ADM Rewrite CS=1, TRG=1 Standby State ANIn INTP3 A /D Conversion ADCR INTAD ANIn ANIn ANIn ANIm ANIm ANIn ANIn Standby State Standby State ADM Rewrite CS=1, TRG=1 ANIm ANIm ANIm 14.
273 CHAPTER 14 A/D CONVERTER Conversion Start CS=1, TRG=0 A /D Conversion ADCR INTAD ANIn ANIn ANIm ANIn ANIm ANIm ANIn ANIn ADM Rewrite CS=1, TRG=0 ADM Rewrite CS=0, TRG=0 Conversion suspended Conver.
274 CHAPTER 14 A/D CONVERTER 14.5 A/D Converter Cautions (1) Power consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock.
275 CHAPTER 14 A/D CONVERTER (3) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AV REF0 and ANI0 to ANI7.
276 CHAPTER 14 A/D CONVERTER A /D Conversion ADCR INTAD ANIn ANIn ANIm ANIm ANIn ANIn ANIm ANIm ADM Rewrite (Start of ANIn Conversion) ADM Rewrite (Start of ANIm Conversion) ADIF is set but ANIm conve.
277 CHAPTER 14 A/D CONVERTER (7) AV DD pin The AV DD pin is the analog circuit power supply pin, and supplies power to the input circuits of ANI0/P10 to ANI7/P17. Therefore, be sure to apply the same voltage as V DD to this pin even when the application circuit is designed so as to switch to a backup battery.
278 [MEMO].
279 CHAPTER 15 D/A CONVERTER 15.1 D/A Converter Functions The D/A converter converts a digital input into an analog value. It consists of two 8-bit resolution channels of voltage output type D/A converter. The conversion method used is the R-2R resistor ladder method.
280 CHAPTER 15 D/A CONVERTER 15.2 D/A Converter Configuration The D/A converter consists of the following hardware. Table 15-1. D/A Converter Configuration Item Configuration D/A conversion value set register 0 (DACS0) D/A conversion value set register 1 (DACS1) Control register D/A converter mode register (DAM) Figure 15-1.
281 CHAPTER 15 D/A CONVERTER (1) D/A conversion value set register 0, 1 (DACS0, DACS1) DACS0 and DACS1 are registers where values are set for determining the analog voltage output respectively to pins ANO0 and ANO1. DACS0 and DACS1 are set with 8-bit memory manipulation instructions.
282 CHAPTER 15 D/A CONVERTER 0 7 0 6 DAM5 DAM4 4 0 3210 FF98H Address DAM Symbol 0 DACE1 DACE0 5 00H After Reset R/W R/W DAM5 0 1 Normal mode Real-time output mode DACE0 0 1 D/A conversion stop D/A co.
283 CHAPTER 15 D/A CONVERTER 15.4 Operations of D/A Converter (1) Select the operation mode for channel 0 using bit 4 (DAM4) of the D/A converter mode register (DAM), and select the operation mode for channel 1 using bit 5 (DAM5).
284 CHAPTER 15 D/A CONVERTER 15.5 Cautions Related to D/A Converter (1) Output impedance of D/A converter Because the output impedance of the D/A converter is high, use of current flowing from the ANOn pins (n = 0,1) is prohibited.
285 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) The µ PD78058F Subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1.
286 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 16.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes.
287 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1).
288 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 16.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware.
289 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) CSIE0 COI WUP CSIM 04 CSIM 03 CSIM 02 CSIM 01 CSIM 00 Serial Operating Mode Register 0 Control Circuit Output Control Selector SI0/SB.
290 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock.
291 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (3) SO0 latch This latch holds the SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In the SBI mode, this latch is set upon termination of the 8th serial clock.
292 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 16.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0.
293 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) Serial Interface Channel 0 Serial Clock Selection TCL33 TCL32 TCL31 TCL30 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f XX /2 f XX /2 2 f XX /2 3 f XX /2 4 f XX /2 5 f XX /2 6 f XX /2 7 f XX /2 8 Setting prohibited f X /2 2 (1.
294 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal.
295 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) WUP 0 1 Wake-up Function Control Note 1 Interrupt request signal generation with each serial transfer in any mode Interrupt request s.
296 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
297 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) Figure 16-5. Serial Bus Interface Control Register Format (2/2) Note The busy mode can be canceled by starting serial interface transfer.
298 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction.
299 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 6543210 7 Symbol CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 FF60H 00H R/W Address After Reset R/W CSIE0 0 Serial Interface Channel 0 Operation Control Operation stopped Operation enabled R/W 1 16.
300 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 16.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series.
301 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 6543210 7 Symbol CSIM0 CSIM01 0 1 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output 0 SBI mode (see section 16.4.3 SBI mode operation .
302 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 6543210 7 Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
303 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) RELT CMDT SO0 latch SI0 SCK0 12345678 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CSIIF0 Transfer Start at the Falling Edge of SCK0 End of Transfer (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units.
304 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 7 6 Internal Bus 1 0 LSB-first MSB-first Read/Write Gate SI0 Serial I/O Shift Register 0 (SIO0) Read/Write Gate SO0 SCK0 DQ SO0 Latch (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.
305 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 16.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI uses a single master device and employs the clocked serial I/O format with the addition of a bus configuration function.
306 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (1) SBI functions In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many port.
307 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (2) SBI definition The SBI serial data format and the signals to be used are defined as follows. Serial data to be transferred with SBI consists of three kinds of data: “address”, “command”, and “data”.
308 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) SCK0 "H" SB0 (SB1) SCK0 "H" SB0 (SB1) (a) Bus release signal (REL) The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the high level when the SCK0 line is at the high level (without serial clock output).
309 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) Master Slave 1 Not Selected Slave 2 Selected Slave 3 Not Selected Slave 4 Not Selected Slave 2 Address Transmission SCK0 A7 A6 A5 A4 .
310 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (d) Command and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. Figure 16-16. Commands Figure 16-17.
311 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 89 ACK SCK0 SB0 (SB1) SCK0 SB0 (SB1) 8 9 10 11 ACK (e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between transmitter and receiver. Figure 16-18.
312 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) READY ACK SCK0 SB0 (SB1) BUSY 89 (f) Busy signal (BUSY) and ready signal (READY) The BUSY signal is intended to report to the master device that the slave device is preparing for data transmission/reception.
313 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used as a port. 3. To use the wake-up function (WUP = 1), clear the bit 5 (SIC) of the interrupt timing specify register (SINT) to 0.
314 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. The shaded area is used in the SBI mode.
315 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) R ACKD Acknowledge Detection Clear Conditions (ACKD = 0) • SCK0 fall immediately after the busy mode is released during the transfer start instruction execution.
316 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 6543210 7 Symbol SINT 0 CLD SIC SVAM 0 0 0 0 FF63H 00H R/W Note 1 Address After Reset R/W SVAM 0 1 SVA Bit to be Used as Slave Addres.
317 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) Write FFH to SIO0 (Transfer Start Instruction) SIO0 SCK0 SB0 (SB1) RELD CMDD Transfer Start Instruction A7 A6 A1 A0 1 2 789 READY A7 .
318 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) SCK0 6 SB0 (SB1) ACKT 7 8 9 D2 D1 D0 ACK When set during this period ACK signal is output for a period of one clock just after setting Figure 16-22. ACKT Operation Caution Do not set ACKT before termination of transfer.
319 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) SB0 (SB1) ACKE If set and cleared during this period and ACKE = 0 at the falling edge of SCK0 ACK signal is not output D2 D1 D0 SCK0 SB0 (SB1) ACKE 1 2 789 D7 D6 D2 D1 D0 When ACKE = 0 at this point ACK signal is not output SCK0 Figure 16-23.
320 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) SCK0 SB0 (SB1) BSYE 7 89 ACK 6 When BSYE = 1 at this point BUSY If reset during this period and BSYE = 0 at the falling edge of SCK0 D2 D1 D0 SB0 (SB1) ACKD ACK 9 SIO0 78 D1 6 D2 D0 Transfer Start Instruction Transfer Start SCK0 Figure 16-24.
321 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) SCK0 D0 READY SB0 (SB1) D0 READY SB0 (SB1) ACK BUSY BUSY ACK 9 "H" SB0 (SB1) SCK0 SCK0 "H" SB0 (SB1) Table 16-3.
322 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) SCK0 SB0 (SB1) 1278 SCK0 SB0 (SB1) 1278 CMD SCK0 SB0 (SB1) 1278 REL CMD SCK0 SB0 (SB1) 12789 1 0 Timing Chart Definition Signal Name .
323 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 ............ Serial clock input/output pin <1> Master .
324 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (6) Address match detection method In the SBI mode, the master transmits a slave address to select a specific slave device. Coincidence of the addresses can be automatically detected by hardware.
325 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 1 2 3 4 5 6 7 8 9 SCK0 Pin A7 A6 A5 A4 A3 A2 A1 A0 ACK BUSY SB0 (SB1) Pin Program Processing Serial Transmission INTCSI0 Generation A.
326 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 1 2 3 4 5 6 7 8 9 SCK0 Pin C7 C6 C5 C4 C3 C2 C1 C0 ACK BUSY SB0 (SB1) Pin Program Processing Serial Transmission INTCSI0 Generation A.
327 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 1 2 3 4 5 6 7 8 9 SCK0 Pin D7 D6 D5 D4 D3 D2 D1 D0 ACK BUSY SB0 (SB1) Pin Program Processing Serial Transmission INTCSI0 Generation A.
328 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 1 2 3 4 5 6 7 8 9 SCK0 Pin D7 D6 D5 D4 D3 D2 D1 D0 ACK BUSY SB0 (SB1) Pin Program Processing Serial Reception INTCSI0 Generation ACK .
329 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied.
330 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (10) How to determine the slave busy state When a device is in the master mode, use the following procedure to determine if the slave is in the busy state or not. <1> Detect the generation of an acknowledge signal (ACK) or interrupt request signal.
331 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 16.4.4 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1).
332 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 6543210 7 Symbol CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 0 1 Serial Interface Channel 0 Clock Selection Input C.
333 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 6543210 7 Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
334 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock.
335 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) RELT CMDT SO0 Latch (3) Other signals Figure 16-33 shows RELT and CMDT operations. Figure 16-33. RELT and CMDT Operations (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied.
336 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) To Internal Circuit SCK0/P27 P27 Output Latch When CSIE0 = 1 and CSIM01 and CSIM00 are 1 and 0, or 1 and 1. SCK0 (1 while transfer is stopped) From Serial Clock Control Circuit Manipulated by bit manipulation instruction 16.
337 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) The µ PD78058FY Subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1.
338 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 17.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes.
339 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (4) I 2 C (Inter IC) bus mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode is in compliance with the I 2 C bus format.
340 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 17.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware.
341 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Figure 17-2. Serial Interface Channel 0 Block Diagram CSIE0 COI WUP CSIM 04 CSIM 03 CSIM 02 CSIM 01 CSIM 00 Serial Operating Mode Re.
342 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock.
343 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (3) SO0 latch This latch holds SI0/SB0/SDA0/P25 and SO0/SB1/SDA1/P26 pin levels. It can be directly controlled by software.
344 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Table 17-3. Serial Interface Channel 0 Interrupt Request Signal Generation Serial Transfer mode BSYE WUP WAT1 WAT0 ACKE Description 3-wire or 2-wire serial I/O 0 0 0 0 0 An interrupt request signal is generated each mode time 8 serial clocks are counted.
345 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 17.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0.
346 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Serial Interface Channel 0 Serial Clock Selection Serial Interface Channel 1 Serial Clock Selection TCL33 TCL32 TCL31 TCL30 0 0 1 1 .
347 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal.
348 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Figure 17-4. Serial Operating Mode Register 0 Format Notes 1. Bit 6 (COI) is a read-only bit. 2. I 2 C bus mode, the clock frequency becomes 1/16 of that output from TO2. 3. Can be used as P25 (CMOS input/output) when used only for transmission.
349 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
350 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Figure 17-5. Serial Bus Interface Control Register Format (2/2) Notes 1. Setting should be performed before transfer. 2. If 8-clock wait mode is selected, the acknowledge signal at reception time must be output using ACKT.
351 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction.
352 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Figure 17-6. Interrupt Timing Specify Register Format (2/2) Notes 1. When using wake-up function in the I 2 C mode, set SIC to 1.
353 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 6543210 7 Symbol CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 FF60H 00H R/W Address After Reset R/W CSIE0 0 Serial Interface Channel 0 Operation Control Operation stopped Operation enabled R/W 1 17.
354 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 17.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series.
355 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. 6543210 7 Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT = 1, SO0 Iatch is set to 1.
356 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) RELT CMDT SO0 latch SI0 SCK0 12345678 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CSIIF0 Transfer Start at the Falling Edge of SCK0 End of Transfer (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units.
357 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 7 6 Internal Bus 1 0 LSB-first MSB-first Read/Write Gate SI0 Serial I/O Shift Register 0 (SIO0) Read/Write Gate SO0 SCK0 DQ SO0 Latch (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.
358 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 17.4.3 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1).
359 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. Notes 1. Bit 6 (COI) is a read-only bit.
360 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 6543210 7 Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
361 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 12345678 SCK0 D7 D6 D5 D4 D3 D2 D1 D0 SB0 (SB1) CSIIF0 Transfer Start at the Fallin g Ed g e of SCK0 End of Transfer (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units.
362 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) RELT CMDT SO0 Latch (3) Other signals Figure 17-12 shows RELT and CMDT operations. Figure 17-12.
363 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 17.4.4 I 2 C bus mode operation The I 2 C bus mode is provided for when communication operations are performed between a single master device and multiple slave devices.
364 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 1-7 8 9 1-7 8 9 1-7 8 9 Address R/W ACK Data ACK Data ACK SCL Start Condition SDA0(SDA1) Stop Condition (1) I 2 C bus mode functions In the I 2 C bus mode, the following functions are available.
365 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 2 3 456 7 A6 A5 A4 A3 A2 A1 A0 R/W Transfer direction specification SCL 8 1 SDA0(SDA1) 1 2 3 456 7 A6 A5 A4 A3 A2 A1 A0 R/W Address .
366 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) H SCL SDA0(SDA1) 12 3 456 7 A6 A5 A4 A3 A2 A1 A0 R/W SCL SDA0 (SDA1) 9 8 ACK (d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received.
367 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (f) Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data.
368 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (3) Register setting The I 2 C bus mode is set by the serial operating mode register 0 (CSIM0), serial bus interface control register (SBIC), and interrupt timing specify register (SINT).
369 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. R/W RELT Use for stop condition output.
370 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (c) Interrupt timing specification register (SINT) SINT is set by the 1-bit or 8-bit memory manipulation instruction.
371 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (4) Various signals A list of signals in the I 2 C bus mode is given in Table 17-4.
372 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (5) Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below. (a) SCL Pin for serial clock input/output dual-function pin.
373 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (7) Error detection In the I 2 C bus mode, transmission error detection can be performed by the following methods because the serial bus SDA0 (SDA1) status during transmission is also taken into the serial I/O shift register 0 (SIO0) register of the transmitting device.
374 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (1/3) (a) Start Condition to Addr.
375 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) L L L L 1 D5 D4 D3 D2 D1 D0 ACK D6 D7 2 3 4 567 8 D7 D6 D5 D4 D3 12 34 5 9 L L L L L L L SIO0 ← Address Master Device Operation Tr.
376 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) L L 1 D5 D4 D3 D2 D1 D0 ACK D6 D7 2 3 4 567 8 A6 A5 A4 A3 12 34 9 L L L L SIO0 ← Data Master Device Operation Transfer Line SIO0 �.
377 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) L L L 1 A0 A1 A2 A3 A4 A5 A6 R ACK 2 3 4 567 8 D6 D7 D5 D4 D3 2 13 4 5 9 L L L SIO0 ← Address Master Device Operation Transfer Lin.
378 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) L L L L H H L 1 D1 D0 D2 D3 D4 D5 D6 D7 ACK 2 3 4 567 8 D6 D7 D5 D4 D3 2 13 4 5 9 L L L SIO0 ← FFH Master Device Operation Transfe.
379 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) L L 1 D1 D0 D2 D3 D4 D5 D6 D7 NAK 2 3 4 567 8 A6 A5 A4 A3 12 34 9 L L SIO0 ← FFH Master Device Operation Transfer Line SIO0 ← Ad.
380 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) SCL CLC CMDT CLD SDA0(SDA1) 17.4.5 Cautions on use of I 2 C bus mode (1) Start condition output (master) The SCL pin normally outputs a low-level signal when no serial clock is output.
381 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Writing FFH to SIO0 Setting CSIIF0 Setting ACKD Serial Reception 9 a 23 A0 R ACK D7 D6 D5 P27 output latch 1 Setting CSIIF0 ACK outp.
382 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Writing data to SIO0 Setting CSIIF0 Setting ACKD Serial Transmission 92 3 A0 ACK D7 D6 D5 P27 output latch 1 Setting CSIIF0 ACK Outp.
383 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (4) Reception completion of salve In the reception completion processing of the slave, check the bit 3 (CMDD) of the serial bus interface control register (SBIC) and bit 6 (COI) of the serial operation mode register 0 (CSIM0) (when CMDD = 1).
384 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) • Example of program releasing serial transfer status SET1 P2.5; <1> SET1 PM2.5; <2> SET1 PM2.7; <3> CLR1 CSIE0; <4> SET1 CSIE0; <5> SET1 RELT; <6> CLR1 PM2.
385 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 17.4.7 SCK0/SCL/P27 pin output manipulation The SCK0/SCL/P27 pin can execute static output via software, in addition to outputting the normal serial clock.
386 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) CLC (manipulated by bit manipulation instruction) Wait request signal Serial clock (low while transfer is stopped) SCL Figure 17-29. Logic Circuit of SCL Signal Remarks 1. This figure indicates the relation of the signals and does not indicate the internal circuit.
387 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.1 Serial Interface Channel 1 Functions Serial interface channel 1 employs the following three modes. • Operation stop mode • 3-wire serial I/O mode •.
388 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware. Table 18-1.
389 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-1. Serial Interface Channel 1 Block Diagram RE ARLD ERCE ERR TRF STRB BUSY 1 BUSY 0 Internal Bus Automatic Data Transmit/Receive Control Register Se.
390 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (1) Serial I/O shift register 1 (SIO1) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock.
391 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.3 Serial Interface Channel 1 Control Registers The following four types of registers are used to control serial interface channel 1.
392 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Serial Interface Channel 1 Serial Clock Selection TCL37 TCL36 TCL35 TCL34 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f XX /2 f XX /2 2 f XX /2 3 f XX /2 4 f XX /2 5 f XX /2 6 f XX /2 7 f XX /2 8 Setting prohibited f X /2 2 (1.
393 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Serial operating mode register 1 (CSIM1) This register sets serial interface channel 1 serial clock, operating mode, operation enable/stop and automatic transmit/receive operation enable/stop. CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction.
394 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Automatic data transmit/receive control register (ADTC) This register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable, error check enable/disable and displays automatic transmit/receive execution and error detection.
395 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Data Transfer Interval Specification (f XX = 5.0 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Minimum Note 2 18.
396 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Data Transfer Interval Specification (f XX = 5.0 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Minimum Note 223.
397 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Data Transfer Interval Specification (f XX = 2.5 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Minimum Note 2 36.
398 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Data Transfer Interval Specification (f XX = 2.5 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Minimum Note 446.
399 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Operation enable 6543210 7 Symbol CSIM1 CSIE1 DIR ATE 0 0 0 CSIM11 CSIM10 SCK1 (Input) CSIE1 0 FF68H 00H R/W Address After Reset R/W CSIM11 P20 PM21 P21 PM22 .
400 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Operation enable SCK1 (Input) CSIE1 0 CSIM11 P20 PM21 P21 PM22 Note 3 Shift Register 1 Operation Serial Clock Counter Operation Control SI1/P20 Pin Function S.
401 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units.
402 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Start bit switching is realized by switching the bit order write to SIO1. The SIO1 shift order remains unchanged.
403 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of a maximum of 32-byte data without the use of software.
404 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Notes 1. If the external clock input has been selected with CSIM11 set to 0, set bit 1 (BUSY 1) and bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) to 0, 0. 2. Can be used freely as port function.
405 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 6543210 7 Symbol ADTC RE ARLD ERCE ERR TRF STRB BUSY1 BUSY0 FF69H 00H R/W Note 1 Address After Reset R/W BUSY1 0 1 1 Busy Input Control Not using busy input B.
406 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction.
407 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Data Transfer Interval Specification (f XX = 5.0 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Minimum Note 223.
408 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Data Transfer Interval Specification (f XX = 2.5 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Minimum Note 2 36.
409 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Data Transfer Interval Specification (f XX = 2.5 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Minimum Note 446.
410 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FAC0H of internal buffer RAM (up to FADFH at maximum). The transmit data should be in the order from high-order address to low-order address.
411 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CSIIF1 TRF SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Interval (3) Communication operation (.
412 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-9. Basic Transmission/Reception Mode Flowchart ADTP: Automatic data transmit/receive address pointer ADTI: Automatic data transmit/receive interval .
413 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission/reception (ARLD = 0, RE = 1) in basic transmit/receive mode, internal buffer RAM operates as follows.
414 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Receive data 1 (R1) Receive data 2 (R2) Receive data 3 (R3) Receive data 4 (R4) Receive data 5 (R5) Receive data 6 (R6) FADFH FAC5H FAC0H SIO1 1 CSIIF1 0 ADTP.
415 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Basic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transmission is started by writing the desired data to serial I/O shift register 1 (SIO1) when bit 7 (CSIE1) of serial operation mode register 1 (CSIM1) is set at 1.
416 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-12. Basic Transmission Mode Flowchart ADTP: Automatic data transmit/receive address pointer ADTI: Automatic data transmit/receive interval specify r.
417 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Transmit data 5 (T5) Transmit data 6 (T6) FADFH FAC5H FAC0H SIO1 0 CSIIF1 5 ADTP –1 In 6-byte transmission (ARLD=0, RE=0) in basic transmit mode, internal buffer RAM operates as follows.
418 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Transmit data 5 (T5) Transmit data 6 (T6) FADFH FAC5H FAC0H SIO1 1 CSIIF1 .
419 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Repeat transmission mode In this mode, data stored in the internal buffer RAM is transmitted repeatedly. Serial transmission is started by writing the desired data to serial I/O shift register 1 (SIO1) when bit 7 (CSIE1) of serial operation mode register 1 (CSIM1) is set at 1.
420 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-15. Repeat Transmission Mode Flowchart ADTP: Automatic data transmit/receive address pointer ADTI: Automatic data transmit/receive interval specify .
421 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD = 1, RE = 0) in repeat transmit mode, internal buffer RAM operates as follows. (i) Before transmission (See Figure 18-16 (a).
422 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Transmit data 5 (T5) Transmit data 6 (T6) FADFH FAC5H FAC0H SIO1 0 CSIIF1 .
423 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Restart Command CSIE1 = 1, Write to SIO1 Suspend .
424 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Synchronization control Busy control and strobe control are functions for synchronizing sending and receiving between the master device and slave device. By using these functions, it is possible to detect bit slippage during sending and receiving.
425 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Furthermore, in the case that the busy control option is used, select the internal clock for the serial clock. The busy signal cannot be controlled with an external clock. The operation timing when the busy control option is used is shown in Figure 18-19.
426 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-20 Busy Signal and Wait Cancel (When BUSY0 = 0) (b) Busy & strobe control option Strobe control is a function for synchronizing the sending and receiving of data between a master device and slave device.
427 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 STB BUSY SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 TRF Busy Input Valid Busy Input Release CSIIF1 Figure 18-21.
428 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Bit Slippage Detection Function Through the Busy Signal During an auto send and receive operation, noise occur in the serial clock signal output by the master device and bit slippage may occur in the slave device side serial clock.
429 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the internal buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit/ receive.
430 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 f X f CPU SCK1 SO1 SI1 T CPU T SCK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Interval (a) When the automatic transmit/receive function is used by the internal clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is set at (1), the internal clock operates.
431 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) When the automatic transmit/receive function is used by the external clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is cleared to 0, external clock operation is set.
432 [MEMO].
433 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption.
434 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 19-1.
435 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Internal Bus Asynchronous Serial Interface Mode Register Asynchronous Serial Interface Status Register Receive Buffer Register (RXB/SIO2) Direction Control Ci.
436 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 TPS3 TPS2 TPS1 TPS0 Internal Bus MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Control Register 4 TXE CSIE2 5-Bit Counter Selector Selector Decoder 1/2 Selector Tra.
437 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data.
438 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 6543210 7 Symbol CSIM2 CSIE2 0 0 0 0 CSIM 22 CSCK 0 FF72H 00H R/W Address After Reset R/W CSCK 0 1 Serial Operating Mode Selection UART mode 3-wire serial I/O mode CSIM22 0 1 First Bit Specification MSB LSB CSIE2 0 1 Operation Control in 3-wire Serial I/O Mode Operation stopped Operation enabled 19.
439 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 6543210 7 Symbol ASIM TXE RXE PS1 PS0 CL SL ISRM SCK FF70H 00H R/W Address After Reset R/W SCK 0 1 Clock Selection in Asynchronous Serial Interface Mode Input.
440 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) 3-wire Serial I/O Mode Table 19-2. Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode P72/SCK2 /ASCK Pin Functions P71/SO2 /TxD Pi.
441 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 PE 6543210 7 Symbol ASIS 0 0 0 0 0 FE OVE FF71H 00H R Address After Reset R/W OVE 0 1 Overrun Error Flag Overrun error not generated Overrun error generated N.
442 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Baud Rate Generator Input Clock Selection MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 .
443 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-6. Baud Rate Generator Control Register Format (2/2) 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS = 1 MCS = 0 0000 f XX /2 10 f XX /2 10 (4.9 kHz) f X /2 11 (2.4 kHz) 11 0101 f XX f X (5.
444 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin.
445 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression.
446 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 19.
447 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 SL 6543210 7 Symbol ASIM TXE RXE PS1 PS0 CL ISRM SCK FF70H 00H R/W Address After Reset R/W RXE 0 1 Receive Operation Control Receive operation stopped Receive.
448 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 6543210 7 Symbol CSIM2 CSIE2 0 0 0 0 CSIM 22 CSCK 0 CSCK 0 1 Serial Operating Mode Selection UART mode 3-wire serial I/O mode CSIM22 0 1 First Bit Specification MSB LSB CSIE2 0 1 Operation Control in 3-wire Serial I/O Mode Operation stopped Operation enabled FF72H 00H R/W Address After Reset R/W 19.
449 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 6543210 7 Symbol ASIM TXE RXE PS1 PS0 CL SL ISRM SCK FF70H 00H R/W Address After Reset R/W SCK 0 1 Clock Selection in Asynchronous Serial Interface Mode Input.
450 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 PE 6543210 7 Symbol ASIS 0 0 0 0 0 FE OVE FF71H 00H R Address After Reset R/W OVE 0 1 Overrun Error Flag Overrun error not generated Overrun error generated N.
451 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Baud Rate Generator Input Clock Selection MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 .
452 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS = 1 MCS = 0 0000 f XX /2 10 f X /2 10 (4.9 kHz) f X /2 11 (2.4 kHz) 11 0101 f XX f X (5.0 MHz) f X /2 (2.5 MHz) 1 0110 f XX /2 f X /2 (2.5 MHz) f X /2 2 (1.
453 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin.
454 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression.
455 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 19-7. Figure 19-7. Asynchronous Serial Interface Transmit/Receive Data Format 1 data frame is composed of each of the bits shown below.
456 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected.
457 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 D1 D2 D6 D7 Parity D0 TxD (Output) INTST STOP START D1 D2 D6 D7 Parity D0 TxD (Output) INTST STOP START (c) Transmission A transmit operation is started by writing transmit data to the transmit shift register (TXS).
458 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (d) Reception When bit 6 (RXE) of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM.
459 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (e) Receive errors Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error.
460 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) UART mode cautions (a) If bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) is cleared to (0) during transmission and sending operation is halt, be sure to set the transmit shift register (TXS) to FFH, then set TXE to 1 before executing the next transmission.
461 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75X/XL Series, 78K Series, 17K Series, etc.
462 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 6543210 7 Symbol ASIM TXE RXE PS1 PS0 CL SL ISRM SCK FF70H 00H R/W Address After Reset R/W SCK 0 1 Clock Selection in Asynchronous Serial Interface Mode Input.
463 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Baud Rate Generator Input Clock Selection MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 .
464 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS = 1 MCS = 0 0000 f XX /2 10 f X /2 10 (4.9 kHz) f X /2 11 (2.4 kHz) 11 0101 f XX f X (5.0 MHz) f X /2 (2.5 MHz) 1 0110 f XX /2 f X /2 (2.5 MHz) f X /2 2 (1.
465 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described below. BRGC setting is not required if an external serial clock is used. (i) When the baud rate generator is not used: Select a serial clock frequency with TPS0 to TPS3.
466 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 SI2 SCK2 12345678 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO2 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SRIF Transfer Start at the Falling Edge of SCK2 End of Transfer (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units.
467 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 19-13 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus.
468 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.4 Restrictions on using UART mode In the UART mode, a receive completion interrupt request (INTSR) is generated after a certain period of time following the generation and clearing of the receive error interrupt request (INTSER).
469 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 RxD (Input) INTSR INTSER (when Framing or Overrun Error is Generated) INTSER (when Parity Error is Generated) D0 T1 T2 D1 D2 D6 D7 STOP ST ART Parity Figure 19-15.
470 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 [Example] INTSER is Generated 7 Clocks (MIN.) of CPU Clock (Time from Interrupt Request to Servicing) Instructions for 2205 clocks (MIN.
471 CHAPTER 20 REAL-TIME OUTPUT PORT 20.1 Real-Time Output Port Functions Data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupt request or external interrupt request generation, then output externally.
472 CHAPTER 20 REAL-TIME OUTPUT PORT 20.2 Real-Time Output Port Configuration The real-time output port consists of the following hardware. Table 20-1.
473 CHAPTER 20 REAL-TIME OUTPUT PORT (1) Real-time output buffer register (RTBL, RTBH) Addresses of RTBL and RTBH are mapped individually in the Special function register (SFR) area as shown in Figure 20-2. When specifying 4 bits × 2 channels as the operating mode, data are set individually in RTBL and RTBH.
474 CHAPTER 20 REAL-TIME OUTPUT PORT 20.3 Real-Time Output Port Control Registers The following three registers control the real-time output port. • Port mode register 12 (PM12) • Real-time output.
475 CHAPTER 20 REAL-TIME OUTPUT PORT (3) Real-time output port control register (RTPC) This register sets the real-time output port operating mode and output trigger. Table 20-3 shows the relation between the operating mode of the real-time output port and output trigger.
476 [MEMO].
477 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled status.
478 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 0 – INTWDT 21.2 Interrupt Sources and Configuration Combining all the factors in interrupts, non-maskable interrupts, maskable interrupts and software interrupts, there are a total of 22 source (see Table 21-1 ).
479 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Table 21-1. Interrupt Source List (2/2) Interrupt Source Name Trigger INTTM3 Reference time interval signal from Internal 001EH (B) watch timer INTTM00 Gene.
480 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Internal Bus IE PR ISP MK IF Priority Control Circuit Vector Table Address Generator Standby Release Signal Interrupt Request Sampling Clock Edge Detector S.
481 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Internal Bus Priority Control Circuit Vector Table Address Generator Interrupt Request External Interrupt Mode Register (INTM0, INTM1) Edge Detector Interrupt Request IE PR ISP MK IF Priority Control Circuit Vector Table Address Generator Standby Release Signal Internal Bus Figure 21-1.
482 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions.
483 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 7 PIF6 Symbol IF0L 6 PIF5 5 PIF4 4 PIF3 3 PIF2 2 PIF1 1 PIF0 0 TMIF4 Address FFE0H 00H After Reset R/W R/W × × IF × 0 1 Interrupt Request Flag No interru.
484 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 7 PMK6 Symbol MK0L 6 PMK5 5 PMK4 4 PMK3 3 PMK2 2 PMK 1 PMK 0 TMMK4 Address FFE4H FFH After Reset R/W R/W × × MK × 0 1 Interrupt Servicing Control Interru.
485 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 7 PPR6 Symbol PR0L 6 PPR5 5 PPR4 4 PPR3 3 PPR2 2 PPR1 1 PPR0 0 TMPR4 Address FFE8H FFH After Reset R/W R/W 0 1 Priority Level Selection High priority level .
486 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Address FFECH 00H After Reset R/W R/W 0 0 1 1 INTP0 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES11 7 ES.
487 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Address FFEDH 00H After Reset R/W R/W 0 0 1 1 INTP3 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES41 7 ES.
488 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Address FF47H 00H After Reset R/W R/W 0 0 1 1 INTP0 Sampling Clock Selection f xx /2 N f xx /2 7 f xx /2 5 f xx /2 6 SCS1 7 0 Symbol SCS 6 0 5 0 4 0 3 0 2 0 1 SCS1 0 SCS0 0 1 0 1 SCS0 MCS = 1 MCS = 0 f x /2 7 (39.
489 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (b) When input is equal to or twice the sampling cycle (t SMP ) The noise elimination circuit sets the interrupt request flag (PIF0) at (1) when the sampled INTP0 input level is active twice in succession. Figure 21-8 shows the input/output timing of the noise elimination circuit.
490 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt processing are mapped.
491 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4 Interrupt Servicing Operations 21.4.1 Non-maskable interrupt acknowledge operation A non-maskable interrupt request is received without condition even when in the interrupt request reception prohibited state.
492 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS WDTM4=1 (with watchdog timer mode selected)? Overflow in WDT? WDTM3=0 (with non-maskable interrupt selected)? Interrupt request generation WDT interrupt ser.
493 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-12. Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt se.
494 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.2 Maskable Interrupt request reception For a maskable interrupt request, the interrupt request flag is set at (1) and if the mask (MK) flag of that interrupt is cleared (0), it is possible for it to be received.
495 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-13. Interrupt Request Acknowledge Processing Algorithm XXIF : Interrupt Request Flag XXMK : Interrupt Mask Flag XXPR : Priority Order Specificatio.
496 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-14. Interrupt Request Acknowledge Timing (Minimum Time) Remark 1 clock : (f CPU : CPU clock) Figure 21-15.
497 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.3 Software interrupt request acknowledge operation A software interrupt request is received by the execution of a BRK command.
498 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Table 21-4. Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing Maskable Interrupt Request PR = 0 PR = 1 IE = 1 IE = 0 IE = 1 IE = 0 Non-maskable interrupt D D D D D ISP=0 E E D D D ISP=1 E E D E D Software interrupt E E D E D Remarks 1.
499 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Main Processing EI INTxx (PR=1) INTyy (PR=0) IE=0 EI RETI INTxx Servicing INTzz (PR=0) IE=0 EI RETI INTyy Servicing IE=0 RETI INTzz Servicing Figure 21-16. Multiple Interrupt Example (1/2) Example 1 Example of multiple interrupt requests being generated twice.
500 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Main Processing INTxx Servicing INTyy Servicing INTxx (PR=0) 1 Instruction Execution IE=0 INTyy (PR=0) IE=0 RETI RETI EI Example 3 Example of a multiple interrupt not being generated because an interrupt was not permitted.
501 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.5 Interrupt request reserve Among the commands, there are some for which, even if an interrupt request is generated while they are being executed, reception of the interrupt request is held until execution of the next command is completed.
502 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Internal bus MK IF Test input signal Standby release signal 21.5 Test Functions When a clock timer overflow occurs and when the port 4 falling edge is detected, a corresponding test input flag is set (1) and a standby release signal is generated.
503 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag register 1L (IF1L) It indicates whether a watch timer overflow is detected or not. It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. It is set to 00H by the RESET signal input.
504 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 7 0 Symbol KRM 6 0 5 0 4 0 3 0 2 0 1 KRMK 0 KRIF Address FFF6H 02H After Reset R/W R/W 0 1 Key Return Signal Not detected Detected (port 4 falling edge dete.
505 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.1 External Device Expansion Functions The external device expansion functions connect external devices to areas other than the internal ROM, RAM, and SFR. Connection of external devices uses ports 4 to 6.
506 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Memory maps when using the external device expansion function are as follows. Figure 22-1. Memory Map When Using External Device Expansion Function (1/2) (a) Memory Map of the µ PD78056F and 78056FY, and of the µ PD78P058F and 78P058FY when the internal PROM is 48 Kbytes.
507 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION FFFFH SFR Internal High-Speed RAM FF00H FEFFH FB00H FAFFH FAE0H FADFH FAC0H FABFH F800H F7FFH F400H F3FFH F000H EFFFH 0000H Reserved Internal Buffer R.
508 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 7 0 Symbol MM 6 0 5 PW1 4 PW0 3 0 2 MM2 1 MM1 0 MM0 Address FFF8H 10H After Reset R/W R/W MM2 MM1 MM0 Single-chip/ Memory Expansion Mode Selection P40.
509 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION (2) Memory size switching register (IMS) This register specifies the internal memory size. In principle, use IMS in a default status.
510 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin.
511 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ASTB RD Lower Address Operation Code AD0 to AD7 A8 to A15 Higher Address WAIT ASTB RD AD0 to AD7 A8 to A15 Lower Address Operation Code Higher Address Internal Wait Signal ( 1-clock wait ) ASTB RD AD0 to AD7 A8 to A15 Lower Address Operation Code Higher Address Figure 22-4.
512 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ASTB RD Lower Address Read Data AD0 to AD7 A8 to A15 Higher Address WAIT ASTB RD AD0 to AD7 A8 to A15 Lower Address Read Data Higher Address Internal Wait Signal (1-clock wait) Higher Address ASTB RD AD0 to AD7 A8 to A15 Lower Address Read Data Figure 22-5.
513 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ASTB WR Higher Address AD0 to AD7 A8 to A15 WAIT Hi-Z Lower Address Write Data ASTB WR AD0 to AD7 A8 to A15 Lower Address Write Data Higher Address Internal Wait Signal ( 1-clock wait ) Hi-Z ASTB WR AD0 to AD7 A8 to A15 Lower Address Write Data Hi-Z Higher Address Figure 22-6.
514 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ASTB RD WR Higher Address AD0 to AD7 A8 to A15 WAIT Hi-Z Lower Address Write Data Read Data Lower Address Higher Address Internal Wait Signal (1-clock.
515 CHAPTER 23 STANDBY FUNCTION 23.1 Standby Function and Configuration 23.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode.
516 CHAPTER 23 STANDBY FUNCTION STOP Mode Clear X1 Pin Voltage Waveform V SS a 23.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS).
517 CHAPTER 23 STANDBY FUNCTION 23.2 Standby Function Operations 23.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below.
518 CHAPTER 23 STANDBY FUNCTION HALT Instruction Interrupt Request Wait Standby Release Signal Operating Mode Clock HALT Mode Wait Oscillation Operating Mode (2) HALT mode clear The HALT mode can be cleared with the following four types of sources.
519 CHAPTER 23 STANDBY FUNCTION (d) Clear upon RESET input The HALT mode is cleared upon RESET signal input. As is the case with normal reset operation, a program is executed after branching to the reset vector address. Figure 23-3. HALT Mode Release by RESET Input Remarks 1.
520 CHAPTER 23 STANDBY FUNCTION 23.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock.
521 CHAPTER 23 STANDBY FUNCTION STOP Instruction Wait (Time set by OSTS) Oscillation Stabilization Wait Status Operating Mode Oscillation Operationg Mode STOP Mode Oscillation Stop Oscillation Standby Release Signal Clock Interrupt Request (2) STOP mode release The STOP mode can be cleared with the following three types of sources.
522 CHAPTER 23 STANDBY FUNCTION RESET Signal Operating Mode Clock Reset Period STOP Mode Oscillation Stop Oscillation Stabilization Wait Status Operating Mode Oscillation Wait (2 17 /f x : 26.
523 RESET Count Clock Reset Control Circuit Watchdog Timer Stop Over- flow Reset Signal Interrupt Function CHAPTER 24 RESET FUNCTION 24.1 Reset Function The following two operations are available to generate the reset signal.
524 CHAPTER 24 RESET FUNCTION RESET Internal Reset Signal Port Pin Delay Delay Hi-Z X1 Normal Operation Reset Period (Oscillation Stop) Oscillation Stabilization Time Wait Normal Operation (Reset Proc.
525 CHAPTER 24 RESET FUNCTION Table 24-1. Hardware Status After Reset (1/2) Hardware Status after Reset Program counter (PC) Note 1 The contents of reset vector tables (0000H and 0001H) are set.
526 CHAPTER 24 RESET FUNCTION Table 24-1. Hardware Status after Reset (2/2) Hardware Status after Reset Watch timer Mode control register (TMC2) 00H Clock select register (TCL2) 00H Mode register (WDT.
527 Match CORENn CORSTn Program counter (PC) Comparator Correction address register n (CORADn) Internal bus Correction control register Correction branch request signal (BR !7FDH) CHAPTER 25 ROM CORRECTION 25.
528 CHAPTER 25 ROM CORRECTION FF3AH/FF3BH 0000H Symbol 15 CORAD0 0 Address FF38H/FF39H After Reset 0000H R/W R/W CORAD1 R/W (1) Correction address registers 0 and 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the mask ROM.
529 CHAPTER 25 ROM CORRECTION 7 0 6 0 5 0 4 0 COREN1 CORST1 COREN0 CORST0 Symbol CORCN Address FF8AH After Reset COREN0 0 1 CORST0 0 1 COREN1 0 1 CORST1 0 1 R/W R/W Note 00H Correction address registe.
530 CHAPTER 25 ROM CORRECTION 25.4 ROM Correction Application (1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such as EEPROM TM ) outside the microcontroller. When two places should be corrected, store the branch destination judgment program as well.
531 CHAPTER 25 ROM CORRECTION No Yes Initialization Load the contents of external nonvolatile memory into internal expansion RAM Correction address register setting ROM correction enabled Is ROM correction used ? Note ROM correction Main program (2) Assemble in advance the initialization routine as shown in Figure 25-6 to correct the program.
532 CHAPTER 25 ROM CORRECTION No Yes Internal ROM program start Does fetch address match with correction address? Set correction status flag Correction branch (branch to address F7FDH) Correction program execution ROM correction Figure 25-7.
533 CHAPTER 25 ROM CORRECTION ADD A, #2 BR !1002H BR !F702H ADD A, #1 MOV B, A 0000H 0080H Program start 1000H 1002H Internal ROM Internal Expansion RAM F400H F702H F7FDH F7FFH (1) (2) (3) EFFFH 25.
534 CHAPTER 25 ROM CORRECTION Correction Place Internal ROM Internal ROM JUMP FFFFH F7FFH F7FDH xxxxH 0000H (1) (2) (3) BR !JUMP Correction Program 25.6 Program Execution Flow Figures 25-9 and 25-10 show the program transition diagrams when the ROM correction is used.
535 CHAPTER 25 ROM CORRECTION Internal ROM Correction Place 1 Internal ROM JUMP Internal ROM (1) (2) (3) (4) (5) (6) (7) (8) FFFFH F7FFH F7FDH yyyyH xxxxH 0000H BR !JUMP Destination judge program Correction program 2 Correction program 1 Correction Place 2 Figure 25-10.
536 CHAPTER 25 ROM CORRECTION 25.7 Cautions on ROM Correction (1) Address values set in correction address registers 0 and 1 (CORAD0 and CORAD1) must be addresses where instruction codes are stored.
537 CHAPTER 26 µ PD78P058F, 78P058FY The µ PD78P058F and 78P058FY are products which have one time PROM incorporated into them, which it is only possible to write to once. The differences between PROM products ( µ PD78P058F and 78P058FY) and ROM products ( µ PD78056F, 78056FY, 78058F and 78058FY) are shown in Table 26-1.
538 CHAPTER 26 µ PD78P058F, 78P058FY 26.1 Memory Size Switching Register In the µ PD78P058F and 78P058FY, internal memory can be selected through the memory size select register (IMS). The same memory mapping as that of mask ROM versions that have a different internal memory can be done by setting IMS.
539 CHAPTER 26 µ PD78P058F, 78P058FY 7 0 Symbol IXS 6 0 5 0 4 0 3 IXRAM3 2 IXRAM2 1 IXRAM1 0 IXRAM0 Address FFF4H 0AH After Reset Internal Extension RAM Capacity Selection IXRAM3 IXRAM2 IXRAM1 1024 bytes 10 1 Setting prohibited Other than above IXRAM0 0 R/W W 0 bytes 11 00 26.
540 CHAPTER 26 µ PD78P058F, 78P058FY Program inhibit High impedance 26.3 PROM Programming The µ PD78P058F and 78P058FY include on-chip PROM in a 60 Kbyte configuration as program memory.
541 CHAPTER 26 µ PD78P058F, 78P058FY (3) Standby mode Setting CE to H sets the standby mode. In this mode, data output becomes high impedance irrespective of the status of OE. (4) Page data latch mode Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode.
542 CHAPTER 26 µ PD78P058F, 78P058FY 26.3.2 PROM write procedure Figure 26-3. Page Program Mode Flowchart Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Latch X = X + 1 0.
543 CHAPTER 26 µ PD78P058F, 78P058FY Page Data Latch Page Program Program Verify Data Input Data Output Hi-Z A2 to A16 A0, A1 D0 to D7 V PP V DD V PP V DD +1.
544 CHAPTER 26 µ PD78P058F, 78P058FY Figure 26-5. Byte Program Mode Flowchart Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 X = X + 1 0.1-ms program pulse Verify Address = N? V DD = 4.
545 CHAPTER 26 µ PD78P058F, 78P058FY A0 to A16 D0 to D7 Program Program Verify Data Input Data Output V PP V DD V DD +1.5 V DD V IH V IL V IH V IL V IH V IL V PP V DD CE PGM OE Figure 26-6. Byte Program Mode Timing Cautions 1. Be sure to apply V DD before applying V PP , and remove it after removing V PP .
546 CHAPTER 26 µ PD78P058F, 78P058FY Address Input A0 to A16 CE (Input) OE (Input) D0-D7 Hi-Z Data Output Hi-Z 26.3.3 PROM read procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the V PP pin.
547 CHAPTER 26 µ PD78P058F, 78P058FY 26.4 Screening of One-Time PROM Versions One-time PROM versions cannot be fully tested by NEC before shipment due to the structure of one-time PROM.
548 [MEMO].
549 CHAPTER 27 INSTRUCTION SET This chapter describes each instruction set of the µ PD78058F and 78058FY Subseries as list table. For details of its operation and operation code, refer to the separate document 78K/0 Series USER’S MANUAL—Instructions (U12326E) .
550 CHAPTER 27 INSTRUCTION SET 27.1 Legends Used in Operation List 27.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail).
551 CHAPTER 27 INSTRUCTION SET 27.1.2 Description of “operation” column A : A register; 8-bit accumulator X : X register B : B register C : C register D : D register E : E register H : H register .
552 CHAPTER 27 INSTRUCTION SET 27.2 Operation List Clock Flag Note 1 Note 2 ZA C C Y r, #byte 2 4 – r ← byte saddr, #byte 3 6 7 (saddr) ← byte sfr, #byte 3 – 7 sfr ← byte A, r Note 3 12 – .
553 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y rp, #word 3 6 – rp ← word saddrp, #word 4 8 10 (saddrp) ← word sfrp, #word 4 – 10 sfrp ← word AX, saddrp 2 6 8 AX ← (saddrp.
554 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y A, #byte 2 4 – A, CY ← A – byte ×× × saddr, #byte 3 6 8 (saddr), CY ← (saddr) – byte ×× × A, r Note 3 2 4 – A, CY ←.
555 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y A, #byte 2 4 – A ← A byte × saddr, #byte 3 6 8 (saddr) ← (saddr) byte × A, r Note 3 24 – A ← A r × r, A 2 4 – r ← r A .
556 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y ADDW AX, #word 3 6 – AX, CY ← AX + word ×× × SUBW AX, #word 3 6 – AX, CY ← AX – word ×× × CMPW AX, #word 3 6 – AX –.
557 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y CY, saddr.bit 3 6 7 CY ← CY (saddr.bit) × CY, sfr.bit 3 – 7 CY ← CY sfr.bit × AND1 CY, A.bit 2 4 – CY ← CY A.bit × CY, PSW.bit 3 – 7 CY ← CY PSW.bit × CY, [HL].bit 2 6 7 + n CY ← CY (HL).
558 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y (SP – 1) ← (PC + 3) H , (SP – 2) ← (PC + 3) L , PC ← addr16, SP ← SP – 2 (SP – 1) ← (PC + 2) H , (SP – 2) ← (PC +.
559 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y saddr.bit, $addr16 3 8 9 PC ← PC + 3 + jdisp8 if(saddr.bit) = 1 sfr.bit, $addr16 4 – 11 PC ← PC + 4 + jdisp8 if sfr.bit = 1 BT A.bit, $addr16 3 8 – PC ← PC + 3 + jdisp8 if A.bit = 1 PSW.
560 CHAPTER 27 INSTRUCTION SET 27.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, .
561 CHAPTER 27 INSTRUCTION SET Second Operand [HL + byte] #byte A r Note sfr saddr !addr16 PSW [DE] [HL] [HL + B] $addr16 1 None First Operand [HL + C] A ADD MOV MOV MOV MOV MOV MOV MOV MOV ROR ADDC X.
562 CHAPTER 27 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand First Operand AX ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW rp MOVW MOVW Not.
563 CHAPTER 27 INSTRUCTION SET AX !addr16 !addr11 [addr5] $addr16 (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand First Operand B.
564 [MEMO].
565 APPENDIX A. DIFFERENCES AMONG µ PD78054, 78058F, AND 780058 SUBSERIES The major differences among the µ PD78054, 78058F, and 780058 Subseries are shown in Table A-1.
566 APPENDIX A. DIFFERENCES AMONG µ PD78054, 78058F, AND 780058 SUBSERIES Table A-1. Major Differences Among µ PD78054, 78058F, and 780058 Subseries (2/2) Product Name µ PD78054 Subseries µ PD7805.
567 APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the µ PD78058F and 78058FY Subseries.
568 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K0-NS Debugging tools • System simulator • Integrated debugger • Device .
569 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (2/2) (2) When using in-circuit emulator IE-78001-R-A Remark The areas shown with dotted lines differ depending on the development environment.
570 APPENDIX B DEVELOPMENT TOOLS B.1 Language Processing Software RA78K/0 Program that converts program written in mnemonic into object codes that Assembler package can be executed by microcontroller. In addition, automatic functions to generate symbol table and optimize branch instructions are also provided.
571 APPENDIX B DEVELOPMENT TOOLS B.2 PROM Programming Tool B.2.1 Hardware PG-1500 This is a PROM programmer capable of programming the single-chip microcontroller with on-chip PROM programmer PROM by manipulating from the stand-alone or host machine through connection of the separately available programmer adapter and the attached board.
572 APPENDIX B DEVELOPMENT TOOLS B.3 Debugging Tool B.3.1 Hardware (1/2) (1) When using in-circuit emulator IE-78K0-NS IE-78K0-NS Note The in-circuit emulator serves to debug hardware and software when In-circuit emulator developing application systems using a 78K/0 Series product.
573 APPENDIX B DEVELOPMENT TOOLS B.3.1 Hardware (2/2) (2) When using in-circuit emulator IE-78001-R-A IE-78001-R-A Note 1 The in-circuit emulator serves to debug hardware and software when In-circuit emulator developing application systems using a 78K/0 Series product.
574 APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (1/2) SM78K0 This simulator can debug target system at C source level or assembler level while System simulator simulating operation of target system on host machine.
575 APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (2/2) ID78K0-NS Note This is a control program that is used to debug the 78K/0 Series. Integrated debugger It uses Windows on a personal computer and OS.
576 APPENDIX B DEVELOPMENT TOOLS B.4 OS for IBM PC The following OSs for the IBM PC are supported. Table B-1. OS for IBM PC OS Version PC DOS Ver. 5.02 to Ver. 6.3 J6.1/V Note to J6.3/V Note IBM DOS TM J5.02/V Note MS-DOS Ver. 5.0 to Ver. 6.22 5.0/V Note to 6.
577 APPENDIX B DEVELOPMENT TOOLS Drawing and Footprint for Conversion Socket (EV-9200GC-80) Figure B-2. EV-9200GC-80 Drawings (For Reference Only) A F D 1 No .1 pin inde x E EV -9200GC-80 B C M N O L K S R Q P I H J G EV -9200GC-80-G1E ITEM MILLIMETERS INCHES A B C D E F G H I J K L M N O P Q R S 18.
578 APPENDIX B DEVELOPMENT TOOLS Figure B-3. EV-9200GC-80 Footprints (For Reference Only) F E D G H I J K L C B A 0.026 × 0.748=0.486 0.026 × 0.748=0.486 EV-9200GC-80-P1 ITEM MILLIMETERS INCHES A B C D E F G H I J K L 19.7 15.0 15.0 19.7 6.0 ± 0.05 6.
579 APPENDIX B DEVELOPMENT TOOLS Drawing of Conversion Adapter (TGK-080SDW) Figure B-4. TGK-080SDW Drawings (For Reference) (unit: mm) ITEM MILLIMETERS INCHES b 0.25 0.010 c 5.3 0.209 a 0.5x19=9.5±0.10 0.020x0.748=0.374±0.004 d 5.3 0.209 h 1.85±0.2 0.
580 [MEMO].
581 APPENDIX C EMBEDDED SOFTWARE This chapter describes the embedded software that is available for the µ PD78058F and 78058FY Subseries to allow users to develop and maintain application programs for these subseries.
582 APPENDIX C EMBEDDED SOFTWARE C.1 Real-time OS (1/2) RX78K/0 RX78K/0 is real-time OS conforming to µ ITRON specifications. Real-time OS Tool (configurator) that generates nucleus of RX78K/0 and plural information tables is supplied. Used in combination with an optional assembler package (RA78K/0) and device file (DF78054).
583 APPENDIX C EMBEDDED SOFTWARE Real-time OS (2/2) MX78K0 µ ITRON-specification subset OS. Nucleus of MX78K0 is supplied. OS This OS performs task management, event management, and time management. It controls the task execution sequence for task management and selects the task to be executed next.
584 [MEMO].
585 APPENDIX D REGISTER INDEX D.1 Register Index (Register Name) [A] A/D conversion result register (ADCR) ............................................................................................................. 2 64 A/D converter input select register (ADIS) .
586 APPENDIX D REGISTER INDEX Interrupt request flag register 1L (IF1L) ................................................................................................... 483, 503 Interrupt timing specify register (SINT) .............................
587 APPENDIX D REGISTER INDEX [S] Sampling clock select register (SCS) ......................................................................................................... 186, 488 Serial bus interface control register (SBIC) ....................
588 APPENDIX D REGISTER INDEX CR00: Capture/compare register 00 .......................................................................................................... 1 77 CR01: Capture/compare register 01 .........................................
589 APPENDIX D REGISTER INDEX PCC: Processor clock control register ..................................................................................................... 1 57 PM0: Port mode register 0 ..................................................
590 APPENDIX D REGISTER INDEX TOC1: 8-bit timer output control register ................................................................................................... 22 3 TXS: Transmit shift register .............................................
591 APPENDIX E REVISION HISTORY Major revisions by edition and revised chapters are shown below. Edition Major Revisions from Previous Edition Revised Chapters 2nd The following products have already .
592 [MEMO].
Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation.
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