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MICROCOMPUTER MN101C00 MN101C1 15/1 17 LSI User ’ s Manual Pub. No. 2141 1-01 1E.
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If you have any inquiries or questions about this book or our semiconductors, please contact one of our sales offices listed at the back of this book or Matsushita Electronics Corporation's Sales Department.
How to Read This Manual–1 The MN101C11x incorporates more than one ROM/RAM to meet a variety of applications. An EPROM version as well as a Mask ROM version is available so users can write a program by themselves.
How to Read This Manual–2 ■ Manual Configuration Each section of this manual consists of a title, summary, main text, supplemental information, precautions and warnings. The layout and definition of each section are shown below. Subtitle Sub-subtitle The smallest block in this manual.
■ Finding Desired Information This manual provides four methods for finding desired information quickly and easily. (1) Consult the index at the front of the manual to locate the beginning of each section. (2) Consult the table of contents at the front of the manual to locate desired titles.
0 Contents 1 Chapter 1 Overview 2 Chapter 2 Basic CPU Functions 3 Chapter 3 Port Functions 4 Chapter 4 T imer Functions 5 Chapter 5 Serial Functions 6 Chapter 6 A/D Conversion Functions 7 Chapter 7 AC.
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0 Contents.
Contents Chapter 1 Overview 1-1 Product Overview ...........................................................................................................2 1-1-1 Overview ..............................................................................
Chapter 3 Port Functions 3-1 Overview ......................................................................................................................38 3-2 Port Control Registers .................................................................
Chapter 5 Serial Functions 5-1 Overview ......................................................................................................................92 5-2 Synchronous Serial Interface .........................................................
Appendices 8-1 EPROM V ersions .......................................................................................................130 8-1-1 Overview ..................................................................................................
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1 1 Chapter 1 Overview.
Chapter 1 Overview 2 1-1 Product Overview 1-1-1 Overview The MN101C00 series of 8-bit single-chip microcomputers incorporate several types of peripheral functions.
Chapter 1 Overview 3 Hardware Functions 1-2 Hardware Functions ROM/RAM Size: <Single chip mode> Internal ROM ∗ 2 16,384 × 8-bit* 3 Internal RAM ∗ 2 512 × 8-bit Machine Cycles: High speed mode 0.10µ s/20MHz (4.5V to 5.5V) 0.25µ s/8MHz(2.7V to 5.
Chapter 1 Overview 4 Timers 2 and 3 can be cascaded. Timer 4 16-bit timer Square wave output, 16-bit PWM output are possible. Clock source: fosc, fs/4, fs/16, TM4IO pin input Input capture function Ti.
Chapter 1 Overview 5 Pins 1-3 Pins 1-3-1 Pin Diagram Figure 1-3-1 Pin Diagram (42-SDIP: TOP VIEW) TXD,SBO0,P00 RXD,SBI0,P01 SBT0,P02 BUZZER, P06 RMOUT,P10 P11 TM2IO,.
Chapter 1 Overview 6 Figure 1-3-2 Pin Diagram (44-QFP: TOP VIEW) MN101C117/115 LED3,P83 LED2,P82 LED1,P81 LED0,P80 AN6,PA6 AN0,PA0 AN1,PA1 AN2,PA2 AN3,.
Chapter 1 Overview 7 Pins Figure 1-3-3 Pin Diagram (48-QFH: TOP VIEW) LED3,P83 LED2,P82 LED1,P81 LED0,P80 NC AN6,PA6 AN0,PA0 AN1,PA1 AN2,PA2 AN3.
Chapter 1 Overview 8 1-3-2 Pin Function Summary *The pin numbers in the list correspond to the QFH package(Refer to Figure 1-3-3 Pin connection.) Be careful when using SDIP and QFP packages. Table 1-3-1 Pin Function Summary (1/4) Pins Pin No. Name Type Dual Function Function Description 17 VSS – Power supply pins Apply 2.
Chapter 1 Overview 9 Table 1-3-1 Pin Function Summary (2/4) 41 to 42 P70 to P71 I/O I/O port 7 2-bit CMOS tri-state I/O port. Each individual bit can be switched to an input or output by the P7DIR register. A pull-up or pull-down resistor for each bit can be selected individually by the P7PLUD register.
Table 1-3-1 Pin Function Summary (3/4) 22 Buzzer I/O P06 Buzzer output Chapter 1 Overview 10 Pins Pin No. Name Type Dual Function Function Description 20 TXD Output SBO0(P00) UART transmit data output pin 21 RXD Input SBI0(P01) UART receive data input pin 20 SBO0 Output TXD(P00) Transmit data output pin for serial interfaces 0.
Chapter 1 Overview Pins Table 1-3-1 Pin Function Summary (4/4) 11 Pin No. Name Type Dual Function Function Description The valid edge for these external interrupt input pins can be selected with the IRQnICR registers. IRQ1 is an external interrupt pin that is able to determine AC zero crossings.
Chapter 1 Overview 12 Overview of Function 1-4 Overview of Functions 1-4-1 Block Diagram Figure 1-4-1 Block Diagram of Functions) CPU MN101C00 System clock oscillator Sub-clock oscillator ROM 16 KB RA.
Chapter 1 Overview 13 Electrical Characteristics 1-5 Electrical Characteristics 1-5-1 Absolute Maximum Ratings ∗ 2 ∗ 3 Note: ∗ 1 Applicable even for an interval of 100ms. *2 Insert at least one bypass capacitor of 0.1 µ F or more between a power source pin and GND to prevent from latchup.
Chapter 1 Overview 14 Electrical Characteristics 1-5-2 Operating Conditions Ta=–40 to +85°C V DD =2.0 to 5.5V V SS =0V Note: *1. Only for 48-QFH package ∗ 2 t c1 , t c2 , t c3 : OSC1 is the CPU clock t c4 : XI is the CPU clock Parameter Symbol Conditions Rating Unit MIN TYP MAX Supply voltage 1V DD1 fosc ≤ 20.
Chapter 1 Overview 15 Electrical Characteristics ∗ 1 Set the clock duty ratio to 45 to 55%. *2 Applicable only for 48-pin QFH package Parameter Symbol Conditions Rating Unit MIN TYP MAX External clock input 1 OSC1 (OSC2 is unconnected) 18 Clock frequency f OSC 1.
Chapter 1 Overview 16 Electrical Characteristics Figure 1-5-3 OSC1 Timing Chart Figure 1-5-4 XI Timing Chart twh1 twl1 0.9V DD 0.1V DD twf1 twr1 twh2 twl2 0.
1-5-3 DC Characteristics Ta=–40 to +85°C V DD =2.0 to 5.5V V SS =0V Notes: ∗ 1 Measured under conditions of Ta=25°C and no load. The supply current during operation, I DD1 (I DD2 ), is measured .
Chapter 1 Overview 18 Electrical Characteristics Ta=–40 to +85°C V DD =2.0 to 5.5V V SS =0V Parameter Symbol Conditions Rating Unit MIN TYP MAX Input pin 1 MMOD 8 Input high voltage 1 V IH1 0.8V DD V DD V 9 Input high voltage 2 V IH2 V DD =4.5 to 5.
Chapter 1 Overview 19 Electrical Characteristics SENS pin Figure 1-5-5 Operation of AC Zero-Cross Detection Circuit Ta=–40 to +85°C V DD =2.0 to 5.5V V SS =0V ← trs → Input voltage level 1 → Input voltage level 2 → (Input) (Output) V DD V DHL V DHH V DLL V DLH V SS ← tfs → 27 Rise time trs Fig.
Chapter 1 Overview 20 Electrical Characteristics Ta=–40 to +85°C V DD =2.0 to 5.5V V SS =0V Parameter Symbol Conditions Rating Unit MIN TYP MAX I/O pin 5 P27 (RST) 36 Input high voltage V IH7 0.
Chapter 1 Overview Ta=–40 to +85°C V DD =2.0 to 5.5V V SS =0V 1-5-4 A/D Converter Characteristics Ta=–40 to+85°C V DD =2.0 to 5.5V V SS =0V Parameter Symbol Conditions Rating Unit MIN TYP MAX 1 .
Chapter 1 Overview 1-6 Option 1-6-1 ROM Option The product equipped with this LSI or an EPROM with this LSI controls the oscillation mode after resetting as well as the runaway-detection watchdog timer, using bits 2 to 0 of the last address of the built-in ROM.
Chapter 1 Overview 23 Chapter 1 Overview 1-6-2 Option Form 1. Oscillation mode MN101C Model Name Customer Approval Date: SE No. Type A Type B 2. Watchdog timer period setting Detection Period fs/2 16 fs/2 18 fs/2 20 Not used Selection Note: Type A: Operation begins from the reset cycle in the NORMAL mode.
Chapter 1 Overview 24 External Dimensions 1-7 Outline Drawings Body Material: Epoxy Resin Lead Material:Fe Ni Lead Finish Method:Soldering dip Figure 1-7-1 42-SDIP The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office.
Chapter 1 Overview Body Material: Epoxy Resin Lead Material:Fe Ni Lead Finish Method:Soldering dip Figure 1-7-2 44-QFP Package code: QFP044-P-1010 Unit: mm The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office.
Chapter 1 Overview Material: Epoxy Resin Lead Material:Fe Ni-42 Alloy Lead Finish Method:Soldering dip Figure 1-7-3 48-QFH Package code: QFH048-P-0707 Unit: mm The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office.
27 2 Chapter 2 Basic CPU Functions.
Chapter 2 Basic CPU Functions 28 Overview/Address Space 2-1 Overview Basic CPU functions are in conformance with the MN101C00 series manual (architecture manual). This chapter describes specifications unique to the MN101C117/115. 2-2 Address Space 2-2-1 Memory Configuration Figure 2-2-1 Memory Map ∗ Differs depending upon the model.
Chapter 2 Basic CPU Functions 29 Address Space 2-2-2 Special Function Registers Memory control register(MEMCTR) is a 4-bit register which set up the base Table 2-2-1 Register Map 01 2345 67 89 A B C D.
2-3 Bus Interface 2-3-1 Overview The MN101C117, unlike other MN101C series microcomputers, does not support memory expansion mode and processor mode. 2-3-2 Control Registers The memory control register is a four-bit register that sets up wait-count at a time of access to a base address of interrupt vector table and a special register zone.
Chapter 2 Basic CPU Functions 31 Interrupts PSW New SP (after interrupt is accepted) 7 0 PC8 to 1 PC16 to 9 PC18,17 HA7 to 0 HA15 to 8 PC0 Old SP (before interrupt is accepted) Low Address High 2-4 In.
Chapter 2 Basic CPU Functions 32 Interrupts ■ Operation when Returning from Interrupt After the program POPs the register and other values saved by the interrupt service routine, an RTI instruction is implemented to return to the program that was being executed when the interrupt was received.
2-4-2 Interrupt Sources and V ector Addresses In addition to reset, there are 20 interrupt vectors that indicate the starting addresses of interrupt programs. These vectors are located in the 80-byte ROM address area X'04004' to X'04053'.
2-4-3 Interrupt Control Registers Interrupt control registers consist of the following: a non-maskable interrupt control register (NMICR), external interrupt control registers (IRQnICR), and internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR, ADICR).
■ Internal Interrupt Control Registers (TMnICR, TBICR, SCOICR, ATCICR, ADICR) The internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR, ADICR) control the interrupt levels of internal interrupts, timer interrupts, serial interrupts, A/D conversion complete interrupts, and interrupt request/enable.
Chapter 2 Basic CPU Functions 36 Reset 2-5 Reset The CPU contents are reset and registers are initialized when the RST pin is pulled to low. ■ Initiating a Reset There are two methods to initiate a reset. (1) Drive the RST pin low for at least four clock cycles.
37 3 Chapter 3 Port Functions.
Chapter 3 Port Functions 38 Overview 3-1 Overview A total of 39 pins on the MN101C117, including those shared with special function pins, are allocated for the 7 ports of P0 to P2, P6 to P8, and PA. Each I/O port is assigned according to the special function register area in memory.
Chapter 3 Port Functions 39 Overview ■ Port 1 (P1) 5-bit CMOS tri-state I/O port. Table 3-1-3 Port 1 Functions ■ Port 2 (P2) 4-bit CMOS tri-state input port.
■ Port 7 (P7) 8-bit CMOS tri-state I/O port. Table 3-1-6 Port 7 Functions ■ Port 8 (P8) 8-bit CMOS tri-state I/O port. Table 3-1-7 Port 8 Functions ■ Port A (PA) 8-bit CMOS tri-state input port.
Chapter 3 Port Functions 41 Port Control Registers 3-2 Port Control Registers 3-2-1 Overview 28 registers control the I/O ports. See table 3-2-1. Table 3-2-1 I/O Port Control Registers (1/2) Name Addr.
Table 3-2-1 I/O Port Control Registers (2/2) Chapter 3 Port Functions 42 Port Control Registers Name Address R/W Function P6DIR P7DIR P8DIR P1OMD PAIMD P0PLU P1PLU P2PLU P6PLU P7PLUD P8PLU PAPLUD FLOA.
Chapter 3 Port Functions 43 Port Control Registers Figure 3-2-1 Port Control Registers (1/2) 0 1 2 4 5 6 73 P0OUT (at reset: -0---000) P1OUT (at reset: ---00000) P0IN (at reset: -X---XXX) P1IN (at res.
Figure 3-2-1 Port Control Registers (2/2) Chapter 3 Port Functions 44 Port Control Registers 0 1 2 4 5 6 73 P7OUT (at reset: - - - - - - 00) P8OUT (at reset: 00000000) P7IN (at reset: - - - - - - XX) .
Chapter 3 Port Functions 45 Port Control Registers 3-2-2 I/O Port Control Registers This section describes the special function registers that control the MN101C117's I/O ports. ■ Data Registers • PnOUT registers Data registers to output to the ports.
Chapter 3 Port Functions 46 Port Control Registers ■ Port Output/Input Mode Registers • PnOMD/PnIMD registers These register settings determine whether the port pins(P10 to P14, PA0 to PA5) are used as I/O ports or as special function pins (dual function).
Chapter 3 Port Functions 47 I/O Port Configuration and Functions 3-3 I/O Port Configuration and Functions ■ P00,P02,P10 to P14 R D L Q Reset Write Read Read R D L Q Reset Write Read R D L Q Reset Wr.
Chapter 3 Port Functions 48 I/O Port Configuration and Functions ■ P01 Figure 3-3-2 Configuration and Functions of P01 R D L Q Write Read Read R D L Q Reset Write Read R D L Q Reset Write Read Pull-.
Chapter 3 Port Functions 49 ■ PA0 to PA7 Figure 3-3-3 Configuration and Functions of PA0 to PA7 R D L Q Reset Write Read R D L Q Reset Write Read Read R D L Q Reset Write Read Pull-up/pull-down resi.
Chapter 3 Port Functions 50 I/O Port Configuration and Functions ■ Pin Configuration for P20, P22 to P23 Figure 3-3-4 Configuration and Functions of P20, P22, P23 R D L Q Reset Write Read Read Schmi.
Chapter 3 Port Functions 51 ■ P21 Figure 3-3-5 Configuration and Functions of P21 Data bus R D L Q Reset Read Read Read Schmitt trigger input R D L Q Reset Read Read Pull-up resistor control Port in.
Chapter 3 Port Functions 52 I/O Port Configuration and Functions ■ P27 Figure 3-3-6 Configuration and Functions of P27 Schmitt trigger input S D L Q Reset Write Port output data Reset signal input D.
Chapter 3 Port Functions 53 ■ P70 to P71 Figure 3-3-7 Configuration and Functions of P70 Read R D L Q Reset Write Read R D L Q Reset Write Read R D L Q Reset Write Read Read R D L Q Reset Write Pull.
Chapter 3 Port Functions 54 I/O Port Configuration and Functions ■ P60 to P67,P80 to P87 Figure 3-3-8 Configuration and Functions of P60 to P67 Figure 3-3-9 Configuration and Functions of P80 to P87.
55 4 Chapter 4 T imer Functions.
Chapter 4 Timer Functions 56 Overview 4-1 Overview The MN101C117 contains three 8-bit timers, one 16-bit timer, a watchdog timer, a time base timer, and circuits for remote control output and buzzer output.
Chapter 4 Timer Functions 57 Overview fs fs/4 fx TM2IO input MUX MUX MUX MUX Synchro- nization MUX MUX MUX MUX MUX MUX Synchro- nization MUX fosc f s/4 f s/16 TM3IO input TM2OC TM3CK0 TM3CK1 TM3CK2 TM.
Chapter 4 Timer Functions 58 Overview Figure 4-1-2 Timer 4 Block Diagram fosc fs/4 fs/16 TM4IO input MUX MUX Synchro- nization Synchro- nization MUX MUX MUX MUX IRQ0 IRQ1 IRQ2 TM4OCL TM4CK0 T4 I CT0 T.
Chapter 4 Timer Functions 59 Overview Figure 4-1-3 Timer 5/Time Base Block Diagram MUX MUX MUX MUX MUX MUX MUX f osc f s/4 f osc f x 250ms (32kHz) 0.977ms (8MHz) 1min (32kHz),250ms (8.
Chapter 4 Timer Functions 60 Overview Figure 4-1-4 Watchdog Timer, Buzzer Block Diagram 1/2 1/4 WDCTR DL YCTR MUX MUX 14 12 1/2 11 1/2 10 1/2 9 1/2 fs 1/2 1/2 R S R R 1/4 1/4 DLYS0 WDEN – – – .
Chapter 4 Timer Functions 61 Overview Figure 4-1-5 Remote Control Transmission Block Diagram Synchronization circuit MUX RMCTR Remote control output 1/3 duty 1/2 duty RMDTY0 – RMOEN – – – – .
Chapter 4 Timer Functions 62 4-2 8-bit T imer Operation (timers 2, 3) 4-2-1 Overview Functions for timers 2 and 3 are listed below. Table 4-2-1 Summary of 8-bit Timer Functions Timer 2 (8-bit) Timer 3.
Chapter 4 Timer Functions 63 8-bit Timer Operation (timers 2, 3) 4-2-2 Operation ■ Timer Operation (timers 2, 3) Settings for timer operation are listed below. Timer 2 is used as an example. (1) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2.
Chapter 4 Timer Functions 64 8-bit Timer Operation (timers 2, 3) If TM2IO input is selected as the clock source and the value of binary counter 2 is to be read during operation, select synchronized TM2IO input to avoid reading data that may be incomplete during count-up transitions.
Chapter 4 Timer Functions 65 The period of a signal output to the port is 1/2 of the period set in the TM2OC register. If port 1 is to be used as a pulse output pin, it is necessary to set the port 1 output direction control register (P1DIR) and the port 1 pull-up/pull-down resistor control register (P1PLU).
Chapter 4 Timer Functions 66 If the TM3PWM flag of the TM3MD register is set to "1" and timer 2 PWM output is selected, the PWM output of timer 2 will also be output from the TM3IO pin. If port 1 is to be used as a PWM output pin, the P1DIR and P1PLU registers must be set.
Figure 4-2-5 PWM Output Timing (when TM2OC register is X'00') Figure 4-2-6 PWM Output Timing (when TM2OC register is X'FF') Chapter 4 Timer Functions 67 8-bit Timer Operation (time.
Chapter 4 Timer Functions 68 The clock source for the serial interface has a frequency that is 1/2 of the overflow output of timer 3. For serial interface settings, refer to the chapter on serial functions. Disable the timer 2 interrupt. ■ Serial Transfer Clock Function(timer 3) Settings for the serial transfer clock function are listed below.
Chapter 4 Timer Functions 69 16-bit Timer Operation (timer 4) 4-3 16-bit T imer Operation (timer 4) 4-3-1 Overview Timer 4 is a 16-bit programmable counter that can be used as an event counter. A signal with a frequency of 1/2 of the timer 4 overflow signal can be output from the TM4IO pin.
Figure 4-3-1 Binary Counter 4 (TM4BC) Count Timing Chapter 4 Timer Functions 70 Clock TM4EN Binary counter 4 Write to registers TM4OCH, TM4OCL 05 04 06 07 08 09 00 If the TM4EN flag of the TM4MD register is changed simultaneously with other bits, the switching operation may cause binary counter 4 to be incremented.
Chapter 4 Timer Functions 71 16-bit Timer Operation (timer 4) If TM4IO input is selected as the clock source and the value of binary counter 4 is to be read during operation, select synchronized TM4IO input to avoid reading data that may be incomplete during count-up transitions.
Chapter 4 Timer Functions 72 ■ Timer Pulse Output Function Settings for the timer pulse output function are listed below. (1) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" so that the count operation of timer 4 is stopped.
■ Pulse Added Type PWM Output Function In the pulse added method, a 1-bit output is appended to the basic component of the 8-bit PWM output. Precise control is possible based on the number of PWM repetitions (256 times) to which this bit is appended.
Chapter 4 Timer Functions 74 16-bit Timer Operation (timer 4) [ ☞ 5-2-3 "Serial Interface Transfer Timing"] ■ Setting the Added Pulse Position The upper 8 bits of compare register 4 (TM4OCH) set the position of the added pulse.
Chapter 4 Timer Functions 75 16-bit Timer Operation (timer 4) ■ Capture Function Settings for the capture function are listed below. (1) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count operation of timer 4.
Chapter 4 Timer Functions 76 8-bit Timer Operation (timers 2, 3) 4-4 8-bit T imer Operation (timer 5) 4-4-1 Overview Timer 5 is an 8-bit timer that can have fosc, fs/4, fx, or time base output as its clock source. 4-4-2 Operation ■ Timer Operation Settings for timer operation are listed below.
4-5 T ime Base Operation 4-5-1 Overview The clock source for the time base timer can be set to fosc or fx. Also, the interrupt period for time base timer (TBIRQ) can be set to 1/2 7 , 1/2 8 , 1/2 9 , 1/2 10 , or 1/2 13 of the clock source. 4-5-2 Operation ■ Time Base Function Settings for the time base function are listed below.
Chapter 4 Timer Functions 78 4-6 W atchdog Timer Operation 4-6-1 Overview The watchdog timer is controlled by the watchdog control register (WDCTR) and can be used for runaway program detection. 4-6-2 Setup and Operation (1) Set the WDEN flag of the watchdog timer control register (WDCTR) to "1" to start the watchdog timer.
4-7 Remote Control Output Operation 4-7-1 Overview A remote control carrier pulse can be generated using the overflow of timer 3. Two duty ratios of 1/2 or 1/3 can be selected.
Chapter 4 Timer Functions 80 4-8 Buzzer Output 4-8-1 Buzzer Output Setup and Operation The square wave having a frequency 1/2 9 to 1/2 12 of the system clock can be output from the P06/BUZZER pin. (1) Set the BUZOE flag of the oscillation stabilization wait control register (DLYCTR) to "0" so that the buzzer output is turned off.
Chapter 4 Timer Functions 81 Overview 4-9 T imer Function Control Registers 4-9-1 Overview 19 registers control the timers. See table 4-9-1. Table 4-9-1 Timer Control Registers R/W: Readable and writa.
Chapter 4 Timer Functions 82 Timer Function Control Registers 4-9-2 Programmable Timer/Counters Timers 2~5 all contain a programmable 8-bit timer/counter (16-bit in timer 4). Programmable timer/counters consist of a compare register and a binary counter.
(5) Compare register 4 (TM4OCL) (lower 8 bits) Figure 4-9-5 Compare Register 4 (TM4OCL: X'03F74', R/W) (6) Compare register 4 (TM4OCH) (upper 8 bits) Figure 4-9-6 Compare Register 4 (TM4OCH:.
Chapter 4 Timer Functions 84 Timer Function Control Registers (9) Input capture register (TM4ICL) (lower 8 bits) Figure 4-9-9 Input Capture Register (TM4ICL: X'03F66', R) (10) Input capture .
Chapter 4 Timer Functions 85 Timer Function Control Registers 4-9-3 T imer Mode Registers Four readable and writable 6-byte timer mode registers. Control timers 2, 3, 4, 5, and the time base.
(2) Timer 3 mode register (TM3MD) Figure 4-9-14 Timer 3 Mode Register (TM3MD: X'03F83', R/W) Chapter 4 Timer Functions 86 Timer Function Control Registers TM3CK1 0 0 1 1 0 0 1 fosc fs/4 fs/1.
(3) Timer 4 mode register (TM4MD) Figure 4-9-15 Timer 4 Mode Register (TM4MD: X'03F84', R/W) Chapter 4 Timer Functions 87 Timer Function Control Registers 0 1 2 4 5 6 7 – 3 (at reset: -000.
(4) Timer 5 mode register (TM5MD) Figure 4-9-16 Timer 5 Mode Register (TM5MD: X'03F88', R/W) Chapter 4 Timer Functions 88 Timer Function Control Registers TM5CK3 X 0 TM5CK2 0 1 1 fs/4 (Use P.
4-9-4 T imer Control Registers (1) Watchdog timer control register (WDCTR) Figure 4-9-17 Watchdog Timer Control Register (WDCTR: X'03F02', R/W) (2) Oscillation stabilization wait control reg.
(3) Remote control carrier output control register (RMCTR) Figure 4-9-19 Remote Control Carrier Control Register (RMCTR: X'03F89', R/W) Chapter 4 Timer Functions 90 Timer Function Control Re.
91 5 Chapter 5 Serial Functions.
Chapter 5 Serial Functions 92 Overview 5-1 Overview The MN101C117 contains a serial interface that can operate in synchronous and simple UART modes. An overview of serial functions is shown below.
Chapter 5 Serial Functions 93 Overview Figure 5-1-1 Serial 0 Block Diagram fs/2 fs/4 fs/16 BC3 × 1/2 SBI0/RXD/P01 SBO0/TXD1/P00 SC0RXB SC0TRB SBT0/P02 SC0IRQ Shift register SWAP Start condition trans.
Chapter 5 Serial Functions 94 5-2 Synchronous Serial Interface 5-2-1 Overview A serial interface begins operation when data is written to the shift buffer. A bit counter is incremented at each 1-bit transfer. The transfer is complete when the counter overflows.
Chapter 5 Serial Functions 95 Synchronous Serial Interface When the clock source is an external clock (SBT0 pin input): • Set the SC0SBTM flag of the SC0MD3 register. • Set bit 2 of the P0DIR register to input mode. • Set the P0PLU register, if necessary.
Chapter 5 Serial Functions 96 Figure 5-2-1 Synchronous Serial Interface Transmission Timing (falling edge) Figure 5-2-2 Synchronous Serial Interface Transmission Timing (rising edge) Clock Start condi.
Chapter 5 Serial Functions 97 ■ Reception (1) Select the synchronous serial interface by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "0." (2 ) Select the transfer bit count with the SC0LNG2 to 0 flags of the serial interface 0 mode register 0 (SC0MD0).
Chapter 5 Serial Functions 98 Figure 5-2-3 Synchronous Serial Interface Reception Timing (reception at rising edge) Figure 5-2-4 Synchronous Serial Interface Reception Timing (reception at falling edg.
Chapter 5 Serial Functions 99 Synchronous Serial Interface 5-2-3 Serial Interface T ransfer Timing Serial interface 0 uses the SC0CE0 and SC0CE1 flags of serial interface 0 mode register 0 (SC0MD0), to control the edge at which transmission data is output and the edge at which reception data is input.
Chapter 5 Serial Functions 100 When serial interface 0 is used for simultaneous transmission and reception, set the SCnCE0 and SCnCE1 flags of the SCnMD0 register to "00" or "01", so that the reception data input edge is opposite in polarity to the transmit data output edge.
Chapter 5 Serial Functions 101 5-3 Half-duplex UART Serial Interface 5-3-1 Overview Setup and operation of UART transmission and reception are described below. 5-3-2 Setup and Operation ■ Transmission (1) Select UART by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "1.
Chapter 5 Serial Functions 102 (7) If parity is enabled by the SC0NPE flag of the SC0MD2 register, set the SC0PM1~0 flags of the SC0MD2 register to specify the added parity bit. (8) Set the SC0FM1 to 0 flags of the SC0MD2 register to specify the frame mode.
Chapter 5 Serial Functions 103 When the serial port is enabled and the SC0CE1 to 0 flags of the SC0MD0 register are toggled, the transfer bit count may change. The TXD pin goes to a high level after reception is complete. Serial interface 0 begins operation when the SC0SBOS or SC0SBIS flag is set to "1.
Chapter 5 Serial Functions 104 Figure 5-3-2 UART Reception Timing Half-duplex UART Serial Interface RXD RXD Parity enabled Parity disabled Parity bit Stop bit Stop bit Stop bit Stop bit SC0BSY Parity .
5-3-3 How to Use the Baud Rate Timer Refer to the following when using the baud rate timer to set the UART transfer speed. (1) Specifying the timer clock source The clock source is specified by the TM3CKS3 to 1 flags of the timer 3 mode register (TM3MD).
Chapter 5 Serial Functions 106 Serial Interface Control Registers 5-4 Serial Interface Control Registers 5-4-1 Overview 7 registers control the serial interface.
Chapter 5 Serial Functions 107 Serial Interface Control Registers 5-4-2 T ransmit/Receive Shift Registers, Receive Data Buffer (1) Serial interface 0 transmit/receive shift register (SC0TRB) This 8-bit, writable register shifts the transmission data and the reception data.
Chapter 5 Serial Functions 108 5-4-3 Serial Interface Mode Registers (1) Serial interface 0 mode register (SC0MD0) Figure 5-4-3 Serial Interface 0 Mode Register 0 (SC0MD0: X'03F50', R/W) Ser.
Chapter 5 Serial Functions 109 Serial Interface Control Registers (2) Serial interface 0 mode register 1 (SC0MD1) Figure 5-4-4 Serial Interface 0 Mode Register 1 (SC0MD1: X'03F51', R/W) 0 1 .
Chapter 5 Serial Functions 110 Serial Interface Control Registers (3) Serial interface 0 mode register 2 (SC0MD2) Figure 5-4-5 Serial Interface 0 Mode Register 2 (SC0MD2: X'03F52', R/W) 0 1 .
Chapter 5 Serial Functions 111 Serial Interface Control Registers (4) Serial interface 0 mode register 3 (SC0MD3) Figure 5-4-6 Serial Interface 0 Mode Register 3 (SC0MD3: X'03F53', R/W) SBI0.
Chapter 5 Serial Functions 112 5-4-4 Serial Interface Control Register (1) Serial interface 0 control register (SC0CTR) Figure 5-4-7 Serial Interface 0 Control Register (SC0CTR: X'03F54', R).
113 6 Chapter 6 A/D Conversion Functions.
Chapter 6 A/D Conversion Functions 114 Overview 6-1 Overview The MN101C117 has an internal A/D converter with 10-bit resolution. A sample-and-hold circuit is contained on-chip and software can switch the analog input between channels 0 to 7 (AN0 to AN7).
Chapter 6 A/D Conversion Functions 115 A/D Conversion 6-2 A/D Conversion The procedures for operating the A/D conversion circuit are listed below. (1) Set the ANCHS2 to ANCHS0 flags of A/D control register 0 (ANCTR0) to specify one of pins AN7 to AN0 (PA7 to PA0) as the analog input.
Chapter 6 A/D Conversion Functions 116 A/D Converter Control Registers The following items must be implemented to maintain the accuracy of the A/D converter: 1. Use a maximum input pin impedance, R, of 500k Ω ∗ 1 with an external capacitor, C, that is minimum 1,000pF and maximum 1µF ∗ 1 .
117 Chapter 6 A/D Conversion Functions A/D Converter Control Registers 6-3 A/D Converter Control Registers 6-3-1 Overview Four registers control the A/D converter.
Chapter 6 A/D Conversion Functions 118 A/D Converter Control Registers 6-3-2 A/D Control Register (ANCTR) This readable and writable 8-bit register controls the operation of the A/D converter. (1) A/D control register 0 (ANCTR0) ∗ 1: Specify that where the period of the A/D conversion clock is greater than 800ns.
Chapter 6 A/D Conversion Functions 119 A/D Converter Control Registers (2) A/D conversion control register 1 (ANCTR1) Figure 6-3-2 A/D Control Register 1 (ANCTR1: X'03F91', R/W) A/D conversi.
Chapter 6 A/D Conversion Functions 120 A/D Converter Control Registers 6-3-3 A/D Buffers (ANBUF) These read-only registers store the A/D conversion results. (1) A/D buffer 0 (ANBUF0) This register stores the lower 2 bits of the A/D conversion results.
121 7 Chapter 7 AC Zero-Cross Circuit/Noise Filter.
Chapter 7 AC Zero-Cross Circuit/Noise Filter 122 Overview 7-1 Overview The P21/SENS pin is the input pin for the AC zero-cross detection circuit. The AC zero-cross detection circuit outputs a high level when the input is at an intermediate level, and a low level at all other times.
Chapter 7 AC Zero-Cross Circuit/Noise Filter 123 AC Zero-Cross Circuit Operation 7-2 AC Zero-Cross Circuit Operation 7-2-1 Setup and Operation Settings for zero-cross circuit operation are listed below. (1) Set the REDG1 flag of the IRQ1ICR register to select the valid edge for IRQ1.
Chapter 7 AC Zero-Cross Circuit/Noise Filter 124 7-3 Noise Filter 7-3-1 Overview External interrupt pins IRQ0 and IRQ1 contain noise filtering circuit.
Chapter 7 AC Zero-Cross Circuit/Noise Filter 125 Noise Filter 7-3-2 Example Input and Output W aveforms for Noise Filter When the noise filter is used, the waveform input to the IRQ0 pin is sampled based on the clock specified by the NF0CKS0 and NF0CKS1 flags of the noise filter control register (NFCTR).
Chapter 7 AC Zero-Cross Circuit/Noise Filter 126 [ ☞ 2-4-3 "Interrupt Control Registers ■ External Interrupt Control Registers"] [ ☞ 3-2-2 "I/O Port Control Registers ■ Pin Control Registers"] 7-4 AC Zero-Cross Control Register 7-4-1 Overview Four registers control the AC zero-cross circuit.
Chapter 7 AC Zero-Cross Circuit/Noise Filter 127 AC Zero-Cross Control Register 7-4-2 Noise Filter Control Register (NFCTR) This 6-bit readable and writable register controls the noise filter.
Chapter 7 AC Zero-Cross Circuit/Noise Filter 128.
129 8 Appendices.
Chapter 8 Appendices 130 EPROM Versions 8-1 EPROM V ersions 8-1-1 Overview EPROM version is microcomputer which was replaced with the mask ROM of the MN101C11 with an electronically programmable 16-KB EPROM. Because the MN101CP117**(**=DP,BF,HP) is sealed in plastic, once data is written to the internal PROM it cannot be erased.
8-1-2 Cautions on Use EPROM Versions differs from the MN101C11* in some of its electrical characteristics. The user should be aware of these differences. (1) To prevent data from being erased by ultraviolet light after a program is written, affix seals impermeable to UV rays to the glass sections at the top and side sections of the CPU.
Chapter 8 Appendices 132 EPROM Versions 8-1-3 Erasing Written Data in W indowed Packages In an internal EPROM with windowed packaging, data is erased("0" → "1") when UV light at 253.7nm permeates the window to irradiate the chip.
Chapter 8 Appendices 133 EPROM Versions 8-1-4 Characteristics of EPROM V ersion The MN101C11*(mask ROM version) and the Microcomputer with internal EPROM version have the following differences. Table 8-1-1 Difference between MN101C*(Mask ROM version) and Internal EPROM version) There are no other functional differences.
8-1-5 W riting to Microcomputer with Internal EPROM ■ Fit in the writing adapter and position the No.1 pin. Figure 8-1-1 Mount on the writing adapter and position of No.1 pin. Chapter 8 Appendices 134 EPROM Versions 1 2 39 40 No.1 pin must be matched to this position.
Chapter 8 Appendices 135 EPROM Versions ■ ROM writer Selection The device names should be set up as listed below. Table 8-1-2 Device selection The above settings are based on the standard samples. When you use the other equipment than the ones listed, contact the nearest semiconductor design center.
Chapter 8 Appendices 136 EPROM Versions 8-1-6 Cautions on Operating the ROM Writer ■ Cautions on operating the ROM writer (1)The Vpp programming voltage for the EPROM versions is 12.5V. Programming with a 21-volt ROM writer can lead to damage. The ROM writer specifications must match those for standard 1-megabit EPROMS:Vpp=12.
Chapter 8 Appendices 137 EPROM Versions 8-1-7 Option Bit The MN101C117 and the MN101CP117 control the oscillation mode after resetting as well as the runaway-detection watch dog timer, using bit 2 to 0 of the last address (X'7FFF) of the built-in ROM.
Chapter 8 Appendices 138 EPROM Versions 8-1-8 W riting Adapter Connection Package Code SDIP042-P-0600 Fig. 8-1-3 MN1-1CP117-DP(DC)EPROM Writing Adapter Connections VSS VSS NOE VSS A14 V.
Chapter 8 Appendices 139 EPROM Versions Package code: QFP044-P-1010 Pin pitch: 0.8mm Fig. 8-1-4 MN101CP117-BL(BC)EPROM Writing Adapter Connections MN101CP117 ４４- ＱＦＰ D3 D2 D1 D0.
Chapter 8 Appendices 140 EPROM Versions Package code: QFH048-P-0707 Pin pitch: 0.5mm Fig. 8-1-5 MN101CP117-HP EPROM Writing Adapter connections P83 P82 P81 P80 NC PA.
Chapter 10 Appendices 141 Instruction Set 8-2 Instruction Set MN101C00 SERIES INSTRUCTION SET Group Data move instructions Mnemonic Operation Affected Flag VF NF CF ZF Code Size Cycle Re- peat Machine.
Chapter 10 Appendices 142 Instruction Set MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes Page 1 23456789 1 0 1 1 Expand .
Chapter 10 Appendices 143 Instruction Set MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes Page 1 23456789 1 0 1 1 Expand .
Chapter 10 Appendices 144 Instruction Set MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes Page 1 23456789 1 0 1 1 Expand .
Chapter 10 Appendices 145 Instruction Set MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes Page 1 23456789 1 0 1 1 Expand TBNZ (abs8)bp,label if(mem8(abs8)bp=1),PC+8+d11(label)+H → PC 00 8 126 127 127 129 129 130 130 131 6/7 0001 1bp.
Chapter 10 Appendices 146 Instruction Set MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Flag VF NF CF ZF Code Size Cycle Re- peat Machine Code Notes Page 1 23456789 1 0 1 1 135 .
Chapter 10 Appendices 147 Instruction Map 8-3 Instruction Map 0 0 NOP RTS MOV #8,(io8) RTI CMP #8,(abs8)/(abs12) POP An ADD #8,Dm MOVW #8,DWm MOVW #8,Am 1 JSR d12(label) JSR d16(label) MOV #8,(abs8)/(.
Chapter 10 Appendices 148 Instruction Map 0 0 TBZ (abs8)bp,d7 TBZ (abs8)bp,d11 1 TBNZ (abs8)bp,d7 TBNZ (abs8)bp,d11 2 CMP Dn,Dm 3 ADD Dn,Dm 4 TBZ (io8)bp,d7 TBZ (io8)bp,d11 5 TBNZ (io8)bp,d7 TBNZ .
Chapter 10 Appendices 149 Summary of Special Function Registers Address X’ 3F00’ X’ 3F01’ X’ 3F02’ X’ 3F03’ X’ 3F10’ X’ 3F11’ X’ 3F12’ X’ 3F13’ .
Chapter 10 Appendices 150 Summary of Special Function Registers Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X’ 3F31’ X’ 3F35’ X’ 3F33’ X’ 3F34’ X’ 3F.
Chapter 10 Appendices 151 Summary of Special Function Registers Bit Symbol Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X’ 3F52’ X’ 3F50’ X’ 3F51’ X’ 3F46’.
Chapter 10 Appendices 152 Summary of Special Function Registers Bit Symbol Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Binary counter 5.
Chapter 10 Appendices 153 Summary of Special Function Registers Bit Symbol Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address X’ 3FF2’ X’ 3FF1’ X’ 3FF0’ X’ 3FEF’.
Chapter 10 Appendices 154 Summary of Special Function Registers Bit Symbol Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address X’ 3FF2’ X’ 3FF1’ X’ 3FF0’ X’ 3FEF’.
MN101C115 / 117 LSI User's Manual August,1999 1st Edition 1st Printing Issued by Matsushita Electric Industrial Co., Ltd. Matsushita Electronics Corporation © Matsushita Electric Industrial Co.
Semiconductor Company Matsushita Electronics Corporation Nagaokakyo, Kyoto, 617-8520 Japan Tel: (075) 951-8151 http://www.mec.panasonic.co.jp ■ U.S.A.
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