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MICR OCOMPUTER MN102H MN102H75K/F75K/85K/F85K LSI User’ s Manual Pub .No .22385-011E.
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PanaXSerie s is a t rademark o f Matsushita Electric Industr ial Co., Ltd. The other corporat ion names, logotyp e and product names written in this book are trademark s or registe red trademarks of their corresp ondin g corp oratio ns.
Contents MN102H75 K /F75K LSI Use r Manual Panasonic Semiconductor Development Company 3 Panas oni c Contents About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Using This Manual.
Contents Panasonic Semicond uctor Development C ompany MN102H75 K/F75K LSI Us er Manual 4 Panas oni c 4.5.1 Setting Up an Ev ent Counter Using T imer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.5.2 Setting Up an Interv al T imer Using T imers 1 and 2 .
Contents MN102H75 K /F75K LSI Use r Manual Panasonic Semiconductor Development Company 5 Panas oni c 6.4.2 Single Channel/Single Co n version T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.4.3 Multiple Channel/Single Con version T iming .
Contents Panasonic Semicond uctor Development C ompany MN102H75 K/F75K LSI Us er Manual 6 Panas oni c 7.13.3 Controlling Shutter ing Ef fects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 7.
Contents MN102H75 K /F75K LSI Use r Manual Panasonic Semiconductor Development Company 7 Panas oni c 11 I/O P or t s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1 11.
Contents Panasonic Semicond uctor Development C ompany MN102H75 K/F75K LSI Us er Manual 8 Panas oni c B.4.2 Circuit Requireme nts for the T ar get Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 B.4.3 Microcontroller Hardw are Used in Onboard Serial Programming .
List of Table s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 9 Panas oni c List of T ables 1-1 General Specif ications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Table s Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 10 Panas oni c 8-5 IR Remote Signal Recei ver Re gisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figur es MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 11 Panas oni c List of Figures 1-1 Con vention al vs. MN102H Series Cod e As signments . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of F igures Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 12 Panas oni c 4-20 One-Shot Pulse Outpu t T iming (16-Bit T imers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figur es MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 13 Panas oni c 5-12 Serial Interface C lock T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of F igures Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 14 Panas oni c 7-31 Shuttered Area Setup Exam ples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figur es MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 15 Panas oni c 11-16 P30/CLH and P33/C LL (Port 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About This Manual Using This Manual Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 16 Panas oni c Abou t This Manual This manual is i ntended fo r assembly-lan guage programming engineers. It describ es the int ernal conf iguration and hardwar e functions of the MN10 2H75K and MN102H85 K microco ntrollers .
About This Manual Related Documents MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 17 Panas oni c Related Documents ■ MN102H S eries LSI Us er Manual (Describes the core hardw are.) ■ MN102H S eries Instruct ion Manual (Describes the instruction set.
General Description MN102H Seri es Over view Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 18 Panasonic 1 General Description 1.1 MN102H S eries Over view The 16-bit MN102H series is the hi gh-speed linear addr essing versio n of the MN10200 series.
General Description MN102H Se ries Feature s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 19 Panasonic ■ Single-byte basic instr uction lengt h The MN102.
General Description MN102H Series Feature s Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 20 Panasonic ■ Fast interrupt response MN102H series de vices can stop execu ting instructions, ev en those with long e xecution c ycles, to service interrupts immediately .
General Description MN1 02H Seri es Desc ript ion MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 21 Panasonic ■ Outstanding po wer savings The MN102H ser i.
General Description MN102 H Serie s Descrip tion Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 22 Panasonic NX: Exte nsion negativ e flag If the most significant bit of the result of an operation has the value 1, this flag is set; if that bit is 0, th is flag is reset.
General Description MN1 02H Seri es Desc ript ion MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 23 Panasonic ■ Internal regis ters, memo ry , and special funct ion registers Note: 1. This allo cation is a represen tative example.
General Description MN102 H Serie s Descrip tion Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 24 Panasonic ■ Addre ss spa ce The memory in the MN102H series is conf igured as linear address space.
General Description MN1 02H Seri es Desc ript ion MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 25 Panasonic ■ Interrupt contr oller An interrupt con t roller e xternal to the core co ntrols all nonmaskable and maskable interrupts e xcept reset.
General Description General Specifications Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 26 Panasonic 1.4 Gener al Spec ifi cations T able 1-1 G eneral Spe ci.
General Description General Specifications MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 27 Panasonic Timer/counters F our 8-bit timers: ♦ Cascading funct.
General Description Block Diagram Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 28 Panasonic 1.5 Block Diagram Figure 1-8 F unctional Bloc k Diag r am A1 A0 A.
General Description Block Diagram MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 29 Panasonic T able 1-2 Block Diagram Explanation Bloc k Description Clock generator An oscillation circuit connected to a n ex ternal cr ystal supplies the clock to all blocks within the CPU .
General Description Pin Descriptions Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 30 Panasonic 1.6 Pin Descriptions 1.6.1 MN102 H85K Pin Description Notes: 1. Pins marked with an as te risk (*) are N-ch annel, open -drai n pins.
General Description Pin D escrip tions MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 31 Panasonic 1.6.2 MN102 H75K Pin Description Notes: 1. Pins marked with an aste risk (*) are N-chann el , open-drain pins.
General Description Pin Descriptions Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 32 Panasonic T able 1-3 Pin Functions Bloc k Pin Name I/O Pin Count Descrip.
General Description Pin D escrip tions MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 33 Panasonic I/O ports MN102H75K/HF75K: total 66 pins MN102H85K/HF85K: .
General Description Pin Descriptions Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 34 Panasonic ■ Consideration s for po wer suppl y , cloc k, and reset p ins ■ Connection th e PLL circu it The MN102H75K/85 K contains an internal PLL circuit.
General Description Bus Interface MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 35 Panasonic 1.7 Bus Int erface 1.7.1 Descrip tion The b us interface op erates in ex ternal extension mode. Figure 1-15 prov ides the memory space fo r the MCU in this mode.
General Description Bus Interface Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 36 Panasonic 1.7.2 Bus Interface Control Registe rs The ex t ernal memory wa i t re gister (EXWMD) and memory mode register 1 (MEMMD1) control the bus interf ace.
Inter r upts Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 37 Panasonic 2 Inte rrupts 2.1 Des cription The most important f actor in real-time con trol is an MCU’ s speed in servicing interrupt s.
Interrupts Description Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 38 Panasonic Figure 2-2 In terrupt V ector Gro up and Class Assignme nts Group Interrupt .
Inter r upts Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 39 Panasonic Figure 2-3 Inte rrupt Servicing Time T able 2-2 Handl er Prepr ocessing .
Interrupts Interrupt Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 40 Panasonic 2.2 Interrupt Setup Exampl es 2.
Inter r upts Interrupt Setup Exa mples MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 41 Panasonic 3. Enable interrup ts b y writing a 1 to the interrupt enable flag (IE) in the PSW and setting th e interrupt masking level (IM[2:0]) to 7 (b’111’).
Interrupts Interrupt Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 42 Panasonic 2.2.2 Setting U p a W atchdog T imer Interrup t The watchd og time r int err upt is provided fo r detec ting a nd ha ndling racing.
Inter r upts Interrupt Setup Exa mples MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 43 Panasonic The main program normally gen- erates and branches to the inter- rupt star t ad dress. If the CPU accepts an interrupt, the program br anches to address x’080008’.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 44 Panasonic 2.3 Interrupt Contr ol Registers A control re gister is as signed to each interr upt vector group.
Inter r upts Interrupt Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 45 Panasonic XnICL (System Interrupt) IR: Interrupt requ est flag 0: .
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 46 Panasonic T able 2-4 Interrupt Contr ol Registers Register Address R/W.
Inter r upts Interrupt Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 47 Panasonic ADM3ICL ADM3ICH ADM2ICL ADM2ICH ADM1ICL ADM1ICH ADM0ICL .
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 48 Panasonic IA GR: Accep ted Inte rrupt Group Numb er Re giste r x’00 FC0E ’ IA GR returns the group number of an accepted interru pt, indicated in the 6-bit GN f ield.
Inter r upts Interrupt Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 49 Panasonic PIICR: Undefin ed Instruction Int err upt Cont rol Register x’00 FC44 ’ PIICR is an 8-bit access re gister .
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 50 Panasonic IQ0ICH: External Interrupt 0 Inte rr upt Control Regis ter (High) x’00 FC49 ’ IQ0ICH sets the priority level for and enables external interrupt 0.
Inter r upts Interrupt Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 51 Panasonic IQ2ICL: Ex ter nal Interrupt 2 Interrupt Control Register (Lo w) x’ 00FC 50’ IQ2ICL requ ests and v erifies inter rupt requests fo r external interrupt 2.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 52 Panasonic IQ3ICH: External Interrupt 3 Inte rr upt Control Regis ter (High) x’00 FC53 ’ IQ3ICH enables ex ternal interrupt 3.
Inter r upts Interrupt Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 53 Panasonic IQ5ICL: Ex ter nal Interrupt 5 Interrupt Control Register (Lo w) x’00FC5A’ IQ5ICL requ ests and v erifies inter rupt requests fo r external interrupt 5.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 54 Panasonic TM4CBI CH: Timer 4 Compar e/Capture B Interr upt C ontrol Regist er (High) x’00FC61’ TM4CBICH sets the priority le vel for and enables timer 4 compare/capture B interrupts.
Inter r upts Interrupt Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 55 Panasonic TM4UDICL: Timer 4 Underfl ow I nterrupt Control Regis ter (Low) x ’00 FC64 ’ TM4UDICL detects and requests timer 4 und erflow interrupts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 56 Panasonic VBIICH: VBI (1) Inte rr upt Control Re gister (High ) x’00 FC67 ’ VBIICH enables VBI (1) interru pts. It is an 8-bit access re gi ster .
Inter r upts Interrupt Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 57 Panasonic TM5CAI CL: Ti mer 5 Compare/ Capture A Interr upt Control Register ( Low) x’ 00FC6A’ TM5CAICL detects and requ ests timer 5 compare/capture interr upts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 58 Panasonic TM5UDICH: Timer 5 Underflo w Interrupt Control Reg i s ter (High) x’00FC6D’ TM5UDICH enables timer 5 underflo w interrupt s.
Inter r upts Interrupt Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 59 Panasonic TM2UDICL: Timer 2 Underfl ow I nterrupt Control Regis ter (Low) x ’00 FC70 ’ TM2UDICL re gister detects and request s timer 2 underflo w interrupts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 60 Panasonic TM1UDICH: Timer 1 Underflo w Interrupt Control Reg i s ter (High) x ’00F C73 ’ TM1UDICH enables timer 1 underflo w interrupt s.
Inter r upts Interrupt Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 61 Panasonic RMCICL: Remo te Sig nal Rece ive Inte rr upt C ontr ol Re gis ter ( Low) x’00 FC76 ’ RMCICL detects and requests remote signal recei ve interrupts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 62 Panasonic ADM3ICH: Address 3 Matc h Interrupt Contro l Register (High) x’00 FC79 ’ ADM3ICH sets the prio rit y level for and enables address match 3 in ter- rupts.
Inter r upts Interrupt Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 63 Panasonic ADM1ICL: Address 1 Match Inte rr upt Cont rol Regi ster (Lo w) x’00FC7C’ ADM1ICL detects and requests address match 1 interrupts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 64 Panasonic ADM0ICH: Address 0 Matc h Interrupt Contro l Register (High) x ’00F C7F’ ADM0ICH enables address match 0 interru pts.
Inter r upts Interrupt Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 65 Panasonic SCT0ICL: Serial 0 T ransmissi on End Interrupt Contro l Regis ter (Lo w) x’00 FC82 ’ SCT0ICL detects and requests serial 0 transmission end interrupts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 66 Panasonic SCR0ICH: Serial 0 Reception End Interrupt Control Re gister (High) x ’00F C85’ SCR0ICH enables serial 0 reception end interrupts.
Inter r upts Interrupt Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 67 Panasonic VBIVWICL: VBIVSYNC (2) In terr upt Control Regis ter (Low) x’00FC8A’ VBIVWICL detects and requests VB IVSYNC (2) interrupts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 68 Panasonic TM3UDICH: Timer 3 Underflo w Interrupt Control Reg i s ter (High) x’00FC8D’ TM3UDICH enables timer 3 underflo w interrupt s.
Inter r upts Interrupt Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 69 Panasonic OSDCICL: OSD (T e xt) Interrupt Con trol Register (Lo w) x’00 FC92 ’ OSDCICL detects and requests OSD (tex t ) interrupts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 70 Panasonic SCT1ICH: Serial 1 T ransmissio n End Interrupt Control Regist er (High) x’00 FC99 ’ SCT1ICH sets the prio rity le vel for and enab les s erial 1 transmiss ion end interrupts.
Inter r upts Interrupt Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 71 Panasonic I2CICL: I 2 C Inter ru pt Co ntr ol Re gist e r (Low ) x’00FC9C’ I2CICL detects and requests I 2 C interru pts.
Low-Power Modes CPU Mode s Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 72 Panasonic 3 Low-P ower Modes The MN102H75K/85 K provides tw o ways to red uce powe.
Low-P owe r Mod es CPU Modes MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 73 Panasonic 3.1.2 Exiting from S LO W Mod e to NORMAL Mod e The MN102H75K/85K rec ov ers from pow er up and reset i n SLOW mode. F or nor mal opera- tion, the progr am must s witch the MCU from SLO W to NOR- MAL mode.
Low-Power Modes CPU Mode s Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 74 Panasonic 3.1.3 Notes on In v o king and Exitin g ST OP and HAL T Modes ■ When in v oking ST OP and HAL T modes.
Low-P owe r Mod es Turning I ndividual Func tions On and Off MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 75 Panasonic 3.2 T urning Individual Functions On and Off Y ou cannot set the PLL function control bit during NORMAL mode .
Low-Power Modes CPU Cont rol Regist er Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 76 Panasonic 3.3 CPU Control Register CPUM: CPU Mode Control Registe r x’00 FC00 ’ This r egister cont rols the in vo king of all of the CPU mod es.
Time rs 8-Bit Timer Desc ription MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 77 Panasonic 4T i m e r s 4.
Timers 8-Bit Timer Fe atures Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 78 Panasonic 4.2 8-Bit Timer Features T able 4-1 8-Bit Timer Functions an d Feature.
Time rs 8-Bit Timer Block Diagrams MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 79 Panasonic 4.3 8-Bit Ti mer Block Diagrams Figure 4-3 Ti mer 0 Block Dia .
Timers 8-Bit Timer Block Diagrams Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 80 Panasonic Figure 4-5 Ti mer 2 Block Dia gram Figure 4-6 Ti mer 3 Block Dia .
Time rs 8-Bit Timer Timing MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 81 Panasonic 4.4 8-Bit Timer Timing Figure 4-7 Ev ent Timer Input Tim ing (8-Bit Ti.
Timers 8-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 82 Panasonic 4.5 8-Bit Timer Setup Examples 4.5.1 Setting Up an Event Counte r Using T imer 0 In this example, timer 0 generates an underflow interrupt on the fourth rising edge of the TM0 IO signal.
Time rs 8-Bit Timer Setup Examples MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 83 Panasonic TM0UDICL (e xample) x’00 FC74 ’ TM0UDICH (e xample) x’00 FC75 ’ 4. Set the divide-by ratio for timer 0. Since the ti mer will count 4 TM0IO cycles, write x’03’ to the timer 0 base register (T M0BR).
Timers 8-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 84 Panasonic 4.5.2 Setting Up an Interva l T imer Usin g T ime rs 1 and 2 In this ex ample, timers 1 and 2 are cascaded to di vide B OSC /4 by 60,00 0 and generate an underflo w interrupt .
Time rs 8-Bit Timer Setup Examples MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 85 Panasonic TM2UDICH (e xample) x’00 FC71 ’ TM2UDICL (e xample) x’00 FC70 ’ TM1UDICH (e xample) x’00 FC73 ’ TM1UDICL (e xample) x’00 FC72 ’ 3.
Timers 8-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 86 Panasonic TM2MD (e xample) x’00 FE22 ’ In the bank and l inear address- ing v ersions of the MN102 series, it was necessar y to set TM0EN and TM0LD to 0 between steps 4 and 5, to ensure stable oper ation.
Time rs 8-Bit Timer Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 87 Panasonic 4.6 8-Bit Timer Control Register s T able 4- 2 sho ws the re gisters used to control the 8-b it timers.
Timers 16-Bit Timer Description Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 88 Panasonic 4.7 16-Bit Timer Description The MN102H75K/85 K contains two 1 6-bit up/d own timers, timers 5 and 6.
Time rs 16-Bit Timer Fe atures MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 89 Panasonic 4.8 16-Bit Timer Features T able 4-3 16-Bit Timer Functio ns and F.
Timers 16-Bit Timer Block Diagrams Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 90 Panasonic 4.9 16-Bit Timer Bloc k Diagrams 4.
Time rs 16- Bit Time r Timing MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 91 Panasonic Figure 4-18 Si ngle-Ph ase PWM Output Timing with Data Chang e (16-.
Timers 16-Bit Timer Timing Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 92 Panasonic Figure 4- 21 Exte rnal Cou nt Direction Cont r ol Timin g (16-Bit Timers.
Time rs 16- Bit Time r Timing MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 93 Panasonic Figure 4- 24 T wo-Phase Capture I nput T iming (16-B it Ti mers) Fi.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 94 Panasonic 4.11 16-Bit Timer Setup Examples 4.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 95 Panasonic TM4CA (e xample) x’00 FE84 ’ 3. Set the phase dif ference for timer 4. For a 2- cycle phase differen ce, write x’0001’ to timer 4 compare/capture re gi ster B (TM4CB).
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 96 Panasonic 4.11.2 Se tting Up a Sing le-Phase PWM O u tput Sig nal Using Ti me r 4 In this example, timer 4 is used to divide B OSC by 5 a nd generate a f iv e-cycle, single-phase PWM signal.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 97 Panasonic P2DIR (e xample) x’00FFE 2’ ■ T o set up time r 4: Use the MO V instruction for t his setup and only use 16-bit write operations .
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 98 Panasonic 6. Set the TM4NLD b it o f the TM4MD register to 1 and the TM4EN bit to 0 . This enables TM4BC and the S-R flip-flop.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 99 Panasonic Figur e 4-30 be lo w sho ws the ou tput w av eforms for TM4O A. Both A and B interrupts can occur, b ut B interrupts can only occur if the TM4CB setting is from 0 to less than TM4C A .
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 100 Panasonic T wo potential types of error s are inheren t with PWM output. First, becau se of the circuit conf iguration, direction errors can occur .
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 101 Panasonic 4.11.3 Se tting Up a T wo-Ph ase PWM Output Sign al Using Ti me r 4 In this e xample, timer 4 i s used to di vide timer 0 underf low by 5 and generate a fi ve- cycle, tw o-pha se PWM signal .
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 102 Panasonic P2DIR (e xample) x’00FFE 2’ ■ T o set up time r 0: 1. Disable timer 0 counting i n the timer 0 mode re gister (TM0MD).
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 103 Panasonic ■ T o set up time r 4: Use the MO V instruction for t his setup and only use 16-bit write operations . This step stops the TM4BC count and clears both TM 4BC and the S-R flip-flop to 0.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 104 Panasonic 6. Set the TM4NLD b it o f the TM4MD register to 1 and the TM4EN bit to 0 . This enables TM4BC and the S-R flip-flop.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 105 Panasonic W ith PWM output, the duty cycle can change dynam ically , which can cause the PWM wa veform t o skip a pu lse (see the single b uffer ing section of f igure 4-34 belo w).
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 106 Panasonic 4.11.4 Se tting Up a Sing le-Phase Cap ture Input Usin g T imer 4 In this example, timer 4 is used to divide B OSC /4 by 6 5,536 and measure ho w long the TM4IA inp ut signal stays high .
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 107 Panasonic change an y other operat ing modes during this st ep. When TM4MD[1:0] = b’10’ (dur- ing capture), TM4CA and TM4CB become read-only reg is- ters.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 108 Panasonic 4.11.5 Se tting Up a T wo-Ph ase Capture Inp ut Using Tim er 4 .
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 109 Panasonic TM0BR (e xample) x’00 FE10 ’ Do not change the cloc k source once you select it. Sel ecting the clock source while you set up the count operati on control will corrupt the value in the binar y counter .
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 110 Panasonic ■ T o service the inte rr upts and calculate the signal w idth: 1. Run the interrup t service routine. The routine mu st determine the int errupt group, then clear th e interrupt request flag.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 111 Panasonic 4.11.6 Se tting Up a 4x T wo-Phase Encod er Input Using T imer 5 In this ex ample, timer 5 inputs a 4 x two-phase en coded signal that makes it count up and do wn.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 112 Panasonic ■ T o set up time r 5: Use the MO V instruction for t his setup and only use 16-bit write operations . This step stops the TM5BC count and clears both TM 5BC and the S-R flip-flop to 0.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 113 Panasonic ■ T o service the inte rr upts: Run the interrupt s ervice routine. The routi ne must determine the in terrupt group, then clear the interru pt request flag.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 114 Panasonic 4.11.7 Setting Up a 1x T w o-Phase Encoder Input U s i n g Ti m e r 5 In this ex ample, timer 5 inputs a 1 x two-phase en coded signal that makes it count up and do wn.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 115 Panasonic ■ T o set up time r 5: Use the MO V instruction for t his setup and only use 16-bit write operations . This step stops the TM5BC count and clears both TM 5BC and the S-R flip-flop to 0.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 116 Panasonic ■ T o service the inte rr upts: Run the interrupt s ervice routine. The routi ne must determine the in terrupt group, then clear the interru pt request flag.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 117 Panasonic 4.11.8 Se tting Up a On e-Shot Pulse Ou tput Using Timer 5 In this e xample, timer 5 o u tputs a one-shot puls e.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 118 Panasonic ■ T o set up time r 5: Use the MO V instruction for t his setup and only use 16-bit write operations . This step stops the TM5BC count and clears both TM 5BC and the S-R flip-flop to 0.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 119 Panasonic T imer 5 can output a one-shot pul se. T imer 5 do es not o per ate in STOP m od e, when B OSC is o ff. If you use an e xternal clock, it mus t be synchro nized to B OSC .
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 120 Panasonic 4.11.9 Se tting Up an Extern al Coun t Direction Contr oller Using T im er 5 In this ex ample, timer 5 counts B OSC /4 an d the TM5IA pin con trols the count direction (up o r down).
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 121 Panasonic ■ T o set up time r 5: Use the MO V instruction for t his setup and only use 16-bit write operations . This step stops the TM5BC count and clears both TM 5BC and the S-R flip-flop to 0.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 122 Panasonic ■ T o service the inte rr upts: Run the interrupt s ervice routine. The routi ne must determine the in terrupt group, then clear the interru pt request flag.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 123 Panasonic 4.11.10 Setting Up External Reset Control U sing T imer 5 In this example, timer 5 is reset by an e xternal signal while countin g up.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 124 Panasonic TM5CA (e xample) x’00 FE94 ’ 3. Set the TM5NLD b it o f the TM5MD register to 1 and the TM5EN bit to 0 . This enables TM5BC and the S-R flip-flop.
Time rs 16-Bit Timer Con tr o l Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 125 Panasonic 4.12 16-Bi t Time r Control Registers T able 4-6 sho ws the re gisters used to control th e 16-bit timers.
Timers 16-Bit Timer Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 126 Panasonic TM4MD/TM5M D: Time r n Mode Register x’00F E80’/x’00FE.
Serial Interfaces Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 127 Panasonic 5 Serial Interfaces 5.1 Des cription The MN102H75K/85 K contains two g eneral-pur pose serial interfaces with syn- chronous serial, U AR T , and I 2 C modes .
Serial Interfaces Connecting the Serial Interfaces Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 128 Panasonic 5.3 Connecting the Serial Interfaces Figures 5-2, 5-3, and 5 -4 illustrate six different methods of connectin g the serial interface.
Serial Interfaces UART Mode Baud Ra tes MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 129 Panasonic 5.4 U AR T Mode Baud Rates In U AR T mode, the serial inter face transfer clock is set to 16 times the baud r ate clock.
Serial Interfaces Serial Interfac e Timing Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 130 Panasonic 5.5.2 U ART Mode Timing In these timing charts, the character leng th is 8 bits, the parity is none, and the stop bit is 2-b it.
Serial Interfaces Serial Inter face Setup Examples MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 131 Panasonic 5.6 Seri al Inte rfac e Setup Ex ample s 5.6.1 Setting U p U ART T rans mission U sing Seria l Interface 0 Y ou must use an 8-bit timer to set the tr ansfer cloc k.
Serial Interfaces Ser ial In terfac e Se tup Ex amples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 132 Panasonic ■ T o set up seria l interface 0: 1. Conf igure the trans mission settings in the serial port 0 contro l re gister (SC0CTR).
Serial Interfaces Serial Inter face Setup Examples MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 133 Panasonic ■ T ransmiss ion sequenc e: 1. Writ e the first data byte to SC0T RB . Once this data is in the register , trans - missio n be gins, syn chronized to t imer 0.
Serial Interfaces Ser ial In terfac e Se tup Ex amples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 134 Panasonic 5.
Serial Interfaces Serial Inter face Setup Examples MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 135 Panasonic 5.6.3 Setting Up the Ser ial Interface Clock This e x ample demonstrates ho w to set up a 19,2 00 bps transfer clock for the U AR T interface by using timer 1 t o di vide B OSC /4 by 39 .
Serial Interfaces Ser ial In terfac e Se tup Ex amples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 136 Panasonic Do not change the cloc k source once you select it. Sel ecting the clock source while you set up the count operati on control will corrupt the value in the binar y counter .
Serial Interfaces Serial Inter face Setup Examples MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 137 Panasonic 5.6.4 Setting U p I 2 C T ran smissio n Using Serial Inte rface 0 This example illustrates the microco ntroller as a master transmitter in the I 2 C mode, usin g the SBO0 and SBT0 pins.
Serial Interfaces Ser ial In terfac e Se tup Ex amples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 138 Panasonic Reception must be enabled f or the circuit to det ect a stop sequence. 2. When you per form step 1, the SBT0 outpu t signal g oes high.
Serial Interfaces Serial Inter face Setup Examples MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 139 Panasonic 5.6.5 Setting U p I 2 C R eception Usin g Serial Interface 0 This e xample illustrates the microcontroller as a master recei ver in the I 2 C mode, using th e SBO 0 and S BT0 pin s.
Serial Interfaces Ser ial In terfac e Co ntrol Regist ers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 140 Panasonic 5.
Serial Interfaces Serial Interface Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 141 Panasonic SCnICM: Ser ial por t n I 2 C mode sel ect .
Serial Interfaces Ser ial In terfac e Co ntrol Regist ers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 142 Panasonic SC0STR/SC1STR: Ser ial P or t n Status R e gister x’00FD83’/x ’00FD8B’ SCnSTR contains the error d etection and status flags for the serial inter- faces.
Analog-to- Digital Converter Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 143 Panasonic 6 Analo g-to-Dig ital C on ver ter 6.1 Des cription The MN102H75K/85 K contains an 8-bit charge redistrib ution A/D c o nv erter (ADC) that can process up to 12 channels.
Analog-to-Digital Converter Bloc k Diag ram Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 144 Panasonic 6.3 Block Diagram 6.
Analog-to- Digital Converter A/D Conver sion Timing MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 145 Panasonic 6.4.2 Single Channe l/Single Co n version T imin g When ANMD[1:0] = b’00’, th e ADC con verts one ADIN input signal a single time.
Analog-to-Digital Converter A/D Conversion Timing Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 146 Panasonic 6.4.4 Single Channe l/Contin uous Con version T iming When ANMD[1:0] = b’10’, th e ADC con verts one ADIN input signal contin- uously .
Analog-to- Digital Converter ADC Setup Ex amples MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 147 Panasonic 6.5 ADC Set up Examples 6.5.1 Setting Up Softw are -Controlled Single-Channel A/D Con version This example illustrates si ng le-channel con version controlled by the software.
Analog-to-Digital Converter ADC Setup Exam ples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 148 Panasonic AN6BUF (e x ample) x’00FF1 4’ 6.5.2 Setting Up Hardware- Controlled Interm ittent Th ree-Channel A/D Con v ersion This example illustrates multip le-channel conv ersion controlled by the hardware.
Analog-to- Digital Converter ADC Setup Ex amples MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 149 Panasonic ■ T o set up the i nput por t: Set the P0DIR[5:3] bi ts of the port 0 I/O cont rol register (P0DIR) to 0.
Analog-to-Digital Converter ADC Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 150 Panasonic 6.6 ADC Cont r ol Re gisters The ADC contains thirteen re gisters— one control re gister (ANCTR) and twelv e data b u ffers (each associated with one of t he ADIN pins).
Analog-to- Digital Converter ADC Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 151 Panasonic ANCTR: ADC Control Register x’00FF0 0’ AN.
Analog-to-Digital Converter Cautions abo ut Analog-to-Digita l Converter Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 152 Panasonic 6.
On-Screen Display Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 153 Panasonic 7 On-Screen Displa y If you use the OSD function, the DMA function ex ecutes for both the te xt and graphics la yers, e ven if y our program does not use one of these la yers .
On-Screen Display Bloc k Diag ram Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 154 Panasonic 7.3 Block Diagram Figure 7-1 O SD Block Diagram VSYNC Vertical p.
On-Screen Display Power-Saving Considerations in the OSD Blo ck MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 155 Panasonic 7.4 P ower -Saving Considerations in the OSD Bloc k T able 7-2 sho ws bits that can decrease the power consumption of the OSD block.
On-Screen Display OSD O per ation Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 156 Panasonic 7.5 OSD Operation This sect ion descr ibes the basic operation of the OSD block. The remainder of section 7 pro v i des more det ai le d specif ications.
On-Screen Display OSD Opera tion MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 157 Panasonic ■ Graphi cs la yer The graphics layer contains tiled images. In the 16-color mode, each 4-bit dot on a tile can display one of 16 colo rs.
On-Screen Display OSD O per ation Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 158 Panasonic 7.5.7 Conditions for VR A M Writes ■ T ext layer Set CHP , CV P , GHP , and GVP f or ev er y line in the VRAM. If you do not, a soft ware processing error may occur .
On-Screen Display Standa rd and Exten ded Display Mode s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 159 Panasonic 7.6 Standard and Extended Di spla y Modes T wo modes are a v ailable for the graph ics and cursor layers, standard and e xtended.
On-Screen Display Standard and Extend ed Display Mode s Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 160 Panasonic In standard mode, STC 0 is the only cursor tile co de register that is enabled.
On-Screen Display Display Setup Examples MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 161 Panasonic 7.7 Display Setup Examples 7.7.1 Setting Up the Gr aphics Layer This sect ion sho ws ho w to set up the graphi cs displa y data in t he VRAM.
On-Screen Display Display Setu p Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 162 Panasonic Figure 7 -4 Graph ics Displ ay Example Line 1 HSZ= 1 (2x.
On-Screen Display Display Setup Examples MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 163 Panasonic 7.7.2 Setting Up the T ext Layer This section sh ows ho w to set up the text display data in th e VRAM.
On-Screen Display Display Setu p Examples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 164 Panasonic The te xt displa y starts one dot to the right of the HP setting.
On-Screen Display VRAM MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 165 Panasonic 7.8 VRAM 7.8. 1 VRAM Op erat ion ■ T ext Layer CC: Charac ter Code ID Code: 00 CCH[9:0] Specifi es the address of one o f 1024 characters stored in the R OM.
On-Screen Display VRAM Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 166 Panasonic BLINK Specifies character blink i ng. 0: Disa ble 1: Enable BCOL[3:0] Specifi es the backgroun d color (1 of 16 colors). CCOL[3 :0] Specifi es the fore ground (character) color ( 1 of 16 colors).
On-Screen Display VRAM MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 167 Panasonic CHP: Char acter Horizontal P osition Control Code ID Code: 1 1 CHSZ[1:0] Specifies the H size of the characters on the ne xt line.
On-Screen Display VRAM Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 168 Panasonic GCB[3:0] Specif i es the number o f times (up to 16) a blank or graphi c ti le is repeated. GPRT Specifies grap hics color palette 1 or 2.
On-Screen Display VRAM MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 169 Panasonic 7.8.2 VRAM Organiz ation Notes: 1. All addresses are expressed i n hex notation. Other values are deci mal. 2. G RAMEND: Graph i cs RAM end address (programma ble to any address) 3.
On-Screen Display VRAM Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 170 Panasonic A. GE XTE = 1 B. GE XTE = 0 Figure 7-7 Graphic s VRAM Organ ization for T w.
On-Screen Display VRAM MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 171 Panasonic 7.8.3 Cautions ab out the number of display code set to VRA M When the di.
On-Screen Display ROM Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 172 Panasonic 7.9 ROM 7.9.1 R OM Or ganizatio n Notes: 1. All addresses are expressed i n hex notation. Other values are deci mal. 2. G R OME ND: Graphics ROM end addre ss (programm able to any address) 3.
On-Screen Display ROM MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 173 Panasonic 7.9.2 Graph ics ROM Organ izatio n in Different Color Modes The graphics layer supports up to sixteen colors, in the 16-color m ode, b u t also supports 2-, 4- , and 8-color modes.
On-Screen Display ROM Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 174 Panasonic Figure 7-11 G raphics R OM in the Four Color Mode s (16W x 16H Tiles) ROMEND.
On-Screen Display ROM MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 175 Panasonic Figure 7-12 G raphics R OM in the Four Color Mode s (16W x 18H Tiles) ROME.
On-Screen Display ROM Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 176 Panasonic Figure 7- 13 Graphics ROM Or ganization in 16-Color Mode (16W x 16H Tiles) F.
On-Screen Display ROM MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 177 Panasonic Figure 7- 17 Graphics ROM Or ganization in 16-Color Mode (16W x 18H Tiles).
On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 178 Panasonic 7.10 S etting Up t he OSD 7.10.1 Se tting Up the OS D Display Colo rs This section des cribes how to set up the display colors for the OSD.
On-Screen Display Setting Up the OSD MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 179 Panasonic ■ T o set up the te xt displa y colors: Write to the fields described below . ♦ CCOL[3:0] (CO L bits 3 to 0 in the RA M data) sets the color of t he charac- ter .
On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 180 Panasonic T r anslucency Selecting YS palette output, by setting the YSPL T bit of OSD1 (x’007F06’) to 1, disab les the PR YM bit.
On-Screen Display Setting Up the OSD MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 181 Panasonic T able 7-9 RGB, YM, and YS Output Contr ol Settings YSPL T .
On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 182 Panasonic Figure 7-21 OSD Signal W ave form TV Graphics la yer Color pa.
On-Screen Display Setting Up the OSD MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 183 Panasonic Figure 7-22 OSD Sig nal Output Switches *** YM3 Bit 15 *** .
On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 184 Panasonic 7.10.2 T ext Layer F unctions This section describes the cha r acter enhancement functions av ailable in the te xt layer .
On-Screen Display Setting Up the OSD MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 185 Panasonic ■ Bo x shadowing In normal mode, writing a 1 to b it 12 (BSHAD1) o f the COL s etting in the VRAM causes a box shado w to appear around all ch aracters follo wing that COL.
On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 186 Panasonic ■ Italicizin g In closed-caption mod e, writ ing a 1 to bit 10 (IT ALIC) of the COL settin g in the VRAM italicizes all characters follo wing that COL.
On-Screen Display Setting Up the OSD MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 187 Panasonic 7.10.3 D isplay Sizes ■ Graphic ti le siz es The settings shown are f or interlaced displays .
On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 188 Panasonic ■ Characte r sizes The settings sho wn are for interlaced displa ys. In progressiv e displays, the vertical size settings (CVSZ[1:0]) are as f ollows: 01 = 1x, 10 = 2x, and 11 = 3x.
On-Screen Display Setting Up the OSD MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 189 Panasonic 7.10.4 Se tting Up the OS D Display P osition This sect ion descr ibes how t o control th e positioning of the OSD.
On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 190 Panasonic ■ T o set up the v er tical position: Cursor ♦ Write the vertical position of the cursor to th e SVP[9 :0] field (x’007F14 ’).
On-Screen Display DMA and Inte rrupt Timing MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 191 Panasonic 7.11 DMA and Interrupt Timing This sect ion descr ibes how t he MN102H75K/8 5 K handles the timing of direct memory access (DMA) transfers of OSD data and OSD interrupts.
On-Screen Display DMA and Inte rrupt Timing Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 192 Panasonic Figure 7-30 DMA an d Interrupt Timing f or the OSD Tex.
On-Screen Display Selecting the OSD Dot Clock MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 193 Panasonic 7.
On-Screen Display Controlling the Shuttering Effect Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 194 Panasonic 7.13 Contr olling the Shuttering Effect The MN102H75K/ 85K OSD ach ie ves a sh uttering effect using four pro - grammable shutters — two vertical and tw o h orizo ntal.
On-Screen Display Controlling the Shu t tering Effect MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 195 Panasonic Figure 7-3 1 Shuttered Area Se tup Example.
On-Screen Display Controlling the Shuttering Effect Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 196 Panasonic 7.
On-Screen Display Controlling the Shu t tering Effect MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 197 Panasonic Figure 7- 32 Shutter Mo vement Setup Ex am.
On-Screen Display Controlling the Shuttering Effect Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 198 Panasonic 7.13.3 Co ntrolling Shutterin g Ef fects Through register set tings, you can inde pendently control shuttering f or text, te xt backgroun d, graphics, and col or backgroun d.
On-Screen Display Controlling the Shu t tering Effect MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 199 Panasonic ■ T o shutter the co lor backgr ound: Set the color backg rou nd shut ter con trol bit, COLBSHT , of the shutter cont rol re gister , SHTC (x’00 7F28’) to 1.
On-Screen Display Controlling the Shuttering Effect Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 200 Panasonic 7.
On-Screen Display Field Detection Circuit MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 201 Panasonic 7.14 Field Detection Cir cuit 7.14.1 Block Diagr am 7.14.2 D escription The 7-bit field counter in this block reset s e very HSYNC interval to count the system clock.
On-Screen Display Field Detection Circuit Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 202 Panasonic 7.14.3 Co nsiderations for I nterlaced Displays ■ Switch ing the displ ay start field The OSD is constructed so the display start p osition is the field (f ield 1) where the EOMON bit is 1.
On-Screen Display OSD Regis ters MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 203 Panasonic 7.15 OSD Re gisters All registers in OSD block canno t be written by byte (by word only). Read by byte is poss ible.
On-Screen Display OSD Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 204 Panasonic is x’900F ’ to x’9FFF ’, with a programmable range from x’00’ to x’FF’.
On-Screen Display OSD Regis ters MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 205 Panasonic STC3: Cursor Tile Code Register 3 x’007E2E’ SPR T3: Cursor .
On-Screen Display OSD Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 206 Panasonic 00: 1 dot = 1 VCLK peri od 01: 1 dot = 2 VCLK peri ods 10: 1 dot =.
On-Screen Display OSD Regis ters MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 207 Panasonic CIVSZ[1:0]: T ext initial v er tical siz e CIVP[9:0] : T ext in.
On-Screen Display OSD Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 208 Panasonic OSD1: OSD Regi ster 1 x’00 7F06’ A write to the OS D bit of OSD1 takes eff ect on the ne xt leading edge of VSYNC.
On-Screen Display OSD Regis ters MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 209 Panasonic OSD2: OSD Regi ster 2 x’007F0 8’ SPEXT: Cursor ex tended mo.
On-Screen Display OSD Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 210 Panasonic OSD3: OSD Regi ster 3 x’007F 0A’ BLINK: Characte r bli nking control Controls blinking for text-layer characters with BLINK set in the COL code.
On-Screen Display OSD Regis ters MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 211 Panasonic VSHT1: V er tical Shutter 1 Register x’007F2 2’ VSON1: V er.
On-Screen Display OSD Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 212 Panasonic HSHT1: Horizo ntal Shutter 1 Register x’00 7F26’ HSON: Horizo .
On-Screen Display OSD Regis ters MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 213 Panasonic CPT0 – CPTF: T e xt P alette C olors 0 – 15 Re gisters x’007F80’ – x’007F9E’ These reg isters contain the colors used in the text layer .
On-Screen Display OSD Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 214 Panasonic BBSHD: Blac k Bo x Shadowi ng Regi ste r x’007F A4’ This re gister con t ains the color used as black in bo x shad o wing.
On-Screen Display OSD Regis ters MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 215 Panasonic GPT20 – GPT2F: Graphi cs P alette 2 Colors 0 – 15 Registers x’007FE0’ – x’007FFE’ These re gisters contain one of tw o sets of colors used in the graphics laye r .
IR Remote Signal Receiver Description Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 216 Panasonic 8 IR Remo te Signal Receiver 8.
IR Remote Signal Receiver Block Diagram MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 217 Panasonic 8.2 Block Diagram Figure 8 -1 IR Remot e Signal Receiver Block Di agram 54 3 2 1 0 MUX CK CK 765 4 32 1 0 MUX CK MUX R CK 4 RMTC: x’007E04’ Frequency division counter PWM3 (375 kHz, 2.
IR Remote Signal Receiver IR Remote Signal Receiver Oper ation Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 218 Panasonic 8.3 IR Remote Signal Re ceiver Ope ration 8.3.1 Operating Modes The IR remote signal recei ver has three operatin g mod es: HEAMA, 5-/6-bit, and HEAMA – 5-/6-bit automatic detect.
IR Remote Signal Receiver IR Remo te Signal Rece iver Operation MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 219 Panasonic 8.3.3 8-Bit Data R eception Resetting the 8-bit data reception counter allows the microcontroller to receiv e 8- bit data, eith er with or without a leader .
IR Remote Signal Receiver IR Remote Signal Receiver Oper ation Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 220 Panasonic 8.3.4 Identifyi ng the D ata F ormat The microcontrol ler determines the l ogic lev els of the data by testing th e interval between remote signal edges.
IR Remote Signal Receiver IR Remo te Signal Rece iver Operation MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 221 Panasonic 8.
IR Remote Signal Receiver IR Remote Signal Receiver Oper ation Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 222 Panasonic 8.3.6 Controllin g the SLO W Mode Use bit 7 (SP) in the RMLD reg- ister to toggle the noise filter sampling frequency between PWM6/PWM8 and PWM3/ PWM5.
IR Remote Signal Receiver IR Remo te Signal Rece iver Control Re gisters MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 223 Panasonic 8.4 IR Remot e Signal Receiver Control Regis- ters All re gisters in RMC block cannot be wr itten by byte ( by word only) .
IR Remote Signal Receiver IR Remote Signal Receiver Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 224 Panasonic All re gisters in RMC block cannot be wr itten by byte ( by word only) . Read by byte is poss ible.
IR Remote Signal Receiver IR Remo te Signal Rece iver Control Re gisters MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 225 Panasonic RMIS: Remote Signa l Interrupt Status Register x ’007E A0’ RMIR in dicates the detecti on and oper ation status of r emote signal inter- rupts.
IR Remote Signal Receiver IR Remote Signal Receiver Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 226 Panasonic RMLD: Remote Sig nal Leader V alue Set R egister x’007EA C’ RMLD is a 16-bit access re gister .
Closed-Caption Decoder Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 227 Panasonic 9 Closed-Caption D ecoder 9.1 Des cription The MN102H75K/85K contain s two identical closed-cap tion decoder circuits, CCD0 and CCD1.
Closed-Caption Decoder Functional Des cription Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 228 Panasonic 9.3 Functional Description 9.3.1 Analog-to-Dig ital Con verter The const an ts shown in figures 9-2 to 9-4 ar e re comm e nded values only .
Closed-Caption Decoder Functional Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 229 Panasonic 9.
Closed-Caption Decoder Functional Des cription Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 230 Panasonic T able 9-5 pro vides the registers used to contro l and mo nitor the clamp ing cir cuit. See the page number ind icated for re gist er and bit descriptions.
Closed-Caption Decoder Functional Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 231 Panasonic Figure 9-6 Sync Separator Ci rcuit Bloc k Diagram .
Closed-Caption Decoder Functional Des cription Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 232 Panasonic 9.3.3.1 HSYN C Sep arator The HSYNC separator e x tracts the HSYNC signal from the composite sync signal u s ing the sampli ng clock generated b y the sync separat or clock pulse g en- erator .
Closed-Caption Decoder Functional Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 233 Panasonic 9.3.3 .2 V SYNC Se parator The VSYNC separator e x tracts the VSYNC signal from the composite signal.
Closed-Caption Decoder Functional Des cription Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 234 Panasonic T able 9-7 pro vides the registers used to control and mon it or the data slicer . See the page number ind icated for register and bit descriptio ns .
Closed-Caption Decoder Functional Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 235 Panasonic 9.3.5.1 CRI Detection for Sampling Clock Generation The decoder cap tures the caption data on the rising edge of the C RI pulse.
Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 236 Panasonic 9.4 Closed-C aption Decoder Registers All registers in Closed-caption Decoder block cannot be written by byte (by word only).
Closed-Caption Decoder Close d-C aptio n Dec oder R egi ster s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 237 Panasonic For desig ns using the closed -cap- tion de coder, always tie the FCC NT register to x’0008’ .
Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 238 Panasonic MAXMIN: CRI Int er v al Max imum and M.
Closed-Caption Decoder Close d-C aptio n Dec oder R egi ster s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 239 Panasonic HNUM: HSYNC Count Register x’00.
Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 240 Panasonic CRIF A: CRI F requency Width Regist er.
Closed-Caption Decoder Close d-C aptio n Dec oder R egi ster s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 241 Panasonic CRI1E: CRI Cap ture Stop Timing C.
Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 242 Panasonic DA T A E : Data Cap ture Stop Ti ming .
Closed-Caption Decoder Close d-C aptio n Dec oder R egi ster s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 243 Panasonic FQSEL: F requency Select Regis te.
Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 244 Panasonic Use this register to specify the position for capturing the pedestal level v alue used during p edestal clampi ng.
Closed-Caption Decoder Close d-C aptio n Dec oder R egi ster s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 245 Panasonic BSP[5:0]: Sy nc separator l e vel f or pedes tal clam ping Sync separator level = (sync tip le vel/2) + BSP[5:0].
Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 246 Panasonic HSEP1: HSYNC Separ a tor Control Regis.
Closed-Caption Decoder Close d-C aptio n Dec oder R egi ster s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 247 Panasonic HDISTW: Sy nc Separator D etectio.
Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 248 Panasonic CLPCND1: Clamping Control Si gnal Stat.
Pulse Width Modulator Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 249 Panasonic 10 Pulse Width Mod ulator 10.
Pulse Width Modu lator Bloc k Diag ram Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 250 Panasonic Not using internal pullup func- tion,Figuer10-2 connect the e x ter n al pullup registance 10.2 Block Diagram 10.
I/O Ports Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 251 Panasonic 11 I/O P or ts 11.1 De scripti on The MN102H75K/85 K contains 50 pins th at form general-purp ose I/O ports. Ports 0, 1 , 2, 3, 4, and 5 are 8-b it ports , and port 6 is a 2-bi t por t.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 252 Panas oni c 11.2 I/ O P ort Circuit Dia grams Figure 11- 1 P00/RMIN/IR.
I/O Ports I/O Port Cir cuit Diag rams MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 253 Panasonic Figure 11-2 P03/ADIN0 to P0 7/ADIN4 (P or t 0 ) P0PUPn 0: .
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 254 Panas oni c Figure 11-3 P10/ADIN5/IRQ1, P11/ ADIN6/IRQ2, and P12/ADIN7.
I/O Ports I/O Port Cir cuit Diag rams MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 255 Panasonic Figure 11-4 P1 3/ADIN8/WDOUT and P14/ADIN9/ST OP (P ort 1).
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 256 Panas oni c Figure 11-5 P15/AD IN10/PWM0 an d P16/ADIN11/PWM1 (P ort 1.
I/O Ports I/O Port Cir cuit Diag rams MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 257 Panasonic Figure 11-6 /PWM2 (P or t 1), P20/PWM3 , P21/PWM4, P22/PWM.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 258 Panas oni c Figure 11- 7 P24/TM4IC/SBT1 (P ort 2) P2PUP4 0: Pullup off.
I/O Ports I/O Port Cir cuit Diag rams MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 259 Panasonic Figure 11-8 P27/TM0IO (P ort 2) P2PUP7 0: Pullup off 1: Pu.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 260 Panas oni c Figure 11-9 P3 5/D AR OUT/R, P36/D A GOUT/G, P37/ DABOUT/B.
I/O Ports I/O Port Cir cuit Diag rams MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 261 Panasonic Figure 11-1 0 P25/TM4IOB/SBI1/SBD1 a nd P26/TM4 IO A/SBO1 .
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 262 Panas oni c Figure 11-1 1 P55 and P56 (P ort 5) P5PUP5 0: Pullup off 1.
I/O Ports I/O Port Cir cuit Diag rams MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 263 Panasonic Figure 11-12 P 57/SBT0 (P or t 5) P5PUP7 0: Pullup off 1: .
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 264 Panas oni c Figure 11-1 3 P02/SCL1 (P or t 0) and P61/SCL0 (P ort 6) P.
I/O Ports I/O Port Cir cuit Diag rams MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 265 Panasonic Figure 11-14 P01/SD A1 (P ort 1) and P60/SD A0 (P ort 6) P.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 266 Panas oni c Figure 11-15 P31/CVBS0 and P3 2/CVBS1 (P ort 3) P3PUPn 0: .
I/O Ports I/O Port Cir cuit Diag rams MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 267 Panasonic Figure 11-16 P30/CLH and P3 3/CLL (P ort 3) P3PUPn 0: Pull.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 268 Panas oni c Figure 11-17 P34/VREF (P or t 3) P3PUP4 0: Pullup off 1: P.
I/O Ports I/O Port Cir cuit Diag rams MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 269 Panasonic Figure 11-18 P 41/TM1IO , P42/TM5IO A, and P43/TM5IOB/HI 0.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 270 Panas oni c Figure 11-20 P45/OSDXO and P46/OSDXI (Po rt 4) P4PUP6 (0: Cut,1: Connect) 0: Pullup off 1: Pullup on LCCNT is the OSDXI/O oscillation control signal from the OSD.
I/O Ports I/O Port Cir cuit Diag rams MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 271 Panasonic Figure 11-21 P47/HSYNC (P or t 4) P4PUP7 0: Pullup off 1: .
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 272 Panas oni c Figure 11-22 P50/SYSCLK (P or t 5) P5PUP0 0: Pullup off 1:.
I/O Ports I/O Port Cir cuit Diag rams MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 273 Panasonic Figure 11-23 P51/YS (P or t 5) P5PUP1 0: Pullup off 1: Pul.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 274 Panas oni c Figure 11-24 P52/IRQ4/VI0 (P ort 5) P5PUP2 0: Pullup off 1.
I/O Ports I/O Port Cir cuit Diag rams MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 275 Panasonic Figure 11 -25 P53/RST (P ort 5) P5PUP3 0: Pullup off 1: Pu.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 276 Panas oni c Figure 11-26 P54/IRQ5/VSYNC (P or t 5) P5PUP4 0: Pullup of.
I/O Ports I/O Port C ontrol Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 277 Panasonic 11.3 I/ O P or t Contr ol Registers Do not activ ate the pullup resis- tors when the pins are in output mode.
I/O Ports I/O Port Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 278 Panas oni c P0IN – P5IN: P or ts 0 – 5 Input Re gisters x’00FFD0 .
I/O Ports I/O Port C ontrol Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 279 Panasonic P0MD: P ort 0 Output M ode Register x’00FFF0’ P0MD is an 8-bit access reg is ter .
I/O Ports I/O Port Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 280 Panas oni c P1MD: P ort 1 Output M ode Register x’00FFF 2’ P1MD is a 16-bit access reg is ter .
I/O Ports I/O Port C ontrol Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 281 Panasonic P2MD: P ort 2 Output M ode Register x’00FFF4’ P2MD is a 16-bit access reg is ter . P2MD14 : P27 func tion swit ch T o use TM0IO as an o utput p in, set this bit to 1 and set th e P2DIR7 bit to 1.
I/O Ports I/O Port Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 282 Panas oni c P3MD: P ort 3 Output M ode Register x’00FFF 6’ P3MD is an 8-bit access reg is ter . P3MD7: P37 output switc h If you set this field to 1, select D AB OUT or B in the RGBC bit of ODS 1.
I/O Ports I/O Port C ontrol Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 283 Panasonic P4MD: P ort 4 Output M ode Register x’00FFF8’ P4MD is an 8-bit access reg is ter . P4MD7: P47 function s witch 0: P47/NHSYNC 1: NHSYNC P4MD6 This bit exists, but contains no funct ion.
I/O Ports I/O Port Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 284 Panas oni c P5MD: P ort 5 Output M ode Register x’00FFF A’ P5MD is an 8-bit access reg is ter . P5MD7: P57 output switc h T o use SBT0 a s an input pin, set this fie ld to 0 and set the P5DIR7 bit to 0.
I/O Ports I/O Port C ontrol Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 285 Panasonic PCNT0: P or t Control R egister 0 x’00FF90’ PCNT0 is a 16-bit access register . Enable PWM (set PCNT1 bit 1 to 1) if you are out putting f SY- SCLK /2 14 .
I/O Ports I/O Port Control Registers Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 286 Panas oni c T o turn off the OSD b loc k to sa ve powe r : 1. Write a 0 to OSD ( OSD1, bit 10). 2. W ait f or the nex t VS YNC input.
I/O Ports I/O Port C ontrol Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 287 Panasonic PCNT2: P or t Control R egister 2 x’00FF92’ Alwa ys set bits 7 to 3 of PCNT2 to 0. Y ou cannot read from or write to the registers associated with a function that is disabl ed.
ROM Correction Description Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 288 Panasonic 12 R OM Co rrection 12.1 De scripti on The R OM correction function can correct the p rog ram data in an y address within the 256-kilobyte R OM.
ROM Correction Block Diagram MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 289 Panasonic 12.2 Block Diagram Figur e 12- 3 i s a blo ck di agr am of the R O M cor rect i on circu it. A match detect io n circuit constantly monitor s the R OM address specified by the CPU instruction pointer (IP).
ROM Correction ROM Correction Control Re gisters Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 290 Panasonic 12.4 R OM Correction Control Register s T able 12-1 sho ws the organ ization of the address match and d ata registers for R OM correction.
ROM Correction ROM Corr ection Control Re gisters MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 291 Panasonic R OMCEN12: Addres s 12 R OM correc tion enab l.
ROM Correction ROM Correction Control Re gisters Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 292 Panasonic AMCHIH0 – AM CHIHF: R OM Correct ion Address Matc h Regis ter n (Hi gh) AMCHIHn is an 8-bit access re gister .
I 2 C Bus Controller Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 293 Panasonic 13 I 2 C Bus Controller 13.1 De scripti on The MN102H75K/85 K contains one I 2 C b u s controller , fully compliant with the I 2 C specif ication, that can control o n e of two I 2 C bus connections.
I 2 C Bus Controller Description Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 294 Panasonic Figure 13-2 sho ws an e x ample of an I 2 C bus conf iguratio n using two microcon- trollers.
I 2 C Bus Controller Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 295 Panasonic Figure 13-3 sho ws the MN102H75K/8 5K operation sequence in each of these modes.
I 2 C Bus Controller Bloc k Diag ram Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 296 Panasonic 13.2 Block Diagram 13.3 Functional Description The I 2 C b us controll er contai ns the re gisters sho wn in t able 13-3.
I 2 C Bus Controller Functional Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 297 Panasonic ■ Register settings con v ersions to I 2 C pr otocol The I 2 C b u s co ntroller con verts the data in the I2CDTRM register to the I 2 C protoco l.
I 2 C Bus Controller Setting Up the I 2 C Bus Con n ection Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 298 Panasonic 13.4 S etting Up t he I 2 C Bus Connection Set the I 2 C connection in the I2CSEL0 and I2CSEL1 bits of the PCNT0 re gister (x’00FF90’).
I 2 C Bus Controller SDA and SCL W aveform Characteristics MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 299 Panasonic 13.5 SD A and SCL W avef o rm Char acteri stics Figur e 13-6 and t able 13- 5 provide t he timin g defini tions and specif ications for the for the MN102H75K/ 85K I 2 C bus interface.
I 2 C Bus Controller I 2 C In terf ace Se tup Ex amples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 300 Panasonic 13.
I 2 C Bus Controller I 2 C Interfac e Setup Example s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 301 Panasonic 13.
I 2 C Bus Controller I 2 C In terf ace Se tup Ex amples Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 302 Panasonic 13.
I 2 C Bus Controller I 2 C Interfac e Setup Example s MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 303 Panasonic 13.6.2.3 Setting Up the Second I nterrupt The master sends an A CK = 0 signal, so the m icrocontroller must send the ne xt data byte.
I 2 C Bus Controller I 2 C Bu s Inte rface Regi ster s Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 304 Panasonic 13.7 I 2 C Bus Int erface Register s All registers in I 2 C bloo k cannot be wri tten by byte ( by wo rd onl y).
I 2 C Bus Controller I 2 C Bus Interface Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 305 Panasonic I2CDREC: I 2 C Recepti on Data Register x’00 7E42’ The I2CDREC re gister contains the status bits for monitoring the d evice and the reception data.
I 2 C Bus Controller I 2 C Bu s Inte rface Regi ster s Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 306 Panasonic I2CCLK: I 2 C Cloc k Control Register x’007E46’ T o conform to the specification, the clock signal must be between 0 and 100 kHz.
H Counter Description MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 307 Panasonic 14 H Counter 14.1 De scripti on The MN102H75K/85K contain s two H coun ter circuits that can be u sed to count the HSYNC signal.
H Counter H Counter Operation Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 308 Panasonic Figure 14-3 shows the input timing for the count sou rce and reset signals. Never input a count so urce signal in less th an 2 45 ns (t 1 ) af ter the reset signal input.
H Counter H Counter Operation MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 309 Panasonic The H counter counts the HSYNC signal for t he interv al set in the HCCNT0 (x’007EB 0’) or HCCNT1 (x’007EB 2’) re gister , la tc hes the co un t valu e in the 10- bit register , then clears the co unter .
H Counter H Counter Control Re gisters Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 310 Panasonic 14.4 H Counter Contr ol Registers All registers in H Counter block cannot be written by by te (by word only). Read by byte is po ssibl e .
H Counter H Counter Control Registers MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 311 Panasonic HCD0: H Counter D ata Re gister 0 x’00 7EB4 ’ HCD[90:00]: Count from HI0 source signal This f ield stores the HI0 clock sou rce count.
Register Map Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 312 Panasonic Appendix A Register Map T able A-1 Re gister Map: x’007E00 ’ to x’007FF F’ (Registers in this area cannot b e wr itten by b yte only b y word.
Register Map MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 313 Panasonic T able A-2 Registe r Map: x’00FC00’ to x’00FDFF’ 20 MSBs 4 LSBs Description.
Register Map Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 314 Panasonic T able A-3 Re gister Map: x’00FE00’ to x’00FFFF’ 20 MSBs 4 LSBs Description F.
Register Map MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 315 Panasonic.
MN102HF75K Flash EEPRO M Version Description Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 316 Panasonic Appendix B MN102HF 75K Flash EEPR OM V er sion B.1 Descri ption The MN102HF75K and MN102HF85K are electrically pro grammable, 256- kilobyte f l ash R OM versio ns of th e MN102H75K and MN102H85K.
MN102HF75K Flash EEPROM Ve rsion Benefits MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 317 Panasonic B.2 Benefits Because you can maintain and upgr ade the.
MN102HF75K Flash EEPRO M Version Using the PROM Writer Mo de Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 318 Panasonic Check th e follo wing web page of our microc omputer di vision for t he writer matching info rmation.
MN102HF75K Flash EEPROM Ve rsion Using the Onboard Serial Programmi ng Mode MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 319 Panasonic B.
MN102HF75K Flash EEPRO M Version Using the O nboard Se rial Programming Mo de Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 320 Panasonic B.
MN102HF75K Flash EEPROM Ve rsion Using the Onboard Serial Programmi ng Mode MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 321 Panasonic B.4.2 Circuit Requirem ents for the T arget Board ■ Duri ng pr o gram ming , the s eri al wri ter s up plies V PP to the microcontro ller .
MN102HF75K Flash EEPRO M Version Using the O nboard Se rial Programming Mo de Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 322 Panasonic B.4.3 Microcon troller Hardware U sed in Onboard Serial Pro- grammin g B.
MN102HF75K Flash EEPROM Ve rsion Using the Onboard Serial Programmi ng Mode MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 323 Panasonic B.4.4 Microcon troller Memory Map Used Durin g Onboa rd Serial Progra mming B.
MN102HF75K Flash EEPRO M Version Using the O nboard Se rial Programming Mo de Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 324 Panasonic ■ Branch in struct.
MN102HF75K Flash EEPROM Ve rsion Using the Onboard Serial Programmi ng Mode MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 325 Panasonic B.4.6 Setting Up the On board Serial Pr ogrammin g Mode T o enter serial pro gramming mode, t he microcon troller must b e in write mode.
MN102HF75K Flash EEPRO M Version Using the O nboard Se rial Programming Mo de Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 326 Panasonic ■ Start routin e for the load pr ogram Condi tions : 1. After the load prog ram initiates a reset start, SB D must be lo w and SBT high .
MN102HF75K Flash EEPROM Ve rsion Using the Onboard Serial Programmi ng Mode MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 327 Panasonic B.
MN102HF75K Flash EEPRO M Version Reprogram ming Flow Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 328 Panasonic B.5 Repr ogramming Flow Figur e B-12 sho ws the flo w for rep rogramming (erasi ng and pro gramming) the flash memory .
page Line defin i- Description of Changes tion Former version New version Cover Pub number C 22385-010E 22385-011E Colophon C September, 2001 1st Edition October, 2001 1st Edition 1st Printing Sales office C Latest version MN102H75K/F75K/85K/F85K LSI User's Manual Description Record of Changes (Ver.
MN102H75K/F75K/85K/F85K LSI User’s Manual Modified Points From MN102H75K/F75K To MN102H75K/F75K/85K/F85K MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 1 Panasonic page Bef ore Modify page After Modify P16 This manual is intended for assembly-l anguage programming engineers.
Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 2 Panasonic P30 1.6 Pin De scr iptions 1.6.1 MN102H85K Pin Description Notes : 1. Pins marked with an asterisk (*) are N-channel, open-drain pins. 2. P in 25 is V DD in the MN102H85K and V PP in the MN102HF85K.
MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 3 Panasonic P33 The MN102H75K contains an inter nal PLL circuit. T o use this circuit, you must connect it to an external (lag-lead) f ilter . P34 The MN102 H75K/85K contains an internal PLL ci rcuit.
Panasonic Semiconductor Development Compa ny MN102H75K /F75K/85K /F85K LSI Us er Manual 4 Panasonic P77 The MN102H75K contains four 8-bit timers t hat can serve as int erval timers, event timer/counters, cl ock generators ( di vide-by-2 output of the underflow), reference clocks for the serial interf aces, or start timers for A/D con versions.
MN102H75 K/F75K/85K/F85K LSI Us er Manual Panaso nic Se miconductor Developm ent Compa ny 5 Panasonic P307 The MN102H75K contains two H counter cir cuits that can b e used to count the HSYNC signal.
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Issued by Matsushita Electric Industrial Co., Ltd. Matsushita E lectric I ndustrial Co., Ltd. MN10 2H75 K/F75K /85K /F85K LSI U ser ’s Manua l October ,2001 1st E d ition 1 st Printi ng.
Semiconductor Company, Matsushita Electric Industrial Co., Ltd. Nagaokakyo, Kyoto, 617-8520 Japan Tel: (075) 951-8151 http://www.panasonic.co.jp/semicon/ SALES OFFICES ■ NORTH AMERICA ● U.S.A. Sales Office: Panasonic Industrial Company [PIC] • New Jersey Office: Two Panasonic Way Secaucus, New Jersey 07094 U.
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