Gebruiksaanwijzing /service van het product AT91M55800A van de fabrikant Atmel
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Features • Utilizes the ARM7TDMI ® ARM ® Thumb ® Processor Core – High-perf ormance 32-bit RISC Arc hitecture – High-density 16-bit Instruction Set – Leader in MIPS/W att – Embedded ICE (.
2 1745D–ATARM–04-Nov-05 AT91M55800A ity vectored interrup t controller in conjunction with the pe ripheral data controller sig nificantly improve the real-time performance of the device. The device is manufactured us ing Atmel’s high-density CMOS technology.
3 1745D–ATARM–04-Nov- 05 AT91M55800A 2. Pin Configurations Notes: 1. Analog pins 2. Battery back up pins T able 2- 1. Pin Configuration for 176- lead LQFP Package Pin A T91M55800A Pin A T91M55800A.
4 1745D–ATARM–04-Nov-05 AT91M55800A T able 2- 2. Pin Configuration for 176- ball BGA Package Pin A T91M55800A Pin A T91M55800A Pin A T91M55800A Pin A T91M55 800A A1 NCS1 C1 A0/NLB E1 A4 G1 A12 A2 .
5 1745D–ATARM–04-Nov- 05 AT91M55800A J1 A17 L 1 A20 N1 D4 R1 D10 J2 A18 L 2 A23 N2 D6 R2 D11 J3 VDDIO L3 D0 N3 VDDIO R3 D12 J4 A16 L 4 D1 N4 D14 R4 D13 J5 – L5 – N5 PB19/TCLK0 R5 PB20/TIOA0 J6.
6 1745D–ATARM–04-Nov-05 AT91M55800A Figure 2-1. 176-lead LQFP Pinout Figure 2-2. 176-ball BGA Pinout 14 4 176 133 132 89 45 88 123456789 1 0 1 1 1 2 A B C D E F G H J K L M N P R 13 14 15.
7 1745D–ATARM–04-Nov- 05 AT91M55800A 3. Pin Description T able 3- 1. Pin Description Module Name Function T ype Active Level Comments EBI A0 - A23 Address bus Output – D0 - D15 Data bus I/O – .
8 1745D–ATARM–04-Nov-05 AT91M55800A DAC D A0 - DA 1 Anal og output channels 0 - 1 Anal og out – D A VREF Analog ref erence Analog ref – Clock XIN Main oscillator input Input – XOUT Main osci.
9 1745D–ATARM–04-Nov- 05 AT91M55800A 4. Bloc k Diagram ARM7TDMI Core Embedded ICE Reset EBI: External Bus Interface Internal RAM 8K Bytes ASB Controller AIC: Advanced Interrupt Controller AMBA Bri.
10 1745D–ATARM–04-Nov-05 AT91M55800A 5. Ar chitectural Overview The AT91M55800A microcontroller integrates an ARM7TDMI with its embedded ICE inter- face, memories and peri pherals. Its architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB).
11 1745D–ATARM–04-Nov- 05 AT91M55800A The Real-time Clock (RTC) perip heral is desi gned for very low power consumptio n, and com- bines a complete time-of-d ay clock with alarm and a two-hundre d year Gregorian cale ndar, complemented by a prog rammable periodic interrup t.
12 1745D–ATARM–04-Nov-05 AT91M55800A 6. Associated Documentation T able 6- 1. Associated Documentat ion Prod uct Informat ion Document Title Literature Number A T91M55800A Inter nal architecture o.
13 1745D–ATARM–04-Nov- 05 AT91M55800A 7. Product Overvie w 7.1 P o wer Supplies The AT91M5580 0A has 5 kinds of power supp ly pins: • VDDCORE pins, which pow er the chip core • VDDIO pins, whi.
14 1745D–ATARM–04-Nov-05 AT91M55800A 7.3 Master Cloc k Master Clock is generated in one of the following ways, depending on progra mming in the APMC registers: • F rom the 32768 Hz low-po wer os.
15 1745D–ATARM–04-Nov- 05 AT91M55800A In order to benefit the most regarding the separation of NRST and NTRST during the Debug phase of deve lopment, the user must independen tly mana ge both signals as shown in exam- ple (1) of Figure 7-1 above.
16 1745D–ATARM–04-Nov-05 AT91M55800A • Internal peripherals in the f our hig hest megabytes In any of these ad dress spaces, the ARM7TDMI ope rates in Little-End ian mode only. 7.6.1 Intern al Memories The AT91M5580 0A microcontroller inte grates an 8-Kbyte SRAM ba nk.
17 1745D–ATARM–04-Nov- 05 AT91M55800A 7.7 External Bus Interface The External Bus Interface h andles the accesses between addresses 0x0040 0 000 and 0xFFC0 0000. It g enerates the signals that con trol access to the external devi ces, and can configure up to eigh t 16-Mbyte banks.
18 1745D–ATARM–04-Nov-05 AT91M55800A 8. P eripherals The AT91M55800A pe ripherals are connected to the 32-bit wide Advan ced Peripheral Bus. Peripheral registers are only word accessible – byte and half-word accesses are not sup- ported.
19 1745D–ATARM–04-Nov- 05 AT91M55800A Most importan tly, the PDC removes th e processor interrupt handling overhea d and signifi- cantly reduces the num ber of clock cycles requir ed for a data transfer . It can transfer up to 64K contiguous byte s.
20 1745D–ATARM–04-Nov-05 AT91M55800A PIO Controllers called PIOA an d PIOB. The PIO controller enables th e generation of an inter- rupt on input chan ge and insertion of a simple input glitch filter on any of the PIO pins.
21 1745D–ATARM–04-Nov- 05 AT91M55800A Each channel can be enabled or disa bled i ndependently, and ha s its own data register. The ADC can be configured to a utomatically ente r Sleep mode after a conversion sequence, and can be triggered by th e software, the Ti mer Count er, or an external signal.
22 1745D–ATARM–04-Nov-05 AT91M55800A 9. Memory Map Figure 9-1. AT91M55800A Memo ry Map Before and after Remap Co mmand Address Function Size Abort Control 0xFFFFFFFF 0xFFC00000 0xFFBFFFFF 0x004000.
23 1745D–ATARM–04-Nov- 05 AT91M55800A 10. P eripheral Memory Map Figure 1. AT91M55800A Per ipheral Memo ry Map Address Peripheral Peripheral Name Size 0xFFFFFFFF 0xFFFFF000 0xFFFFBFFF 0xFFFF8000 0.
24 1745D–ATARM–04-Nov-05 AT91M55800A 11. EBI: External Bus Interface The EBI generates the sign als that control the access to the exter nal memory or peripheral devices. The EBI is f ully-programmable and can address up to 1 28M bytes. It has eight chip selects and a 24-bit address bus.
25 1745D–ATARM–04-Nov- 05 AT91M55800A 11.1 External Memory Mapping The memory map associates the internal 32- bit address space with the ext ernal 24-bit address bus. The memory map is defined by pr ogramming the base addr ess and page size of the external memories (see EBI User Interface reg isters EBI _CSR0 to EBI_CSR7).
26 1745D–ATARM–04-Nov-05 AT91M55800A 11.2 EBI Pin Description The following table shows how cert ain EBI signals are multiplexed: Name Description T ype A0 - A23 Address bus (output) Output D0 - D.
27 1745D–ATARM–04-Nov- 05 AT91M55800A 11.3 Data Bus Width A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by the DBW field in the EBI_CSR (Chip-select Registe r) for the corresponding chip select. Figure 11-2 shows how to conne ct a 512K x 8-bit memory on NCS2.
28 1745D–ATARM–04-Nov-05 AT91M55800A Figure 11-4. Memory Connecti on for 2 x 8-bit Data Bu sses Byte-select Access is used to connec t 16-bit devices in a memory page. • The signal A0/NLB is used as NLB and enab les the lo wer b yte for both read and write operations .
29 1745D–ATARM–04-Nov- 05 AT91M55800A Figure 11-6 shows how to conne ct a 16-bit device without byte access (e.g. Flash) on NCS2. Figure 11-6. Connection for a 16-bit Data Bu s Without Byte-w rite Capability.
30 1745D–ATARM–04-Nov-05 AT91M55800A 11.6 Read Pr otocols The EBI provides two alternative prot ocols fo r external memo ry read access: standard and early read. The difference between the tw o protocols lies in the tim ing of the NRD (read cycle) waveform.
31 1745D–ATARM–04-Nov- 05 AT91M55800A Figure 11-8. Early Read Prot ocol 11.6.3 Early Read W ait State In early read protocol, an early read wait state is a utomatically inserted when an external write cycle is followed by a r ead cycle to allow time f or the write cycle to end before the subsequent read cycle begins (see Figur e 11-9 ).
32 1745D–ATARM–04-Nov-05 AT91M55800A 11.7 Write Data Hold Time During write cycles in both protocols, output data becomes valid after the falling edge of the NWE signal and remains valid after the rising edge of NWE, as illustrated in the figure below.
33 1745D–ATARM–04-Nov- 05 AT91M55800A 11.8 W ait States The EBI can automatica lly insert wait states. The diffe rent types of wait states are listed b elow: • Standard w ait states • Data float w ait states • External wait states • Chip select change w ait states • Early read wait states (as described in Read Protocols) 11.
34 1745D–ATARM–04-Nov-05 AT91M55800A indicates the number of d ata float wait s to be ins erted and represents the time allow ed for th e data output t o go high impedance after th e memory is disabled. Data float wait states do not delay internal memory accesses.
35 1745D–ATARM–04-Nov- 05 AT91M55800A Figure 11-13. External Wait Notes: 1. Early Read Protocol 2. Standard Read Protocol 11.8.4 Chip Selec t Change Wait States A chip select wait state is aut omatically inserted when consec utive accesses are m ade to two different external memories (if no wait states have already been inserted ).
36 1745D–ATARM–04-Nov-05 AT91M55800A 11.9 Memory Access W avef orms Figure 11-15 t hrough Figure 11-18 show examp les of the two alter native protocols for ex ternal memory read acce ss.
37 1745D–ATARM–04-Nov- 05 AT91M55800A Figure 11-16. Early Re ad Protocol with no t DF Read Mem 1 Write Mem 1 A0 - A23 NRD NWE NCS1 NCS2 D0 - D15 (Mem 1) D0 - D15 (Mem 2) D0 - D15 (AT91) MCK Early .
38 1745D–ATARM–04-Nov-05 AT91M55800A Figure 11-17. Standard Read Protocol with t DF Read Mem 1 Write Mem 1 A0 - A23 NRD NWE NCS1 NCS2 D0 - D15 (Mem 1) D0 - D15 (Mem 2) D0 - D15 (AT91) MCK Data Flo.
39 1745D–ATARM–04-Nov- 05 AT91M55800A Figure 11-18. Early Re ad Protocol with t DF Read Mem 1 Write Mem 1 A0 - A23 NRD NWE NCS1 NCS2 D0 - D15 (Mem 1) D0 - D15 (Mem 2) D0 - D15 (AT91) MCK Data Floa.
40 1745D–ATARM–04-Nov-05 AT91M55800A Figure 11 -19 through Figure 11-25 sho w the timing c ycles and wait sta tes for rea d and writ e access to the various AT91M558 00A external memory devices. The co nfigurations described are as follows: T able 11- 1.
41 1745D–ATARM–04-Nov- 05 AT91M55800A Figure 11-19. 0 Wait St ates, 16-b it Bus Width, Word Transfe r ADDR ADDR+1 B 2 B 1 B 4 B 3 B 4 B 3 B 2 B 1 MCK A1 - A23 NCS NRD D0 - D15 Internal Bus X X B 2.
42 1745D–ATARM–04-Nov-05 AT91M55800A Figure 11-20. 1 Wait State, 16-bit Bus Width, Word Tran sfer ADDR ADDR+1 B 2 B 1 B 4 B 3 X X B 2 B 1 B 4 B 3 B 2 B 1 1 Wait State 1 Wait State MCK A1 - A23 NCS.
43 1745D–ATARM–04-Nov- 05 AT91M55800A Figure 11-21. 1 Wait St ate, 16-bit Bus Width, Half-w ord Transf er B 2 B 1 1 Wait State MCK A1 - A23 NCS NRD D0 - D15 Internal Bus X X B 2 B 1 READ ACCESS ·.
44 1745D–ATARM–04-Nov-05 AT91M55800A Figure 11-22. 0 Wait States, 8-bit Bus Width, Wo rd Transfer ADDR ADDR+1 X B 1 X B 3 B 2 B 1 MCK A0 - A23 NCS NRD D0 - D15 Internal Bus ADDR+2 ADDR+3 X X B 2 B.
45 1745D–ATARM–04-Nov- 05 AT91M55800A Figure 11-23. 1 Wait State, 8-bit Bus Width, Half-word Transf er ADDR X B 1 1 Wait State MCK A0 - A23 NCS NRD D0 - D15 Internal Bus ADDR+1 1 Wait State X X B .
46 1745D–ATARM–04-Nov-05 AT91M55800A Figure 11-24. 1 Wait St ate, 8-bit Bu s Width, Byte Transfer XB 1 1 Wait State MCK A0 - A23 NCS NRD D0-D15 Internal Bus X X X B 1 READ ACCESS · Standard Proto.
47 1745D–ATARM–04-Nov- 05 AT91M55800A Figure 11-25. 0 Wait St ates, 16-b it Bus Width, Byte Transf er MCK A1-A23 NCS NWR1 D0-D15 X B 1 B 2 X ADDR X X X 0 ADDR X X X 0 ADDR X X X 0 ADDR X X X 1 Int.
48 1745D–ATARM–04-Nov-05 AT91M55800A 11.10 EBI User Interface The EBI is programmed using the reg isters listed in the table below. The Remap Control Reg- ister (EBI_RCR) controls ex it from Boot Mode (see Section 11.
49 1745D–ATARM–04-Nov- 05 AT91M55800A 11.10.1 E BI Chip Select Registe r Register Name: EBI_CSR0 - EB I_CSR7 Access Type: Read/Write Reset Value: See Table 11-2 Absolute Address : 0xFFE00000 - 0xFFE0001C • DBW: Data Bus Width • NWS: Number of W ait States This field is valid only if WSE is set.
50 1745D–ATARM–04-Nov-05 AT91M55800A • P A GES: Pa ge Siz e • TDF: Data Float Output Time • BA T : Byt e Access T ype • CSEN: Chip Sele ct Enable (Code Labe l EBI_CSEN ) 0 = Chip select is disabled. 1 = Chip select is enabled. • B A: Base Address (Co de Label EBI_BA ) These bits co ntain the highest bits of the base address.
51 1745D–ATARM–04-Nov- 05 AT91M55800A 11.10.2 EBI Remap Control Register Register Name: EBI_RCR Access Type: Write-only Absolute Address : 0xFFE00020 Offset: 0x20 • RCB: Remap Command Bit (Code Label EBI_RCB ) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the p age zero memory devices.
52 1745D–ATARM–04-Nov-05 AT91M55800A 12. APMC: Ad v anced P o wer Management Cont rolle r The AT91M55800A feat ures an Advanced Power Managem ent Controller, which optimizes both the power consumption of the device and t he complete system.
53 1745D–ATARM–04-Nov- 05 AT91M55800A 12.1 Operating Modes Five operating mode s are supported by the APM C and of fer different power consum ption lev- els and event respon se latency times.
54 1745D–ATARM–04-Nov-05 AT91M55800A Figure 12-2. APMC Block Diagram ARM7TDMI Clock NIRQ NFIQ IDLE MODE FF APMC_SCDR APMC_SCSR MCK (Master Clock) Prescaler Peripheral Clocks Clear Set XIN XOUT MCK.
55 1745D–ATARM–04-Nov- 05 AT91M55800A 12.2 Slow Cloc k Generator The AT91M55800A has a very low power 32 kHz oscillator powered by the backup batt ery voltage supplied on the VDDBU pins. The XIN3 2 and XO UT32 pins must be connected to a 32768 Hz crystal.
56 1745D–ATARM–04-Nov-05 AT91M55800A 12.3 Cloc k Generator The clock generator consists of the main oscillator, the PLL and the clock selection logic with its prescaler. It aim s at selecting the Master Clock, called MCK t hroughout this datasheet.
57 1745D–ATARM–04-Nov- 05 AT91M55800A in APMC_SR and loads the PLL counter with t he value programmed in the PLLCOUNT field. Then, the PLL counter decre ments at each Slow Clock cycle. Note: Programming one in PLLCOUNT is the minimu m allowed and guarantees at least 2 Slo w Clock cycles before the loc k bit is set.
58 1745D–ATARM–04-Nov-05 AT91M55800A Figure 12-6. Clock Switch 12.3.5 Slow Clock Interrupt The APMC also feat ures the Slow Clo ck interrupt, allow ing the user to detect when the Master Clock is actually switched to the Slow Clock.
59 1745D–ATARM–04-Nov- 05 AT91M55800A 12.4 System Cloc k The AT91M55800A has only one system clock: the ARM Core clock. It can be enabled an d disabled by writing to the System Clock Enable (APMC_SCER) and System Clock Disable Registers (APMC_SCDR).
60 1745D–ATARM–04-Nov-05 AT91M55800A Figure 12-7. Shut-down an d Wake-up Fea tures To accommodate the different types of main power supply available, and differ ent signals that can command the sh ut-down of this device, tr i-state, level 0 and level 1 a re user-definable for the Shut-down pin.
61 1745D–ATARM–04-Nov- 05 AT91M55800A 12.8 Fir st Star t-up Sequence At initial startup, or after VDDBU has be en disconnected, the battery-supplie d logic must be initialized.
62 1745D–ATARM–04-Nov-05 AT91M55800A 12.9 APMC User Interface Base Address: 0xFFFF4000 (Code Label APMC_BASE ) T able 12- 1. APMC Memory Map Offset Register Name Access Main Reset Backup Reset 0x0.
63 1745D–ATARM–04-Nov- 05 AT91M55800A 12.9.1 APMC System Clock Enable Register Register Name: APMC_SCER Access Type: Write-only Offset: 0x00 • CPU: System Cloc k Enable Bit 0 = No effect.
64 1745D–ATARM–04-Nov-05 AT91M55800A 12.9.3 APMC System Clock Status Register Register Name: APMC_SCSR Access Type: Read-only Reset Value: 0x 1 Offset: 0x08 • CPU: System Cloc k Status Bit 0 = System Clock is disabled. 1 = System Clock is enabled.
65 1745D–ATARM–04-Nov- 05 AT91M55800A 12.9.5 APMC Perip heral Cloc k Disable Register Register Name: APMC_PCDR Access Type: Write-only Offset: 0x14 • P eripheral Cloc k Disab le (per peripheral) 0 = No effect. 1 = Disables the peripheral clock. 12.
66 1745D–ATARM–04-Nov-05 AT91M55800A 12.9.7 APMC Clock Generator Mode Register Register Name: APMC_CGMR Access Type: Read/Write Reset Value: 0x 0 Offset: 0x20 • MOSCBYP: Main Oscillator Bypass ( Code Label APMC_MOSC_BYP ) 0 = Crystal must be connect ed between XIN and XOUT.
67 1745D–ATARM–04-Nov- 05 AT91M55800A • CSS: Clock Sour ce Selection • OSCOUNT : Main Oscillator Count er Specifies the number of 32,768 Hz divided by 8 clock cycles for the main osc illator start-up timer to count before the main oscillator is stabilized, a fter the os cillator is enabled.
68 1745D–ATARM–04-Nov-05 AT91M55800A 12.9.8 APMC P ower Contr ol Register Register Name: APMC_PCR Access Type: Write-only Offset: 0x28 • SHD ALC: Shut-down or Ala rm Command (Code Label APMC_SHDALC ) 0 = No effect. 1 = Configur es the SHDN p in as defi ned by the field SHDALS in APMC_PMR.
69 1745D–ATARM–04-Nov- 05 AT91M55800A 12.9.9 APMC P ower Mode Regi ster Register Name: APMC_PMR Access Type: Read/Write Backup Rese t Value: 0x1 Offset: 0x2C • SHD ALS: Shut-down or Ala rm Output Selection This field defi nes the state of the SHDAL pin when shut -down or alarm is requested.
70 1745D–ATARM–04-Nov-05 AT91M55800A • WKEDG: W ake-up Input Edge Select ion This field defines the edge to detect on the W ake-up pin (W AKEUP) to provoke a wake-up. WKEDG Wake-up Input Edge Selection Code Label 0 0 None. No edge is dete cted on wake-up .
71 1745D–ATARM–04-Nov- 05 AT91M55800A 12.9.10 APMC Stat us Register Register Name: APMC_SR Access Type: Read-only Offset: 0x30 • MOSCS: Main Oscillator Status (Code Label APMC_MOSCS ) 0 = Main Oscillator outp ut signal is not stabilized or the Main Oscillator is disabled.
72 1745D–ATARM–04-Nov-05 AT91M55800A 12.9.12 APMC Interrupt Disable Register Register Name: APMC_IDR Access Type: Write-only Offset: 0x38 • MOSCS: Main O scillator Interrupt Di sable (Code Label APMC_MOSCS ) 0 = No effect. 1 = Disables the Main Oscillator Stabilized Interrupt.
73 1745D–ATARM–04-Nov- 05 AT91M55800A 13. RTC: Real-time Cloc k The AT91M55800A feat ures a Real-time Clock (RTC) peripheral that is designe d for very low power consumption. It combine s a complete time-of-day clock with alarm and a two-hundred year Gregoria n calendar, complemented by a programmable p eriodic interrupt.
74 1745D–ATARM–04-Nov-05 AT91M55800A 13.2 Functional Description The RTC provides a full Binary-Coded Decimal (B CD) clock which includ es century (19/20), year (with leap year s), month, date, day, hours, minutes and second s. The valid year range is 1900 to 2099, a two-hundred year Gregorian calendar achieving full Y2K compliance.
75 1745D–ATARM–04-Nov- 05 AT91M55800A 6. Hour (BCD chec k, in 24-hour mode chec k range 00 - 23 and chec k that AM/PM flag is not set if R TC is set in 24-Hour mode , in 12-Hour mode chec k range 01 - 12) 7. Minute (c heck BCD and r ange 00 - 59) 8.
76 1745D–ATARM–04-Nov-05 AT91M55800A 13.3 R TC User Interface Base Address: 0xFFFB8000 (Code Label RTC_BASE ) T able 13- 1. RTC Memory Map Offset Register Name Access Reset State 0x0000 Mode Regis.
77 1745D–ATARM–04-Nov- 05 AT91M55800A 13.3.1 RTC Mode Register Register Name :R T C _ M R Access : Read/ Write Offset: 0x00 • UPDTIM: Update Request Time Register (Code Label RTC_UPDTIM ) 0 = Enables the RTC time countin g. 1 = Stops th e RTC time co unting.
78 1745D–ATARM–04-Nov-05 AT91M55800A 13.3.2 RTC Ho ur Mode Register Register Name: RTC_HMR Access Type: Read/Write Reset State: 0x0 Offset: 0x04 • HRMOD: 12/24 Hour Mode 31 30 29 28 27 26 25 24 .
79 1745D–ATARM–04-Nov- 05 AT91M55800A 13.3.3 RTC Time Regist er Register Name: RTC_TIMR Access Type: Read/Write Reset State: 0x0 Offset: 0x08 • SEC: Current Second (Code Label RTC_SEC ) The range that can be set is 0 - 59 (BCD). The lowest four bits encode t he units.
80 1745D–ATARM–04-Nov-05 AT91M55800A 13.3.4 RTC Calendar Register Register Name: RTC_CALR Access Type: Read/Write Reset State: 0x018198 19 Offset: 0x0C • CENT : Current Ce ntury (Code Label RTC_CENT ) The range that can be set is 19 - 20 (BCD). The lowest four bits encode t he units.
81 1745D–ATARM–04-Nov- 05 AT91M55800A 13.3.5 RTC Time Alarm Regi ster Register Name: RTC_TAR Access Type: Read/Write Reset State: 0x0 Offset: 0x10 • SEC: Second Alarm This field is t he alarm fie ld correspo nding to the BCD-coded second cou nter.
82 1745D–ATARM–04-Nov-05 AT91M55800A 13.3.6 RTC Calendar Alarm Regi ster Register Name: RTC_CAR Access Type: Read/Write Reset State: 0x0 Offset: 0x14 • MONTH: Month Alarm This field is the alarm f ield corresponding to the BCD-coded month coun ter.
83 1745D–ATARM–04-Nov- 05 AT91M55800A 13.3.7 RTC Status Re gister Register Name: RTC_SR Access Type: Read-only Reset State: 0x0 Offset: 0x18 • A CKUPD: Acknowledge fo r Update (Code Label RTC_ACKUPD ) 0 = Time and Calendar registers cann ot be updated.
84 1745D–ATARM–04-Nov-05 AT91M55800A 13.3.8 RTC Status Clear Register Register Name: RTC_SCR Access Type: Write-only Offset: 0x1C • A CKUPD: Acknowledge for Update Interrupt Clea r (Code Label RTC_ACKUPD ) 0 = No effect. 1 = Clears Acknowledge fo r Update st atus bit.
85 1745D–ATARM–04-Nov- 05 AT91M55800A 13.3.9 RTC Interrupt Enable Register Register Name: RTC_IER Access Type: Write-only Offset: 0x20 • A CKUPD: Acknowledge Update In terrupt Enable (Code Label RTC_ACKUP D ) 0 = No effect. 1 = The acknowledge for upda te interrupt is enabled.
86 1745D–ATARM–04-Nov-05 AT91M55800A 13.3.10 R TC Interrupt Disable Regis ter Register Name: RTC_IDR Access Type: Write-only Offset: 0x24 • A CKUPD: Acknowledge Update In terrupt Disable (Code Label RTC_ACKUPD ) 0 = No effect. 1 = The acknowledge for upda te interrupt is disabled.
87 1745D–ATARM–04-Nov- 05 AT91M55800A 13.3.11 RTC Interrupt Mask Register Register Name: RTC_IMR Access Type: Read-only Reset State: 0x0 Offset: 0x28 • A CKUPD: Acknow ledg e Update Interrupt Mask (Code Label RTC_ACKUPD ) 0 = The acknowledge for upda te interrupt is disabled.
88 1745D–ATARM–04-Nov-05 AT91M55800A 13.3.12 RTC V ali d Entry R egister Register Name: RTC_VER Access Type: Read-only Reset State: 0x0 Offset: 0x2C • NVT : Non-V alid Time (Code Label RTC_NVT ) 0 = No invalid data has bee n detected in RTC_TI MR.
89 1745D–ATARM–04-Nov- 05 AT91M55800A 14. WD: W atchdog Timer The AT91M55800A has an internal Watchdog Timer that can be used to prevent system lock- up if the software become s trapped in a deadlock. In normal operation the user reloads the watchdog at regular intervals before the timer over- flow occurs.
90 1745D–ATARM–04-Nov-05 AT91M55800A 14.0.1 WD User Inte rface WD Base Address: 0xFFFF8000 (Code La bel WD_BASE ) T able 14- 1. WD Memory Map Offset Register Name Access R eset State 0x00 Overflow.
91 1745D–ATARM–04-Nov- 05 AT91M55800A 14.0.2 WD Overf low Mode Register Name: WD_OMR Access: Read/Write Reset Value: 0 Offset: 0x00 • WDEN: W atc hdog Enable (Code Label WD_WDEN ) 0 = Watchdog is disabled and do es not generate any signals. 1 = Watchdog is enabled and gen erates enabled signals.
92 1745D–ATARM–04-Nov-05 AT91M55800A 14.0.3 WD Clock Mode Register Name: WD_CMR Access: Read/Write Reset Value: 0 Offset: 0x04 • WDCLKS: Cloc k Selection • HPCV : High Pre-load Counter V alue (Code Label WD_HPCV ) Counter is preloaded when watchdog counter is restar ted with bits 0 to 11 set (FFF) and bits 12 to 15 equaling HPCV.
93 1745D–ATARM–04-Nov- 05 AT91M55800A 14.0.4 WD Control Regist er Name: WD_CR Access: Write-only Offset: 0x08 • RSTKEY : Restart Ke y (Code Label WD_RSTKEY ) 0xC071 = Watch Dog counte r is restarted.
94 1745D–ATARM–04-Nov-05 AT91M55800A 14.0.5 WD Status Register Name: WD_SR Access: Read-only Reset Value: 0x 0 Offset: 0x0C • WDO VF: W atchdo g Overflow (Code Label WD_WDOVF ) 0 = No watchdog overflow. 1 = A watchdog overfl ow has occurred since the last restart of the watchdog counter or sin ce internal or external re set.
95 1745D–ATARM–04-Nov- 05 AT91M55800A 15. AIC: Adv anced Interrupt Contr oller The AT91M55800A has a n 8-level priority, individually ma skable, vectored interrupt con troller. This feature substantially reduces the software and real-time overhead in handling internal and external interrupt s.
96 1745D–ATARM–04-Nov-05 AT91M55800A T able 15- 1. AIC Inte rrupt Sourc es Interrupt Sour ce Interrupt Name Interrupt Descri ption 0 FIQ F ast interr upt 1 SWIRQ Software interr upt 2 US0IRQ USART.
97 1745D–ATARM–04-Nov- 05 AT91M55800A 15.1 Hard ware Interrupt V ectoring The hardware interrupt vector ing reduces the numbe r of instructions to reach the interr upt handler to only one.
98 1745D–ATARM–04-Nov-05 AT91M55800A 15.4 Interrupt Masking Each interrupt so urce, includ ing FIQ, can be en abled or disab led using the co mmand regis ters AIC_IECR and AIC_IDCR. The interr upt mask can be read in the Read-only regist er AIC_IMR.
99 1745D–ATARM–04-Nov- 05 AT91M55800A The same mechanism of Spurious Interrupt o ccurs if the ARM7TDMI reads the IVR (applica- tion software o r ICE) when there is no interrupt pend ing.
100 1745D–ATARM–04-Nov-05 AT91M55800A The following table shows the main steps of an interrupt and the order in which they are per- formed according t o the mode: Notes: 1. NIRQ de-asser tion and automatic interru pt cl earing if the source is programmed as le vel sensitive 2.
101 1745D–ATARM–04-Nov- 05 AT91M55800A 15.10 AIC User Interface Base Address: 0xFFFFF000 (Code L abel AIC_BASE ) Note: 1. The reset value of this register depends on the le vel of the Externa l IRQ lines. All other sources are cleared at reset. T able 15- 2.
102 1745D–ATARM–04-Nov-05 AT91M55800A 15.10.1 AIC Sour ce Mode Regist er Register Name: AIC_SMR0...AIC_SMR31 Access Type: Read/Write Reset Value: 0 • PRIOR: Priority Le vel (Code Label AIC_PRIOR ) Program the prior ity level for all sources ex cept source 0 (FIQ) .
103 1745D–ATARM–04-Nov- 05 AT91M55800A 15.10.2 AIC Sour ce V ector Register Register Name: AIC_SVR0..AIC _SVR31 Access Type: Read/Write Reset V alue: 0 • VECT OR: Interrupt Handler Addre ss The user may store in these register s the addresses of the corresponding handler f or each interrupt source.
104 1745D–ATARM–04-Nov-05 AT91M55800A 15.10.4 A IC FIQ V ector Regi ster Register Name: AIC_FVR Access Type: Read-only Reset V alue: 0 Offset: 0x104 • FIQV : FIQ V ector Register The FIQ Vector Re gister contains the vector programmed by th e use r in the Source Vector Register 0 which corresponds to FIQ.
105 1745D–ATARM–04-Nov- 05 AT91M55800A 15.10.6 AIC I nterrupt P ending Register Register Name: AIC_IPR Access Type: Read-only Reset V alue: Undefined Offset: 0x10C • Interrupt P ending 0 = Corresponding inter rupt is inactive. 1 = Corresponding inter rupt is pending.
106 1745D–ATARM–04-Nov-05 AT91M55800A 15.10.8 AIC Core I nterrupt Status Regist er Register Name: AIC_CISR Access Type: Read-only Reset V alue: 0 Offset: 0x114 • NFIQ: NFIQ Status (Code Label AIC_NFIQ ) 0 = NFIQ line inactive. 1 = NFIQ line active.
107 1745D–ATARM–04-Nov- 05 AT91M55800A 15.10.10 AIC Interrupt Dis able Command Regist er Register Name: AIC_IDCR Access T ype: Write-only Offset: 0x124 • Interrupt Disab le 0 = No effect.
108 1745D–ATARM–04-Nov-05 AT91M55800A 15.10.12 AIC Interrupt Set Command Regi ster Register Name: AIC_ISCR Access T ype: Write-only Offset: 0x12C • Interrupt Set 0 = No effect.
109 1745D–ATARM–04-Nov- 05 AT91M55800A 15.10.14 AIC Spurious V ector Register Register Name: AIC_SPU Access Type: Read/Write Reset Value: 0 Offset: 0x134 • SPUVEC: Spurious Interrupt V ector Handler Address The user may store the addr ess of the Spurious Interrupt ha ndler in this register.
110 1745D–ATARM–04-Nov-05 AT91M55800A 15.11 Standard Interrupt Sequence It is assumed that: • The Advanced Interr upt C ontroller has been programmed, AIC_SVR are lo aded with corresponding inte rr upt service routine addresses and interrupts are en abled.
111 1745D–ATARM–04-Nov- 05 AT91M55800A masking or unmasking the inte rr upts depending on the st ate sav ed in the SPSR (the pre vious state of the ARM Core) . Note: The I bit in the SPSR is signif icant. If it is set, it indicates t hat the ARM Core w as just about to mask IRQ interrupts when the mask instructio n was interrupted.
112 1745D–ATARM–04-Nov-05 AT91M55800A 16. PIO: P arallel I/O Contr oller The AT91M558 00A has 58 progr ammable I/O lines. 1 3 pins are dedicated as general-pur pose I/O pins. The othe r I/O lines are multiplex ed with an external signal of a peripheral to op timize the use of available packa ge pins.
113 1745D–ATARM–04-Nov- 05 AT91M55800A can be selected whether the pin is used for its peripher al function or as a parallel I/O line. The register PIO_IFSR (Input Filter Status) indicate s whether or not the filter is activated for each pin.
114 1745D–ATARM–04-Nov-05 AT91M55800A Figure 16-1. Parallel I/O Multiplexed wit h a Bi-directional Signal Note: 1. See “ Section 16.8 ”PIO Connection Table s” .
115 1745D–ATARM–04-Nov- 05 AT91M55800A 16.8 PIO Connection T ables Note: 1. The OFF value is the def ault lev el seen on the per ipheral input when the PIO line is enabled.
116 1745D–ATARM–04-Nov-05 AT91M55800A Note: 1. The OFF value is the def ault lev el seen on the per ipheral input when the PIO line is enabled. T able 16- 2.
117 1745D–ATARM–04-Nov- 05 AT91M55800A 16.9 PIO User Interface PIO Control ler A Base Address: 0xFFFEC000 (Cod e Label PIOA_BASE ) PIO Control ler B Base Address: 0xFFFF000 0 (Code Label PIOB_BASE ) Notes: 1. The reset value of this register depends on the lev el of the e xter nal pins at reset.
118 1745D–ATARM–04-Nov-05 AT91M55800A 16.9.1 PIO Enable Register Register Name: PIO_PE R Access Type: Write-only Offset: 0x00 This register is used to enable individual pins to be contr o lled by the PIO Controller instea d of the associated peripheral.
119 1745D–ATARM–04-Nov- 05 AT91M55800A 16.9.3 PIO St atus Regi ster Register Name: PIO_PS R Access Type: Read-onlyRead-only Offset: 0x08 Reset Value: 0x3FFFFFFF (A) 0x0FFFFFFF (B) This register indicates which pins are enabled for PIO cont rol. T his register is updated when PIO lines a re enabled or disabled.
120 1745D–ATARM–04-Nov-05 AT91M55800A 16.9.5 PIO O utput D isable Regist er Register Name: PIO_ODR Access Type: Write-only Offset: 0x14 This register is used to disable PIO out put drivers. If the pin is driven by the peripheral, this has no e ffect on the pin, but the information is stored.
121 1745D–ATARM–04-Nov- 05 AT91M55800A 16.9.7 PIO Input Filter Enable Register Register Name: PIO_IFER Access Type: Write-only Offset: 0x20 This register is used to ena ble input glitch filters. It affects the pin whe ther or not the PIO is enabled .
122 1745D–ATARM–04-Nov-05 AT91M55800A 16.9.9 PIO I nput Filter Status Register Register Name: PIO_IFSR Access Type: Read-only Offset: 0x28 Reset Value: 0 This register indica tes which pins have glitch filters selected. It is updated when PIO output s are enabled or disabled by writing to PIO_IF ER or PIO_IFDR.
123 1745D–ATARM–04-Nov- 05 AT91M55800A 16.9.11 PIO C lear Output Data Register Register Name: PIO_CODR Access Type: Write-only Offset: 0x34 This register is used to clear PIO ou tput data. It af fects the pin only if the corresponding PI O output line is enab led and if the pin is controlled by the PIO.
124 1745D–ATARM–04-Nov-05 AT91M55800A 16.9.13 PIO Pin Data Status R egister Register Name: PIO_PDSR Access Type: Read-only Offset: 0x3C Reset Value: Undefined This register shows t he state of the physical pin of the ch ip. The pin values are always valid, regardless of whether the pins are enabled as PIO, peri pheral, input or output.
125 1745D–ATARM–04-Nov- 05 AT91M55800A 16.9.15 PIO Interrupt D isable Register Register Name: PIO_IDR Access Type: Write-only Offset: 0x44 This register is used to di sable PIO interrupts on the co rresponding pin. It has effect whether the PIO is enabl ed or not.
126 1745D–ATARM–04-Nov-05 AT91M55800A 16.9.17 PIO Interrupt S tatus Regist er Register Name: PIO_ISR Access Type: Read-only Offset: 0x4C Reset Value: 0 This register indicates for ea ch pin when a logic value change has been dete cted (rising or falling edge).
127 1745D–ATARM–04-Nov- 05 AT91M55800A 16.9.19 PIO Mult i-driver Disable Regi ster Register Name: PIO_MDDR Access Type: Write-only Offset: 0x54 This register is used to disa ble the open drain configuratio n of the output buffer. 1 = Disables the multi-dr iver option on the corresponding pin.
128 1745D–ATARM–04-Nov-05 AT91M55800A 17. SF: Special Function Register s The AT91M55800A provides reg isters which implement the following sp ecial functions. • Chip identification • RESET status 17.1 Chip Identifier The following chip identifie r values are covered in this datasheet: 17.
129 1745D–ATARM–04-Nov- 05 AT91M55800A 17.2.1 Chip ID Regis ter Register Name: SF_CIDR Access Type: Read-only Offset: 0x00 • VERSION: V er sion of the chip (Code Label SF_VERSION ) This value is incremented by one with each new version of the chip (f rom zero to a maximum value of 31).
130 1745D–ATARM–04-Nov-05 AT91M55800A • ARCH: Chip Architecture Code of Architecture: Two BCD d igits • NVPTYP: Non v olatile Program Memory T ype Note: All other codes are reser ved.
131 1745D–ATARM–04-Nov- 05 AT91M55800A 17.2.3 Reset Status Register Register Name: SF_RSR Access Type: Read-only Offset: 0x08 • RESET : Reset Status Information This field indicates whet her the reset was demanded by the e xternal system (via NRST) or by the Watchdo g internal reset request.
132 1745D–ATARM–04-Nov-05 AT91M55800A 18. USAR T : Univer sal Synchr onous/ Asynchr onous Receiver/T ransmitter The AT91M55800AA provide s three identical, full-d uplex, universal synchronou s/asynchro- nous receiver /transmitters w hich are connec ted to the Periphe ral Data Controlle r.
133 1745D–ATARM–04-Nov- 05 AT91M55800A 18.1 Pin Description Notes: 1. After a hardware reset, the USART cloc k is disabled by def ault. The user must configur e the P ower Management Controller bef ore any access to the User Interface of the USAR T .
134 1745D–ATARM–04-Nov-05 AT91M55800A 18.2 Baud Rate Generator The Baud Rate Generator provides the bit period clock (the Baud Rate clock) to both the Receiver and the Transmitter. The Baud Rate Generat or can select between external an d internal clock sources.
135 1745D–ATARM–04-Nov- 05 AT91M55800A 18.3 Receiver 18.3.1 Asynchr onous Receiver The USART is configured for asynchronous oper ation when SYNC = 0 (bit 7 of US_MR). In asynchronous mode, the USART detects the start of a received character by sampling the RXD signal until it detects a valid start bit.
136 1745D–ATARM–04-Nov-05 AT91M55800A 18.3.2 Synchr onous Receiver When configured fo r synchronous operation (SYNC = 1) , the receiver samples the RXD signal on each rising edge of the Baud Rate clock. If a low level is detected, it is considered as a start.
137 1745D–ATARM–04-Nov- 05 AT91M55800A 18.4 T ransmitter The transmitter ha s the same behavio r in both synchrono us and asynchronous ope rating modes. Start bi t, data bits, parity b it and stop bits are ser ially shifted, lowest significa nt bit first, on the falling edge of the serial clock.
138 1745D–ATARM–04-Nov-05 AT91M55800A 18.6 Break A break condition is a low signal level which has a duration of at least one char acter (including start/stop b its and p arity). 18.6.1 T ransmit Break The transmitter generates a break condition on th e TXD line when STTBRK is set in US_CR (Control Register).
139 1745D–ATARM–04-Nov- 05 AT91M55800A The standa rd break transmission sequen ce is: 1. W ait for the transmitter ready (US_CSR.TXRD Y = 1) 2. Send the STTBRK command (write 0x0200 to US_CR) 3. W ait f or the transmitter rea dy (bit TXRD Y = 1 in US_CSR) 4.
140 1745D–ATARM–04-Nov-05 AT91M55800A 18.7 P eripheral Data Controller Each USART channel is closely connected to a corresponding Peripheral Data Controller channel. One is dedicated to the receiver. The other is dedicated t o the transmitter. Note: The PDC is disabled if 9-bit char acter length is selected (MODE9 = 1) in US_MR.
141 1745D–ATARM–04-Nov- 05 AT91M55800A Figure 18-7. Channel Modes Receiver Transmitter Disabled RXD TXD Receiver Transmitter Disabled RXD TXD V DD Disabled Receiver Transmitter Disabled RXD TXD Di.
142 1745D–ATARM–04-Nov-05 AT91M55800A 18.10 USART User Interface Base Address USART0: 0xFFFC0000 (Code La bel USART0_BASE ) Base Address USART1: 0xFFFC4000 (Code La bel USART1_BASE ) Base Address USART2: 0xFFFC8000 (Code Label USART2_BASE ) T able 18- 2.
143 1745D–ATARM–04-Nov- 05 AT91M55800A 18.10.1 USAR T Contr ol Register Name: US_CR Access Type: Write-only Offset: 0x00 • RSTRX: Reset Receiv er (Code Label US_RSTRX ) 0 = No effect. 1 = The receiver logic is reset. • RSTTX: Rese t T ransmitte r (Code Label US_RSTTX ) 0 = No effect.
144 1745D–ATARM–04-Nov-05 AT91M55800A • STTT O: Start Time-out (Code Label US_STTTO ) 0 = No effect. 1 = Start waiting for a cha racter before clocking the time-out count er. • SEND A: Send Addre ss (Code Label US_SENDA ) 0 = No effect. 1 = In Multi-drop Mode only, th e next character written to the US_ THR is sent with the address bit set.
145 1745D–ATARM–04-Nov- 05 AT91M55800A 18.10.2 USAR T Mode Regi ster Name: US_MR Access Type: Read/Write Reset State: 0 Offset: 0x04 • USCLKS: Cloc k Selection (Baud Rate Generator Input Cloc k) • CHRL: Character Len gth Start, stop and parity bits are added to the character length.
146 1745D–ATARM–04-Nov-05 AT91M55800A • NBST OP: Number of Stop Bits The interpretat ion of the number of stop bit s depends on SYNC. • CHMODE: Channel Mode • MODE9: 9-Bit Characte r Length (Code Label US_MODE9 ) 0 = CHRL defines character lengt h.
147 1745D–ATARM–04-Nov- 05 AT91M55800A 18.10.3 USART Interrupt Enable Regi ster Name: US_IER Access Type: Write-only Offset: 0x08 • RXRD Y : Enab le RXRD Y Interrupt (Code Label US_RXRDY ) 0 = No effect. 1 = Enables RXRDY Interrupt. • TXRD Y : Enable TXRD Y Interrupt (Code Label US_TXRDY ) 0 = No effect.
148 1745D–ATARM–04-Nov-05 AT91M55800A 18.10.4 USAR T Interr upt Disable Regist er Name: US_IDR Access Type: Write-only Offset: 0x0C • RXRD Y : Disable RXRD Y Interrupt (Code Label US_RXRDY ) 0 = No effect. 1 = Disables R XRDY Interr upt. • TXRD Y : Disable TXRD Y Interrupt (Code Label US_TXRDY ) 0 = No effect.
149 1745D–ATARM–04-Nov- 05 AT91M55800A 18.10.5 USAR T Interr upt Mask Register Name: US_IMR Access Type: Read-only Reset Value: 0x0 Offset: 0x10 • RXRD Y : RXRD Y Interrupt Mask (Code Label US_RXRDY ) 0 = RXRDY Interrupt is Disabled. 1 = RXRDY Inte rrupt is Enab led.
150 1745D–ATARM–04-Nov-05 AT91M55800A 18.10.6 USAR T Channel Status Register Name: US_CSR Access Type: Read-only Reset: 0x18 Offset: 0x14 • RXRD Y : Receiver Read y (Code Label US_RXRDY ) 0 = No complete character has been r eceived since the la st read of the US_RHR or the receiver is disabled.
151 1745D–ATARM–04-Nov- 05 AT91M55800A • TIMEOUT : Receiver Time-out (Code Lab el US_TIMEOUT ) 0 = There has not been a time- out since the last “Start Time -out” command or the Time-o ut Register is 0. 1 = There has been a time-out since the last “Start Time-ou t” command.
152 1745D–ATARM–04-Nov-05 AT91M55800A 18.10.7 USART Receiver Hold ing Register Name: US_RHR Access Type: Read-only Reset State: 0 Offset: 0x18 • RXCHR: Received Character Last character received if RXRDY is set. Whe n number of data bits is le ss than 9 b its, the bits a re right-alig ned.
153 1745D–ATARM–04-Nov- 05 AT91M55800A 18.10.9 U SART Baud Rate Generator Regi ster Name: US_BRGR Access Type: Read/Write Reset State: 0 Offset: 0x20 • CD: Cloc k Divisor This register has no effect if Synchronous Mode is selected with an external clock.
154 1745D–ATARM–04-Nov-05 AT91M55800A 18.10.10 USART Receiver Time-out Register Name: US_RTOR Access Type: Read/Write Reset State: 0 Offset: 0x24 • T O: Time-out V alue When a value is writte n to this register, a Start Time -out Command is automati cally performed.
155 1745D–ATARM–04-Nov- 05 AT91M55800A 18.10.12 USART Receive P ointer Regi ster Name: US_RPR Access Type: Read/Write Reset State: 0 Offset: 0x30 • RXPTR: Receive P ointer RXPTR must be loaded with the add ress of the receive buff er.
156 1745D–ATARM–04-Nov-05 AT91M55800A 18.10.14 USART T ransmit P ointer Re gister Name: US_TPR Access Type: Read/Write Reset State: 0 Offset: 0x38 • TXPTR: T ransmit P oint er TXPTR must be loaded with the address of the transmit buf fer. 18.10.
157 1745D–ATARM–04-Nov- 05 AT91M55800A 19. TC: Timer Counte r The AT91M55800A features two Ti mer Counter Blocks, each containing three identical 16-bit timer counter channels.
158 1745D–ATARM–04-Nov-05 AT91M55800A Figure 19-1. TC Block Diagr am Timer Counter Channel 0 Timer Counter Channel 1 Timer Counter Channel 2 SYNC Parallel IO Controller TC1XC1S TC0XC0S TC2XC2S INT.
159 1745D–ATARM–04-Nov- 05 AT91M55800A 19.1 Signal Name Description Notes: 1. After a hardware reset, the TC cloc k is disabled b y default ( See “APMC: Advanced Power Management Controller” on page 52. ). The user must configure the P o wer Management Contro ller before any access to the User Interface of the TC .
160 1745D–ATARM–04-Nov-05 AT91M55800A 19.2 Timer Counter Description Each Timer Counter channel is identical in operation. The register s for channel programming are listed in Table 19 -1 on page 159 . 19.2.1 Counter Each Timer Counte r channel is organized aroun d a 16-bit counter.
161 1745D–ATARM–04-Nov- 05 AT91M55800A 19.2.3 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled /disabled and started/stopped . • The clock can be enabled or disabled by the user with the CLKEN and t he CLKDIS commands in the Control Reg ister .
162 1745D–ATARM–04-Nov-05 AT91M55800A • Softw are T rigger : Each channel has a software trigger , av ailable b y setting SWTRG in TC_CCR. • SYNC: Each channel has a synchroniza tion signal SYNC. When asser ted, this signal has the same eff ect as a softw are trigger .
163 1745D–ATARM–04-Nov- 05 AT91M55800A 19.3 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Chan nel Mode Register). Capture Mode allows the T C Channel to perf o rm measurements such as pulse timing, fre- quency, period , duty cycle and phase on TIOA and TIOB signals which are considered as input.
164 1745D–ATARM–04-Nov-05 AT91M55800A Figure 19-4. Capture Mod e MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024 XC0 XC1 XC2 TCCLKS CLKI QS R S R Q CLKSTA CLKEN CLKDIS BURST TIOB Register C Capture Register A.
165 1745D–ATARM–04-Nov- 05 AT91M55800A 19.4 W avef orm Operating Mode This mode is entered by setti ng the WAVE parameter in TC_CMR (Channel Mode Register).
166 1745D–ATARM–04-Nov-05 AT91M55800A The tables below show which parameter in TC_CMR is used to define the effect of each event. If two or m ore events occur at the same time, t he priority le vel is defined a s follows: 1. Software tr igger 2. Exter nal e vent 3.
167 1745D–ATARM–04-Nov- 05 AT91M55800A Figure 19-5. Waveform Mo de MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024 XC0 XC1 XC2 TCCLKS CLKI QS R S R Q CLKSTA CLKEN CLKDIS CPCDIS BURST TIOB Register A Register .
168 1745D–ATARM–04-Nov-05 AT91M55800A 19.5 TC User Interface TC Block 0 Base Address: 0xFFFD000 0 (Code Label TCB0_BASE ) TC Block 1 Base Address: 0xFFFD400 0 (Code Label TCB1_BASE ) TC_BCR (Block Control Register) and TC_BMR (Block M ode Register) control the TC block.
169 1745D–ATARM–04-Nov- 05 AT91M55800A 19.5.1 TC Block Cont rol Register Register Name: TC_BCR Access Type: Write-only Offset: 0xC0 • SYNC: Synchr o Command (Code Lab el TC_SYNC ) 0 = No effect. 1 = Asserts the SYNC signal which genera tes a software trigger simultaneously for each of the channels.
170 1745D–ATARM–04-Nov-05 AT91M55800A 19.5.2 TC Block Mo de Register Register Name: TC_BMR Access Type: Read/Write Reset State: 0 Offset: 0xC4 • TC0XC0S: External Clo ck Signal 0 Selecti on • .
171 1745D–ATARM–04-Nov- 05 AT91M55800A 19.5.3 TC Channel Contr ol Register Register Name: TC_CCR Access Type: Write-only Offset: 0x00 • CLKEN: Counter Cloc k Enable Command (Code Label TC_CLKEN ) 0 = No effect. 1 = Enables the clock if CLKDIS is not 1.
172 1745D–ATARM–04-Nov-05 AT91M55800A 19.5.4 TC Channel Mode Register: Capt ure Mode Register Name: TC_CMR Access Type: Read/Write Reset State: 0 Offset: 0x04 • TCCLKS: Clock Selection • CLKI: Cloc k In ver t (Code Label TC_CLKI ) 0 = Counter is increm ented on r ising edge o f the cloc k.
173 1745D–ATARM–04-Nov- 05 AT91M55800A • ETRGEDG: External T rigger Edge Selection • ABETRG: TIO A or TIOB External T rigg er Selection • CPCTRG: RC Compare T rigger Enable (Code Labe l TC_CPCTRG ) 0 = RC Compare has no effect on the counter and its clock.
174 1745D–ATARM–04-Nov-05 AT91M55800A 19.5.5 TC Channel Mode Register: W a veform Mode Register Name: TC_CMR Access Type: Read/Write Reset State: 0 Offset: 0x4 • TCCLKS: Clock Selection • CLKI: Cloc k In ver t (Code Label TC_CLKI ) 0 = Counter is increm ented on r ising edge o f the cloc k.
175 1745D–ATARM–04-Nov- 05 AT91M55800A • EEVTEDG: External Ev ent Edge Selection • EEVT : External Event Selection Note: If TIOB is chosen as the e xter nal ev ent signal, it is configured as an input an d no longer generates wa vef or ms.
176 1745D–ATARM–04-Nov-05 AT91M55800A • AEEVT : External Event Effect on TIO A • ASWTRG: Soft ware T rigge r Effect on TIO A • BCPB: RB Compare Effect on TIOB • BCPC: RC Compare Effect on .
177 1745D–ATARM–04-Nov- 05 AT91M55800A • BSWTRG: Soft ware T rigge r Effect on TIOB BSWTRG Eff ect Code Label: TC_BSWTRG 0 0 None TC_BSWTRG_OUTPUT_NONE 0 1 Set TC_BSWTRG_SET_OUTPUT 1 0 Clear TC_.
178 1745D–ATARM–04-Nov-05 AT91M55800A 19.5.6 TC Counter V alue Register Register Name: TC_CVR Access Type: Read-only Reset State: 0 Offset: 0x10 • CV : Counter V alue (Code Label TC_CV ) CV contains the counter value in re al-time.
179 1745D–ATARM–04-Nov- 05 AT91M55800A 19.5.8 TC Register B Register Name: TC_RB Access Type: Read-only if WAVE = 0, Read/Write if WAVE = 1 Reset State: 0 Offset: 0x18 • RB: Register B (Code Label TC_RB ) RB contains the Register B value in real-time .
180 1745D–ATARM–04-Nov-05 AT91M55800A 19.5.10 TC Status Register Register Name: TC_SR Access Type: Read/Write Offset: 0x20 • CO VFS: Count er Overflow Status (Cod e Label TC_COVFS ) 0 = No counter overflow ha s occurred since the last read of the Statu s Register.
181 1745D–ATARM–04-Nov- 05 AT91M55800A • MTIOB: TIOB Mirror (Code Label TC_MTIOB ) 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this mean s that TIOB pin is high.
182 1745D–ATARM–04-Nov-05 AT91M55800A 19.5.11 TC Interrupt Enable Register Register Name: TC_IER Access Type: Write-only Offset: 0x24 • CO VFS: Co unter Overflow (Code La bel TC_COVFS ) 0 = No effect. 1 = Enables the Counter Overflow Interrupt. • LO VRS: Load Overrun (Code La bel TC_LOVRS ) 0 = No effect.
183 1745D–ATARM–04-Nov- 05 AT91M55800A 19.5.12 TC Interrup t Disable Regist er Register Name: TC_IDR Access Type: Write-only Offset: 0x28 • CO VFS: Co unter Overflow (Code La bel TC_COVFS ) 0 = No effect. 1 = Disables the Coun ter Overflow Interrupt.
184 1745D–ATARM–04-Nov-05 AT91M55800A 19.5.13 TC Interrupt Mask Register Register Name: TC_IMR Access Type: Read-only Reset State: 0 Offset: 0x2C • CO VFS: Co unter Overflow (Code La bel TC_COVFS ) 0 = The Coun ter Overflow Interrupt is disabled.
185 1745D–ATARM–04-Nov- 05 AT91M55800A 20. SPI: Serial P eripheral Interface The AT91M55800A includes an SPI which provides communication with external devices in master or slave mode. The SPI has four exter nal chip selects which can be connected to up to 15 devices.
186 1745D–ATARM–04-Nov-05 AT91M55800A Notes: 1. After a hardware reset, the SPI clock is disabled by de f ault. The u ser must configure the P ow er Management Controller bef ore any access to the User Interface of the SPI. 2. After a hardware reset, the SPI pi ns are deselected b y default (see Section 16.
187 1745D–ATARM–04-Nov- 05 AT91M55800A 20.2.2 V ariable Peripheral Select Variable Peripheral Select is act ivated by setting bit PS to o ne. The PCS field in SP_TDR (Transmit Data Register ) is used to select the destinat ion peripheral.
188 1745D–ATARM–04-Nov-05 AT91M55800A Figure 20-1. Functional Flow Diag ram in Master Mode SPI Enable TDRE PS 1 0 0 1 1 1 0 Same P eripheral New P eripheral NPCS = SP_TDR(PCS) NPCS = SP_MR(PCS) De.
189 1745D–ATARM–04-Nov- 05 AT91M55800A Figure 20-2. SPI in Master Mode 0 1 SP_MR(MCK32) MCK MCK/32 SPCK Clock Generator SP_CSRx[15:0] S R Q M O D F T D R E R D R F O V R E S P I E N S 0 1 SP_MR(PS.
190 1745D–ATARM–04-Nov-05 AT91M55800A 20.3 Slave Mode In Slave Mode, th e SPI waits for NSS to go active low before receiving the se rial clock from a n external maste r. In slave mode CPOL, NCPHA and BITS fields of SP_CSR0 are used to define the transfer characteristics.
191 1745D–ATARM–04-Nov- 05 AT91M55800A 20.4 Data T ransfer The following waveforms show examples of data transfers. Figure 20-3. SPI Transfer Format (NCPHA equals One, 8 bits per tra nsfer) Figure 20-4.
192 1745D–ATARM–04-Nov-05 AT91M55800A Figure 20-5. Programmab le Delays (DLY B CS, DLYBS and DLYBCT) 20.5 Cloc k Generation In master mode the SPI Master Clock is either MCK or MCK/32, as defined by the MCK32 field of SP_MR. The SPI baud rate clock is generated by dividin g the SPI Master Clock by a value between 4 and 5 10.
193 1745D–ATARM–04-Nov- 05 AT91M55800A 20.7 SPI Programmer’ s Model SPI Base Address: 0xFFFBC000 (Code Label SPI_BASE ) T able 20- 1. SPI Memory Map Offset Register Name Access Reset State 0x00 .
194 1745D–ATARM–04-Nov-05 AT91M55800A 20.7.1 SPI Control Regi ster Register Name: SP_CR Access Type: Write-only Offset: 0x00 • SPIEN: SPI Enable (Code Label SP_SPIEN ) 0 = No effect. 1 = Enables the SPI to transf er and receive data. • SPIDIS: SPI Disable (Code Label SP_SPIDIS ) 0 = No effect.
195 1745D–ATARM–04-Nov- 05 AT91M55800A 20.7.2 SPI Mode Register Register Name: SP_MR Access Type: Read/Write Reset State: 0 Offset: 0x04 • MSTR: Master/Sla ve Mode (Code Label SP_MSTR ) 0 = SPI is in Slave mode. 1 = SPI is in Master mo de. MSTR configur es the SPI Interfa ce for either mast er or slave mode oper ation.
196 1745D–ATARM–04-Nov-05 AT91M55800A • PCS: P eripheral Chip Select (Code Label SP_PCS ) This field is only used if Fixed Peripheral Select is active (PS=0).
197 1745D–ATARM–04-Nov- 05 AT91M55800A 20.7.3 SPI Receiv e Data Register Register Name: SP_RDR Access Type: Read-only Reset State: 0 Offset: 0x08 • RD: Receive Data (Code Label SP_RD ) Data received by the SPI In terface is sto red in this register righ t-justified.
198 1745D–ATARM–04-Nov-05 AT91M55800A 20.7.4 SPI T ra nsmit Data Register Register Name: SP_TDR Access Type: Write-only Offset: 0x0C • TD: T ransmit Data ( Code Label SP_TD ) Data which is to be trans mitted by the SPI Inte rface is store d in this register.
199 1745D–ATARM–04-Nov- 05 AT91M55800A 20.7.5 SPI Status Register Register Name: SP_SR Access Type: Read-only Reset State: 0 Offset: 0x10 • RDRF: Receive Da ta Register Full (Code Label SP_RDRF ) 0 = No dat a has been received sin ce the last read o f SP_RDR.
200 1745D–ATARM–04-Nov-05 AT91M55800A 20.7.6 SPI Interrupt Enable Regi ster Register Name: SP_IER Access Type: Write-only Offset: 0x14 • RDRF: Receive Da ta Register Full Interrupt Enable (Co de Label SP_RDRF ) 0 = No effect. 1 = Enables the Receive r Data Register Full Interrupt.
201 1745D–ATARM–04-Nov- 05 AT91M55800A 20.7.7 SPI Interrupt Disable Register Register Name: SP_IDR Access Type: Write-only Offset: 0x18 • RDRF: Receive Da ta Register Full Interrupt Disab le (Code Label SP_RDRF ) 0 = No effect. 1 = Disables t he Receiver Da ta Register Full Inte rrupt.
202 1745D–ATARM–04-Nov-05 AT91M55800A 20.7.8 SPI Interrupt Mask Register Register Name: SP_IMR Access Type: Read-only Reset State: 0 Offset: 0x1C • RDRF: Receive Da ta Register Full Interrupt Mask (Code Lab el SP_RDRF ) 0 = Receive Data Register Full Interrupt is disabled.
203 1745D–ATARM–04-Nov- 05 AT91M55800A 20.7.9 SPI Receiv e P ointer Register Name: SP_RPR Access Type: Read/Write Reset State: 0 Offset: 0x20 • RXPTR: Receive P ointer RXPTR must be loaded with the add ress of the receive buff er.
204 1745D–ATARM–04-Nov-05 AT91M55800A 20.7.11 SPI T ra nsmit P ointe r Register Name: SP_TPR Access Type: Read/Write Reset State: 0 Offset: 0x28 • TXPTR: T ransmit P oint er TXPTR must be loaded with the address of the transmit buf fer.
205 1745D–ATARM–04-Nov- 05 AT91M55800A 20.7.13 SPI Chip Select R egister Register Name: SP_CSR0.. SP_CSR3 Access Type: Read/Write Reset State: 0 Offset: 0x30......0x3C • CPOL: Cloc k P olarity (Code Label SP_CPOL ) 0 = The inactive state value of SPCK is logic level zero.
206 1745D–ATARM–04-Nov-05 AT91M55800A • SCBR: Serial Clock Ba ud Rate (Code Label SP_SCBR ) In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the SPI Maste r Clock (selected between MCK and MCK/32). The Baud rate is selected by writing a value from 2 to 255 in the field SCBR.
207 1745D–ATARM–04-Nov- 05 AT91M55800A 21. ADC: Analog-to-digital Con verter The AT91M55800A features two identical 4-cha nnel 10-bit Analog-to-d igital converters (ADC) based on a Successive Approximatio n Register (SAR) approach.
208 1745D–ATARM–04-Nov-05 AT91M55800A 21.0.1 Analog-to-digital Con version The ADC has an internal sample-and-hold cir cuit that holds the sampled analog value during a complete conversion. The reference voltag e pin ADVREF allows the analog input conver sion range to be set between 0 a nd ADVREF.
209 1745D–ATARM–04-Nov- 05 AT91M55800A the enabled channe l. When all conversions are complete, the ADC is deactiva ted until the next trigger. This permits an automatic conver sion sequence with minimum CPU inte rvention and opti- mized power con sumption.
210 1745D–ATARM–04-Nov-05 AT91M55800A 21.0.5 ADC Us er Interface Base Address ADC 0: 0xFFFB0000 (Code Label ADC0_BASE ) Base Address ADC 1: 0xFFFB4000 (Code Label ADC1_BASE ) T able 21- 2.
211 1745D–ATARM–04-Nov- 05 AT91M55800A 21.0.6 ADC Control Register Register Name: ADC_CR Access Type: Write-only Offset: 0x00 • SWRST : Software Re set (Code Label ADC_SWRST ) 0 = No effect. 1 = Resets the ADC simulatin g a hardware reset. • ST ART : Start Con version (Code Label ADC_START ) 0 = No effect.
212 1745D–ATARM–04-Nov-05 AT91M55800A 21.0.7 ADC M ode Register Register Name: ADC_MR Access Type: Read/Write Reset State: 0 Offset: 0x04 • TRGEN: T rigger Enable . • TRGSEL: T rigger Se lection This field selects th e hardware trigger. • RES: Resolution.
213 1745D–ATARM–04-Nov- 05 AT91M55800A • SLEEP: Sleep Mode • PRESCAL: Prescaler Rate Selection ( ADC_PRESCAL ) This field define s the conversion clock in function of the Master Clock (MCK): The ADC clock range is betwe en MCK/2 (PRESCAL = 0) and M CK /128 (PRESCAL = 63).
214 1745D–ATARM–04-Nov-05 AT91M55800A 21.0.8 ADC Cha nnel Enable Regis ter Register Name: ADC_CHER Access Type: Write-only Offset: 0x10 • CH: Channel Enab le (Code Label ADC_CHx ) 0 = No effect.
215 1745D–ATARM–04-Nov- 05 AT91M55800A 21.0.10 ADC Channel Status Register Register Name: ADC_CHSR Access Type: Read-only Reset State: 0 Offset: 0x18 • CH: Channel Status (Code Label ADC_CHx ) 0 = Corresponding c han nel is disabled. 1 = Corresponding channel is ena bled.
216 1745D–ATARM–04-Nov-05 AT91M55800A 21.0.12 ADC Interrupt Enable Registe r Register Name: ADC_IER Access Type: Write-only Offset: 0x24 • EOC: End of Con version Interrupt Enab le (Code Label ADC_EOCx ) 0 = No effect. 1 = Enables the End of Conversion Interrupt .
217 1745D–ATARM–04-Nov- 05 AT91M55800A 21.0.14 ADC Interrupt M ask Register Register Name: ADC_IMR Access Type: Read-only Reset State: 0 Offset: 0x2C • EOC: End of Con version Int errupt Mask (Code Label ADC_EOCx ) 0 = End of Conversi on Interrupt is disabled.
218 1745D–ATARM–04-Nov-05 AT91M55800A 22. D A C: Digital-to-analog Con verter The AT91M55800A features two ident ical 1-channe l 10-bit Digital-to-analog converters (DAC). Each DAC has an analog ou tput pin (DA0 and DA1) and provides an interrupt si gnal to the AIC (DA0IRQ and DA1IR Q).
219 1745D–ATARM–04-Nov- 05 AT91M55800A DA = DAVREF x (DAC_DOR / 1024) When DAC_DOR ( Data Output Register) is lo aded, the an alog output v oltage is availa ble after a settling t ime of approximately 5 µsec.
220 1745D–ATARM–04-Nov-05 AT91M55800A 22.2 D A C User Interface Base Address DAC 0: 0xFFFA8000 (Code Label DAC0_BASE ) Base Address DAC 1: 0xFFFAC000 (Code Label DAC1_BASE ) Offset Register Name A.
221 1745D–ATARM–04-Nov- 05 AT91M55800A 22.2.1 DA C Control Regist er Register Name: D AC_CR Access Type: Write-only Offset: 0x00 • SWRST : Software Re set (Code Label DAC_SWRST ) 0 = No effect. 1 = Resets the DAC. A softw are-triggered reset of the DAC interface is performed.
222 1745D–ATARM–04-Nov-05 AT91M55800A 22.2.2 DA C Mode Register Register Name: DAC_MR Access Type: Read/Write Reset State: 0 Offset: 0x04 • TTRGEN: Ti mer T rigger Enable (Code La bel DAC_TTRGEN.
223 1745D–ATARM–04-Nov- 05 AT91M55800A 22.2.3 DA C Da ta Holding Register Register Name: D AC_DHR Access Type: Read/Write Reset State: 0 Offset: 0x08 • D A T A: Data to be Converted (C ode Labe l DAC_DATA_10BITS or DAC_DATA_8BITS depending on RES) Data that is to be converted by th e DAC is stored in this register.
224 1745D–ATARM–04-Nov-05 AT91M55800A 22.2.4 D A C Output Register Register Name: D AC_DOR Access Type: Read-only Reset State: 0 Offset: 0x0C • D A T A: Data being Con verted (Code Label DAC_DATA_10BITS or DAC_DATA_8BITS depending on RES) Data being conver ted is stored, in a right -aligned format, in this register.
225 1745D–ATARM–04-Nov- 05 AT91M55800A 22.2.6 DA C Inte rrupt Enable Register Register Name: DAC_IER Access Type: Write-only Offset: 0x14 • D A TRD Y : Data Read y for Con ver sion Interrupt Enable (Code Label DAC_DATRDY ) 0 = No effect. 1 = Enables the Data Ready fo r Conversion Interrupt.
226 1745D–ATARM–04-Nov-05 AT91M55800A 22.2.8 DA C Inte rrupt Mask Register Register Name: DAC_IMR Access Type: Read-only Reset State: 0 Offset: 0x1C • D A TRD Y : Data Read y for Con ver sion Interrupt Mask (Code Label DAC_DATRDY ) 0 = Data Ready for Conversion Inter rupt is disabled.
227 1745D–ATARM–04-Nov- 05 AT91M55800A 23. JT A G Boundary-scan Register The Boundary-scan Registe r (BSR) contains 256 bits which correspond to active pins an d associated control signals. Each AT91M558 00A input pin has a co rresponding bit in the Boundary-scan Regist er for observability.
228 1745D–ATARM–04-Nov-05 AT91M55800A 232 PB12 IN/OUT OUTPUT 231 INPUT 230 CTRL 229 PB11 IN/OUT OUTPUT 228 INPUT 227 CTRL 226 PB10 IN/OUT OUTPUT 225 INPUT 224 CTRL 223 PB9 IN/OUT OUTPUT 222 INPUT .
229 1745D–ATARM–04-Nov- 05 AT91M55800A 199 PB1 IN/OUT OUTPUT 198 INPUT 197 CTRL 196 PB0 IN/OUT OUTPUT 195 INPUT 194 CTRL 193 NCS7 OUTPUT OUTPUT 192 NCS6 OUTPUT OUTPUT 191 NCS5 OUTPUT OUTPUT 190 NC.
230 1745D–ATARM–04-Nov-05 AT91M55800A 164 P A21TXD2 IN/OUT INPUT 163 CTRL 162 P A20SCK2 IN/OUT OUTPUT 161 INPUT 160 CTRL 159 P A19RXD1 IN/OUT OUTPUT 158 INPUT 157 CTRL 156 P A18/TXD1/NTRI IN/OUT O.
231 1745D–ATARM–04-Nov- 05 AT91M55800A 129 P A9/IRQ0 IN/OUT OUTPUT 128 INPUT 127 CTRL 126 PA 8 / T I O B 5 IN/OUT OUTPUT 125 INPUT 124 CTRL 123 PA 7 / T I O A 5 IN/OUT OUTPUT 122 INPUT 121 CTRL 12.
232 1745D–ATARM–04-Nov-05 AT91M55800A 95 INPUT 94 CTRL 93 PB25/TCLK2 IN/OUT OUTPUT 92 INPUT 91 CTRL 90 PB24/TIOB1 IN/OUT OUTPUT 89 INPUT 88 CTRL 87 PB23/TIOA1 IN/ OUT OUTPUT 86 INPUT 85 CTRL 84 PB.
233 1745D–ATARM–04-Nov- 05 AT91M55800A 60 D9 IN/OUT INPUT 59 OUTPUT 58 D8 IN/OUT INPUT 57 OUTPUT 56 D[15:8] IN/OUT CTRL 55 D7 IN/OUT INPUT 54 OUTPUT 53 D6 IN/OUT INPUT 52 OUTPUT 51 D5 IN/OUT INPUT.
234 1745D–ATARM–04-Nov-05 AT91M55800A 25 A11 OUTPUT OUTPUT 24 A10 OUTPUT OUTPUT 23 A9 OUTPUT OUTPUT 22 A8 OUTPUT OUTPUT 21 A[15:8] OUTPUT CTRL 20 A7 OUTPUT OUTPUT 19 A6 OUTPUT OUTPUT 18 A5 OUTPUT .
235 1745D–ATARM–04-Nov- 05 AT91M55800A 24. P ac kaging Inf ormation Figure 24-1. 176-lead Thin Quad Flat Pack Package Dr awing PIN 1 aaa bbb cc 1 ddd θ2 θ3 S L1 R1 R2 0.
236 1745D–ATARM–04-Nov-05 AT91M55800A T able 24- 1. Common Dimensions (mm) Symbol Min Nom Max c 0.09 0.20 c1 0.09 0.16 L 0.45 0.6 0.75 L1 1.00 REF R2 0.08 0.2 R1 0.08 S0 . 2 q0 ° 3.5 ° 7 ° θ 10 ° θ 21 1 ° 12 ° 13 ° θ 31 1 ° 12 ° 13 ° A 1.
237 1745D–ATARM–04-Nov- 05 AT91M55800A Figure 24-2. 176-ball Ball Grid Array Package Drawing T able 24- 4. Device an d 176-ball BGA P ackage Max imum Weight 606 mg Notes: 1. P ackage dimensions conform to JEDEC MO-205 2. Dimensioning and tolerancing per ASME Y14.
238 1745D–ATARM–04-Nov-05 AT91M55800A 25. Soldering Pr ofile 25.1 Green P acka ge Soldering Profile Table 25-1 gi ves the recommended solder ing profile from J-STD-020 C. Note: The package is certified to be backw ard compatible with Pb/Sn solderi ng profile.
239 1745D–ATARM–04-Nov- 05 AT91M55800A 26. Or dering Information T able 26- 1. Ordering Inform ation Ordering Code Pac kage Pac kage T ype T emperature Operating Rang e A T91M55800A-33 AI LQFP 176.
240 1745D–ATARM–04-Nov-05 AT91M55800A 27. Errata The following known errata are applca ble to: • The follo wing datasheets: AT91M55800A Summa ry, 1745S AT91M55800A, (This document) AT91M55800 A, Electrical Char acteristics Rev .1727 • 176-lead LQFP and 17 6-ball BGA de vices with the f ollowing markings: 27.
241 1745D–ATARM–04-Nov- 05 AT91M55800A In other cases, the followin g erroneous behavior occurs: – 32-bit read ac cesses are not managed correct ly and the first 16-bit data sampling takes int o account only the standard wa it states. 16- and 8-b it accesses are not aff ected.
242 1745D–ATARM–04-Nov-05 AT91M55800A Figure 27-2. Number o f Standard W ait States is Two Note: 1. These numbers ref er to the standard access cycles. If the first two condition s are not met during a 32-bit read access, the fi rst 16-bit data is read at the end of the standa rd 16-bit read access.
243 1745D–ATARM–04-Nov- 05 AT91M55800A If the first t wo conditions are not met during writ e accesses, th e NWE signal is not affected b y the NWAIT assertion.
244 1745D–ATARM–04-Nov-05 AT91M55800A 27.6 SPI in Slave Mode does not W ork In transmission, the data to be transmitted (written in SP_TDR) is transferred in the shift register and, co nsequently, the TDRE bit in SP_SR is set to 1 .
245 1745D–ATARM–04-Nov- 05 AT91M55800A Rrevision History . Doc. Rev Date Comme nt s Change Re quest Ref. 1745A July, 2001 First Issue First issue 1745B 18 -Jul-2002 Pag e : 9 Change to Bl ock Diagram. P age : 9 “ P eripherals”: T ext changed. P age 10 “User P er ipherals”: T e xt changed.
i 1745D–ATARM–04-Nov- 05 AT91M55800A T able of Contents Features ................ ................ .............. ............... .............. .............. ............ 1 1 Description ............ ............................ ............... .
ii 1745D–ATARM–04-Nov-05 AT91M55800A 11.6 Re ad Protocols .......... ................ ............. ................ ............. ................ ............. 30 11.7 Write Data Hold Time ... ................ ............. ................ ....
iii 1745D–ATARM–04-Nov- 05 AT91M55800A 16.2 Ou tput Selectio n ........ ............. ................ ............. ................ ............. .............. 112 16.3 I/O Levels ........... ............. ................. ............ .......
iv 1745D–ATARM–04-Nov-05 AT91M55800A 20.6 Per ipheral Data Controller ............ ............. ................ ............. ................ ........ 192 20.7 SPI Programmer’s Model ....... ................ ............. ................ ...
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