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DS-102 Dual Channel RS-232 Asynchronous Communications Adapter for ISA compatible machines User's Manual QUATECH, INC. TEL: (330) 434-3154 662 Wolf Ledges Parkway FAX: (330) 434-1409 Akron, Ohio .
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28 VIII. TROUBLESHOOTING 27 VII. SPECIFICATIONS 25 BAUD RATE SELECTION 24 FIFO polled mode operation (16550 UART only) 23 FIFO INTERRUPT MODE OPERATION (16550 UART only) 22 SCRATCHPAD REGISTER 22 MODE.
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WARRANTY INFORMATION Quatech, Inc. warrants the DS-102 to be free of defects for one (1) year from the date of purchase. Quatech, Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period.
© 1993, Quatech, Inc. NOTICE The information contained in this document cannot be reproduced in any form without the written consent of Quatech, Inc. Likewise, any software programs that might accompany this document can be used only in accordance with any license agreement(s) between the purchaser and Quatech, Inc.
I . GENERAL INFORMATION The Quatech, Inc. DS-102 provides two RS-232 asynchronous serial communication interfaces for IBM-compatible personal computer systems using the ISA (Industry Standard Architecture) expansion bus. The DS-102's two serial ports are implemented using 16450 Universal Asynchronous Receiver/Transmitters (UARTs).
II . INSTALLATION If the default address and interrupt settings are sufficient, the DS-102 can be quickly installed and put to use. The factory defaults are listed in Figure 1 .
IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Set IRQ levels here (Diagram not to scale) 16450/16550 16450/16550 SW1 Serial 1 SW2 Serial 2 J4 Set addresses here (SW1, SW2) (J5, J6) J7 J8 J1 Serial 1 Serial 2 CN1 CN2 J5 J6 Serial 1 Serial 2 J2 J3 QUATECH INC.
III . ENABLING AND ADDRESSING PORTS Setting the address Each serial port on the DS-102 uses 8 consecutive I/O locations in the range of 0000 hex to 07FF hex.
Switch on bit = 0 Switch off bit = 1 Serial 1 uses SW1 Serial 2 uses SW2 Factory default setting for Serial 1 --- 03F8 hex (COM1) ON 1234567 8 8 2 1 F 4 8 8 2 1 3 0 SW1 Factory default setting for Ser.
The standard addresses for serial ports COM1 and COM2 are listed in Figure 5 . Recommended addresses for serial ports COM3 and COM4 are also listed. The switch settings for these addresses are shown in Figure 4 . 02E8 hex COM4 Recommendations only. No official standards exist for COM3 and COM4.
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IV . SETTING INTERRUPT LEVELS ( IRQ S) The DS-102 interrupt circuitry allows each port to use any interrupt level in the range IRQ2 through IRQ7. The interrupt levels are selected using jumper packs J5 for Serial 1 and J6 for Serial 2. In Figure 7 , the factory default settings for Serial 1 and Serial 2 are shown.
Interrupt Sharing An interrupt sharing circuit allows a port on the DS-102 to share an interrupt with the other port on the board or with another Quatech adapter supporting sharable interrupts. When interrupt sharing is used, the software must query each port attached to a given IRQ level when an interrupt for that IRQ is received by the computer.
V . EXTERNAL CONNECTIONS RS-232-C devices are classified by their function as either Data Terminal Equipment (DTE) or Data Communication Equipment (DCE).
To simplify connections to other devices, each port on the DS-102 is equipped with a jumper block that allows the port to be configured as either a DTE- or DCE-type device. This allows the DS-102 to communicate with either DTE- or DCE-type devices without using a null modem cable.
The DS-102 connects to peripheral equipment through male D-9 connectors. Adapters are available to convert these connectors into standard D-25 male connectors.
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VI . SERIAL PORT FUNCTIONAL DESCRIPTION This section contains information intended for advanced users planning to do custom programming with the DS-102. The information presented here is a technical description of the interface to the 16450 or 16550 UART.
Accessing the Serial Port registers Figure 15 lists the address map for the 16450 and 16550 UARTs. Each register can be accessed by reading from or writing to the proper I/O address. This I/O address is determined by adding an offset to the base address set for the particular serial port.
INTERRUPT ENABLE REGISTER This register is located at I/O address [base+1]. It enables the five types of UART interrupts. Interrupts can be totally disabled by setting all of the enable bits in this register to a logic 0. Setting any bit to a logic 1 enables that particular interrupt.
IP --- Interrupt pending: When logic 0, indicates that an interrupt is pending and the contents of the interrupt identification register may be used to determine the interrupt source. See Figure 18 . 0 IID0 --- 1 IID1 --- 2 Interrupt Identification: Indicates highest priority interrupt pending if any.
FIFO CONTROL REGISTER (16550 only) This register, which applies only to the 16550 UART, is a write-only register located at I/O address [base+2]. It is used to enable the FIFO mode, clear the FIFOs, set the threshold level for the receive FIFO to generate interrupts, and to set the mode under which the device uses DMA.
LINE CONTROL REGISTER This register is located at I/O address [base+3]. It is used for specifying the format of the asynchronous serial data to be processed by the UART, and to set the Divisor Latch Access Bit (DLAB) allowing access to the baud rate divisor latches.
MODEM CONTROL REGISTER This register is located at I/O address [base+4], and is used to control the interface with the modem or device used in place of a modem. This register allows the states of the "modem control signals" to be changed. These are DTR (Data Terminal Ready) and RTS (Request To Send).
LINE STATUS REGISTER This register is located at I/O address [base+5]. It is used to provide various types of status information concerning the data transfer. As Figure 22 shows, the Line Status Register indicates several types of errors, an empty transmit buffer, a ready receive buffer, or a break on the receive line.
MODEM STATUS REGISTER This register is located at I/O address [base+6]. It reports on the status of signals coming from the modem or equipment used in place of a modem.
FIFO INTERRUPT MODE OPERATION (16550 UART only) When the receiver FIFO and receiver interrupts are enabled: 1 . The receive data interrupt is issued when the receive FIFO reaches the trigger level. The interrupt is cleared as soon as the receive FIFO falls below the trigger level.
FIFO polled mode operation (16550 UART only) The receiver and transmitter are operated independently, which would allow either or both to be used in a polled mode rather than using interrupts to determine when the UART needs to be serviced.
BAUD RATE SELECTION The 16450 or 16550 UART determines the baud rate of the serial output using a combination of the clock input frequency and the value written to the divisor latches. Standard personal computer serial interfaces use an input clock of 1.
2.86 2 56000 - 3 38400 - 6 19200 - 12 9600 - 16 7200 - 24 4800 - 32 3600 - 48 2400 0.69 58 2000 - 64 1800 - 96 1200 - 192 600 - 384 300 - 768 150 0.026 1047 110 - 1536 75 - 2304 50 ERROR BETWEEN DESIRED AND ACTUAL VALUES (%) DIVISOR LATCH VALUE DESIRED BAUD RATE Figure 25 --- Divisor Latch settings for common baud rates using 1.
VII . SPECIFICATIONS Bus interface: Industry Standard Architecture (ISA) 8-bit bus Serial ports Controller: 16450 (16550 optional) Interface: Two male D-9 connectors Two male D-25 connectors optional using adapter cables Transmit drivers: MC1488 or compatible High level output voltage: +9V min, +10.
VIII . TROUBLESHOOTING Listed here are some common problems and frequent causes of those problems. Suggestions for corrective action are given. If the information here does not provide a solution, contact Quatech Customer Service for technical support.
DS-102 Dual Channel RS-232 Asynchronous Communications Adapter User's Manual Revision 3.00 August 13, 1993.
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