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ES-100 EIGHT CHANNEL RS-232 ASYNCHRONO US ADAPTER CARD for ISA compatible machines User's Manual QUATECH, INC. TEL: (330) 655-9000 5675 Hudson Industrial Parkway FAX: (330) 655-9010 Hudson, Ohio 44236 http://www.
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Warranty Information Quatech Inc. warrants the ES-100 to be free of defects for one (1) year from the date of purc hase. Quatech In c. will repair or replace a ny adapter that fails to perform under nor mal operating conditions and in accordance with the procedures outlined in this document during the warranty period.
The information contained in this doc ument cannot be reproduced in any form without the written consent of Quatech, In c. L ikewise, any software programs that might accompany this document can be used only in accordance with any license agreement(s) bet ween the purchaser and Quatech, Inc.
Compliances - Electromagnetic Emissions EC - Council Directive 89/336/EEC This equipment has been tested and found to comply with the limits of the following standards for a digital device: EN5008.
1. GENERAL INFORMATION The Quatech, Inc. ES-100D provides eight RS-232 asynchronous serial communication interfaces for IBM-compatible personal computer systems using the 16-bit ISA (Industry Standard Architecture) expansion bus. The ES-100D's serial ports are implemented using 16450 Universal Asynchronous Receiver/Transmitters (UARTs).
2. INSTALLATION If the default address and interrupt settings are sufficient, the ES-100D can be quickly installed and put to use. The factory defaults are listed in Figure 1.
(Diagram not to sc ale) SW 1 SW 2 Set addresses here (SW 1, SW 2) IRQ 2 IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 IRQ 1 0 IRQ 1 1 IRQ 1 2 IRQ 1 4 IRQ 1 5 J2 Set IRQ level he re (J2) QUATECH I NC.
3. ADDRESSING PORTS Setting the address The base address of the ES-100D is set using the two DIP switch packs. When setting the address selection switches, a switch in the "ON" position specifies that the corresponding address line must be a logic 0 for the port to be selected.
two, and one, hence the maximum value of 8+4+2+1 = 15. A serial por t's address is a 16-bi t quantity that is most often expressed in four hexadecimal (base 16) digit s. A hex digit can hold a value from 0 to 15 (decimal), and is made up of four binary bits given weights of eight , four, A possible seri al port address is 5240 hex.
4. INTERRUPT LEVEL (IRQ) The ES-100D allows the use of any interrupt level in the range IRQ2 to IRQ7, IRQ10 to IRQ12, IRQ14, or IRQ15, selected using jumper pack J2. In Figure 6, the factory default setting of IRQ3 is shown. To select a different IRQ, move the jumper to the appropriate position on J2.
ON 123456 SW 2 ON 123456 SW 2 Slide position 6 of SW 2 toward the top of the ES -100D to enable the interrupt stat us register, or tow ard the bottom of the E S-100D to disable it.
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5. EXTERNAL CONNECTIONS RS-232-C devices are classified by their function as either Data Terminal Equipment (DTE) or Data Communication Equipment (DCE).
Channel Output Configuration The ES-100D connects to peripheral equipment through a single female D-78 connector, or using the adapter cable, eight male D-25 connectors. The standard serial port connections are listed in Figure 11 . Unlisted pins are not used and not connected.
D-78 connect or 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 41 42 43 44 45 46 47 48 49 50 60 61 62 63 64 65 66 67 68 69 70 71 72 73 7.
6. SERIAL PORT FUNCTIONAL DESCRIPTION This section contains information intended for advanced users planning to do custom programming with the ES-100D. The information presented here is a technical description of the interface to the 16450 or 16550 UART.
Accessing the Serial Port registers Figure 13 lists the address map for the 16450 and 16550 UARTs. Each register can be accessed by reading from or writing to the proper I/O address. This I/O address is determined by adding an offset to the base address set for the particular serial port.
INTERRUPT ENABLE REGISTER This register is located at I/O address [base+1]. It enables the five types of UART interrupts. Interrupts can be totally disabled by setting all of the enable bits in this register to a logic 0. Setting any bit to a logic 1 enables that particular interrupt.
IP --- Interrupt pending: When logic 0, indicates that an interrupt is pending and the contents of the interrupt identification register may be used to determine the interrupt source. See Figure 16. 0 IID0 --- 1 IID1 --- 2 Interrupt Identification: Indicates highest priority interrupt pending if any.
FIFO CONTROL REGISTER (16550 only) This register, which applies only to the 16550 UART, is a write-only register located at I/O address [base+2]. It is used to enable the FIFO mode, clear the FIFOs, set the threshold level for the receive FIFO to generate interrupts, and to set the mode under which the device uses DMA.
LINE CONTROL REGISTER This register is located at I/O address [base+3]. It is used for specifying the format of the asynchronous serial data to be processed by the UART, and to set the Divisor Latch Access Bit (DLAB) allowing access to the baud rate divisor latches.
MODEM CONTROL REGISTER This register is located at I/O address [base+4], and is used to control the interface with the modem or device used in place of a modem. This register allows the states of the "modem control signals" to be changed. These are DTR (Data Terminal Ready) and RTS (Request To Send).
LINE STATUS REGISTER This register is located at I/O address [base+5]. It is used to provide various types of status information concerning the data transfer. As Figure 20 shows, the Line Status Register indicates several types of errors, an empty transmit buffer, a ready receive buffer, or a break on the receive line.
MODEM STATUS REGISTER This register is located at I/O address [base+6]. It reports on the status of signals coming from the modem or equipment used in place of a modem.
FIFO INTERRUPT MODE OPERATION (16550 UART only) When the receiver FIFO and receiver interrupts are enabled: 1. The receive data interrupt is issued when the receive FIFO reaches the trigger level. The interrupt is cleared as soon as the receive FIFO falls below the trigger level.
FIFO polled mode operation (16550 UART only) The receiver and transmitter are operated independently, which would allow either or both to be used in a polled mode rather than using interrupts to determine when the UART needs to be serviced.
BAUD RATE SELECTION The 16450 or 16550 UART determines the baud rate of the serial output using a combination of the clock input frequency and the value written to the divisor latches. Standard personal computer serial interfaces use an input clock of 1.
7. SPECIFICATIONS Bus interface: Industry Standard Architecture (ISA) 16-bit bus IBM PC-AT TM compatible Dimensions: 13.4" x 4.2" Serial ports Number of ports: eight Controllers: 16450 (1655.
8. TROUBLESHOOTING Listed here are some common problems and frequent causes of those problems. Suggestions for corrective action are given. If the information here does not provide a solution, contact Quatech Customer Service for technical support. Any unauthorized repairs or modifications will void the ES-100D's warranty.
Version 1.01 March 2004 Part No. 940 - 00 99-101 Quatech Inc , ES-100 Manual.
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