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Altera DE2-70 Board V ersion 1.01 Copyright © 2007 T erasic T echnologies.
Altera DE2 Board ii CONTENTS Chapter 1 DE2-70 Package ............................................................................................................... 1 1.1 Package Contents ..............................................................
Altera DE2 Board iii 5.12 TV Decoder ................................................................................................................ ........ 52 5.13 Implementing a TV Encoder ..........................................................
DE2-70 Us er Manual 1 Chapter 1 DE2-70 Package The DE2-70 package contains all components needed to use the DE 2-70 board in conjunction with a computer that runs the Microsoft W indows software. 1.1 Package Contents Figure 1.1 shows a photograph of the DE2-70 package.
DE2-70 Us er Manual 2 The DE2-70 package includes: • The DE2-70 board • USB Cable for FPGA programming and control • DE2-70 System CD containing the DE2-70 docum entation and supporting material.
DE2-70 Us er Manual 3 1.3 Getting Help Here are the addresses where you can get help if you encounter problems: • Altera Corporation 101 Innovation Drive San Jose, California, 95134 USA Email: university@altera.com • T erasic T echnologies No. 356, Sec.
DE2-70 Us er Manual 4 Chapter 2 Altera DE2-70 Board This chapter presents the features and design characteristics of the DE2-70 board. 2.1 Layout and Components A photograph of the DE2-70 board is shown in Fi gure 2.1. It depicts the layout of the board and indicates the location of the connectors and key components.
DE2-70 Us er Manual 5 (AS) programming modes are supported • 2-Mbyte SSRAM • T wo 32-Mbyte SDRAM • 8-Mbyte Flash memory • SD Card socket • 4 pushbutton switches • 18 toggle switches • 18 red user LEDs • 9 green user LEDs • 50-MHz oscillator and 28.
DE2-70 Us er Manual 6 Figure 2.2. Block diagram of the DE2-70 board. Following is more detailed informati on about the blocks in Figure 2.2: Cyclone II 2C70 FPGA • 68,416 LEs • 250 M4K RAM blocks .
DE2-70 Us er Manual 7 SSRAM • 2-Mbyte standard synchronous SRAM • Organized as 512K x 36 bits • Accessible as memory for the Nios II pr ocessor and by the DE2-70 Control Panel SDRAM • T wo 32-.
DE2-70 Us er Manual 8 Audio CODEC • W olfson WM8731 24-bit sigm a-delta audio CODEC • Line-level input, line-level outpu t, and microphone input jacks • Sampling frequency: 8 to 96 KHz • Applications for MP3 players and recorders, PDAs, smart phones, voice recorders, etc.
DE2-70 Us er Manual 9 Serial ports • One RS-232 port • One PS/2 port • DB-9 serial connector for the RS-232 port • PS/2 connector for connecting a PS2 m ouse or keyboard to the DE2-70 board IrDA tran sceiver • Contains a 1 15.
DE2-70 Us er Manual 10 At this point you should observe the following: • All user LEDs are flashing • All 7-segment displays are cycling through the numbers 0 to F • The LCD display shows W elcome to the Altera DE2-70 • The VGA monitor displays the image shown in Figure 2.
DE2-70 Us er Manual 11 Chapter 3 DE2-70 Contr ol Panel The DE2-70 board comes with a Control Panel f acility that allows users to access v arious components on the board from a host com puter . Th e host computer communi cates with the board through an USB connection.
DE2-70 Us er Manual 12 close that port; you cannot use Quartus II to do wnload a configuration f ile into the FPGA until you close the USB port. 7. The Control Panel is now ready for use; ex periment by setting the value of some LEDs display and observing the result on the DE2 -70 board.
DE2-70 Us er Manual 13 7-SEG Display 16x2 LCD LEDs LEDs PS/2 SDRAM Flash SSRAM SD Card Soket USB Blaster USB Device Control Codes Figure 3.2. The DE2 -70 Control Panel concept.
DE2-70 Us er Manual 14 Figure 3.3. Controlling LEDs. Choosing the 7-SEG tab leads to the window in Figure 3.4. In the tab sheet, directly use the Up-Down control and Dot Check box to specified desired patte rns, the 7-SEG patterns on the board will be updated immediately .
DE2-70 Us er Manual 15 Choosing the LCD tab leads to the window in Figure 3.5. T ext can be written to the LCD display by typing it in the LCD box and pressing the Set button. Figure 3.5. Controlling LEDs and the LCD display . The ability to set arbitrary values into sim ple display devices is not n eeded in typical desig n activities.
DE2-70 Us er Manual 16 Figure 3.6. Monitoring switches and buttons. The ability to check the sta tus of button and sw itch is not need ed in typical design activities. However , it provides users a simple mechanism for verifying if the bu ttons and switches are functioning correctly .
DE2-70 Us er Manual 17 Figure 3.7. Accessing the SDRAM-U1. A 16-bit word can be written in to the SDRAM by entering the a ddress of the desired location, specifying the data to be written, and pressing the Wri t e button. Contents of the location can be read by pressing the Read button.
DE2-70 Us er Manual 18 into the memory . The Sequential Read function is used to read the contents of the SDRAM-U1 and place them into a file as follows: 1. Specify the starting address in the Addr ess box. 2. Specify the number of bytes to be copied into the file in the Length box.
DE2-70 Us er Manual 19 Figure 3.8. USB Mouse Monitoring T ool. 3.6 PS2 Device The Control Panel provides users a tool to receive the inputs from a PS2 ke yboard in real tim e. The received scan-codes are translated to ASCII code and displayed in the control window .
DE2-70 Us er Manual 20 Figure 3.9. Reading the PS2 Keyboard. 3.7 SD CARD The function is designed to r ead the identifica tion and specification of the SD card. The 1-bit SD MODE is used to access the SD card. This fu ncti on can be used to verify the functionality of SD-CARD Interface.
DE2-70 Us er Manual 21 Figure 3.10. Reading the SD card Identification and Specification. 3.8 Audio Playing and Recording This interesting audio tool is designed to c ontrol the audio chip on the DE2-70 board for audio playing and recording. It can play audio stored in a given W A VE file, r ecord audio, and save the audio signal as a wave file.
DE2-70 Us er Manual 22 Figure 3.1 1. Playing audio fr om a selected wave file T o record sound using a microphone, please follow the steps below: 1. Plug a microphone to the MIC port on the board. 2. Select the “Record MIC” item in the com-box a nd select desired sam pling rate, as shown in Figure 3.
DE2-70 Us er Manual 23 Figure 3.12. Audio Recording and Saving as a W A V file. T o record audio sound from LINE-IN port, please connect an audio source to the LINE-IN port on the board.
DE2-70 Us er Manual 24 FPGA/ SOPC NIOS II TIMER JTAG System Interconnect Fabr ic SDRAM Controller LCD Controller PIO Controller PS2 Controller Flash Controller SSRAM Controller Avalon - MM Tri s tate .
DE2-70 Us er Manual 25 Chapter 4 DE2-70 V ideo Utility The DE2-70 board comes with a v ideo utility that allows users to access video components on the board from a host computer . The host computer com municates with the board throug h the USB-Blaster link.
DE2-70 Us er Manual 26 Figure 4.1. The DE2-70 V i deo Utility window . 4.2 VGA Display Choosing the Display tab in the DE2-70 V ideo Utility lead s to the window shown in Figure 4.2. The function is designed to download an image fr om the host com puter to the FPGA board and output the image through the VGA i nterface with resolution 640x480.
DE2-70 Us er Manual 27 Figure 4.2. Displaying selected image file on VGA Monitor . 4.3 V ideo Capture Choosing the Capture tab leads to the window in Figure 4.3. Th e function is designed to capture an image from the video so urces, and sent the image from the FPGA board to the host computer .
DE2-70 Us er Manual 28 Figure 4.3. V ideo Capturing T ool. 4.4 Overall S tructure of the DE2-70 V ideo Utility The DE2-70 V i deo Utility is based on a NIOS II system running in the Cy clone II FPGA with the SDRAM-U2 or SSRAM.
DE2-70 Us er Manual 29 FPGA SOPC NIOS II TIMER JTAG System Interconne ct Fabric SDRAM -U 1 SDRAM Controller Multi -P o r t SSRAM Controller JTAG Blaster Hardware VGA Controller SSRAM VIDEO -I n Controller Avalon MM Slave VGA VIDEO IN NIOS II Program SDRAM -U 2 SDRAM Controll er Figure 4.
DE2-70 Us er Manual 30 Chapter 5 Using the DE2-70 Board This chapter gives instructions for using the DE 2-70 board an d describes each of its I/O devices. 5.1 Configuring the Cyclon e II FPGA The procedure for downloading a circuit from a host computer to the DE2-70 board is described in the tutorial Quartus II Intr oduction .
DE2-70 Us er Manual 31 Configuring the FPGA in JT AG Mode Figure 5.1 illustrates the JT AG confi guration setup. T o download a conf iguration bit stream into the Cyclone II FPGA, perform the followin.
DE2-70 Us er Manual 32 position and then reset the board by turning th e power switch of f and back on; this action causes the new configuration data in the EPCS 16 device to be loaded into the FPGA chip.
DE2-70 Us er Manual 33 There are also 18 toggle switche s (sliders) on the DE2-70 board. These switches are not debounced, and are intended for use as level-sensitive data inputs to a circuit. Each switch is con nected directly to a pin on the Cyclone II FPGA.
DE2-70 Us er Manual 34 LED10 LED11 LED 13 LED12 LED16 LED17 LED15 LED14 LED9 LED8 LED2 LED 3 LED1 LED0 LED7 LED6 LED4 LED5 LED18 LED20 LED21 LED19 LED22 LED23 LED24 LED25 LED26 LED[0.
DE2-70 Us er Manual 35 SW[16] PIN_L7 Toggle Switch[16] SW[17] PIN_L8 Toggle Switch[17] T able 5.1. Pin assignments for the toggle switches. Signal Name FPGA Pin No. Description KEY[0] PIN_T29 Pushbutton[0] KEY[1] PIN_T28 Pushbutton[1] KEY[2] PIN_U30 Pushbutton[2] KEY[3] PIN_U29 Pushbutton[3] T able 5.
DE2-70 Us er Manual 36 LEDG[7] PIN_ AA24 LED Green[7] LEDG[8] PIN_ AC14 LED Green[8] T able 5.3. Pin assignments for the LEDs. 5.3 Using the 7-segm ent Displays The DE2-70 Board has eight 7-segm ent displays. These displays ar e arranged into two pairs and a group of four , with the intent of displaying numbers of various sizes .
DE2-70 Us er Manual 37 HEX0_D[3] PIN_AD10 Seven Segment Digit 0[3] HEX0_D[4] PIN_AF10 Seven Segment Digit 0[4] HEX0_D[5] PIN_AD11 Seven Segment Digit 0[5] HEX0_D[6] PIN_AD12 Seven Segment Digit 0[6] H.
DE2-70 Us er Manual 38 HEX5_D[0] PIN_M3 Seven Segment Digit 5[0] HEX5_D[1] PIN_L1 Seven Segment Digit 5[1] HEX5_D[2] PIN_L2 Seven Segment Digit 5[2] HEX5_D[3] PIN_L3 Seven Segment Digit 5[3] HEX5_D[4].
DE2-70 Us er Manual 39 SMA Connector 50-MHz Oscillator 28-MHz Oscillator TV decoder 1 TV decoder 2 VGA DAC Ethernet PS/2 AUDIO CODEC GPIO_0 GPIO_1 2 2 2 2 4 Cyclone II FPGA 2 4 SDRAM 1 SDRAM 2 SSRAM FLASH SD Card Figure 5.8. Block diagram of the clock distribution.
DE2-70 Us er Manual 40 5.5 Using the LCD Module The LCD module has built-in font s and can be used to display text by sending appropriate commands to the display controller , which is called HD44780.
DE2-70 Us er Manual 41 LCD_DATA[5] PIN_C2 LCD Data[5] LCD_DATA[6] PIN_C3 LCD Data[6] LCD_DATA[7] PIN_B2 LCD Data[7] LCD_RW PIN_F3 LCD Read/Write Select, 0 = Write, 1 = Read LCD_EN PIN_E2 LCD Enable LCD_RS PIN_F2 LCD Command/Data Select, 0 = Command, 1 = Data LCD_ON PIN_F1 LCD Power ON/OFF LCD_BLON PIN_G3 LCD Back Light ON/OFF T able 5.
DE2-70 Us er Manual 42 JP1 1.8V 2.5V 3.3V 2 1 4 35 6 Figure 5.10. JP1 pin settings. IO _A 2 IO _A 1 IO _A0 GP IO _D 0 G PIO _D 1 IO _A 10 IO _A 20 IO _A 24 IO _A 28 IO _A6 IO _A 13 IO _A 9 IO _A1 9 IO.
DE2-70 Us er Manual 43 IO_A [3] PIN_D29 GPIO Connection 0 IO[3] IO_A [4] PIN_E27 GPIO Connection 0 IO[4] IO_A [5] PIN_D28 GPIO Connection 0 IO[5] IO_A [6] PIN_E29 GPIO Connection 0 IO[6] IO_A [7] PIN_.
DE2-70 Us er Manual 44 IO_B [4] PIN_H28 GPIO Connection 1 IO[4] IO_B [5] PIN_L25 GPIO Connection 1 IO[5] IO_B [6] PIN_K27 GPIO Connection 1 IO[6] IO_B [7] PIN_L28 GPIO Connection 1 IO[7] IO_B [8] PIN_.
DE2-70 Us er Manual 45 5.7 Using VGA The DE2-70 board includes a 16-pin D-SUB conn ector for VGA output. Th e VGA synchronization signals are provided directly fr om the Cyclone II FPGA, and the Analog Devices ADV7123 triple 10-bit high-speed video DAC is used to produce th e analog data signals (red, green, and blue).
DE2-70 Us er Manual 46 found on the manufacturer's web site, or in the Datasheet/VGA DAC folder on the DE2-70 System CD-ROM . The pin assignments between the Cyclone II FPGA and the ADV7123 a re listed in T able 5.1 1. An example of code that drives a VGA display is described in Sections 6.
DE2-70 Us er Manual 47 Signal Name FPGA Pin No. Description VGA_R[0] PIN_D23 VGA Red[0] VGA_R[1] PIN_E23 VGA Red[1] VGA_R[2] PIN_E22 VGA Red[2] VGA_R[3] PIN_D22 VGA Red[3] VGA_R[4] PIN_H21 VGA Red[4] .
DE2-70 Us er Manual 48 5.8 Using the 24-bit Audio CODEC The DE2-70 board provides high-quality 24-b it audio via the W olfson WM8731 audio CODEC (enCOder/DECoder). This chip supp orts microphone-in, line-in, and li ne-out ports, with a sample rate adjustable from 8 kHz to 96 kHz.
DE2-70 Us er Manual 49 5.9 RS-232 Serial Port The DE2-70 board uses the ADM3202 transceiver chip and a 9-pin D-SUB connector for RS-232 communications. For detailed information on how to use the transceiver r efer to the datasheet, which is available on the manuf acturer ’ s web site, or in the Datasheet/RS232 folder on the DE2-70 System CD-ROM .
DE2-70 Us er Manual 50 KB C LK KB DA T MS DA T MS C LK PS 2_K B DA T PS 2_K B C LK PS 2_M SC LK PS 2_M SD AT VCC 5 V CC 5 VCC 5 VCC 33 VCC 33 VCC 5 VCC 5 VCC 33 V CC 33 R 172 2K R 172 2K BC 35 0.1u BC 35 0.1u R 174 120 R 174 120 R 175 120 R 175 120 D9 BA T54S D9 BA T54S 1 2 3 D 96 BA T54S D 96 BA T54S 1 2 3 D 10 BA T54S D 10 BA T54S 1 2 3 BC 34 0.
DE2-70 Us er Manual 51 SPEED ENET_ D0 ENET_ D15 ENET_D 13 ENET_ D1 ENET_ D 4 ENET_ D1 2 ENET_ D9 ENET_D 11 ENET_ D8 ENET_ D6 ENET_ D14 ENET_D 10 ENET_ D7 ENET_ D2 ENET_ D3 ENET_ D5 RX- TX+ TX- SPEED RX+ ACT ACT ENET_D [0.
DE2-70 Us er Manual 52 ENET_CS_N PIN_C28 DM9000A Chip Select ENET_INT PIN_C27 DM9000A Interrupt ENET_IOR_N PIN_A28 DM9000A Read ENET_IOW_N PIN_B28 DM9000A Write ENET_RESET_N PIN_B29 DM9000A Reset T able 5.15. Fast Ethernet pin assignments. 5.12 TV Decoder The DE2-70 board is equipped with two Anal og Devices ADV7180 TV decoder chips.
DE2-70 Us er Manual 53 TD 1_D 6 TD1_D7 TD 1_D 0 I2C _ SC LK I2C _ SD AT 28M HZ TD2_ D0 TD 2_D1 TD2_ D 2 TD2_ D 3 TD 2_D4 TD2_ D 5 TD2_ D6 TD 2_D7 TD 1_D1 28M HZ TD 1_D 2 TD 1_D3 TD 1_D4 TD1_D5 I2C _SDAT I2 C_SCLK TD 1_R ESET_n TD2_ RESET_n TD2_H S TD2_VS TD 1_HS TD 2_D[0.
DE2-70 Us er Manual 54 TD1_CLK27 PIN_G15 TV Decoder 1 Clock Input. TD1_RESET_N PIN_D14 TV Decoder 1 Reset TD2_D[0] PIN_C10 TV Decoder 2 Data[0] TD2_D[1] PIN_A9 TV Decoder 2 Data[1] TD2_D[2] PIN_B9 TV .
DE2-70 Us er Manual 55 5.14 Using USB Host and Device The DE2-70 board provides both USB host and de vice interfaces usi ng the Philips ISP1362 single-chip USB controller . The hos t and device controllers are com pliant with the Universal Seria l Bus Specification Rev .
DE2-70 Us er Manual 56 OTG_D[4] PIN_J12 ISP1362 Data[4] OTG_D[5] PIN_H12 ISP1362 Data[5] OTG_D[6] PIN_H13 ISP1362 Data[6] OTG_D[7] PIN_G13 ISP1362 Data[7] OTG_D[8] PIN_D4 ISP1362 Data[8] OTG_D[9] PIN_.
DE2-70 Us er Manual 57 The pin assignments of the associat ed interface are listed in T able 5.18. IR D A _T XD IR D A _R XD VCC 33 VCC 33 R 42 120 R 42 120 R 41 120 R 41 120 U6 IrD A U6 IrD A A G N D 4 V C C 3 N C 2 G N D 1 S D 5 R X D 6 T X D 7 LE D A 8 SH IE LD 9 R 43 47 R 43 47 Figure 5.
DE2-70 Us er Manual 58 DR AM 0_ A 3 DR AM 0_A 0 DR AM 0_ A 2 DR AM 0_A 1 DR AM 0_ A10 DR AM _D 5 DR AM _D 0 DR AM _D 7 DR AM _D 6 DR AM _D 3 DR AM _D 2 DR AM _D 4 DR A M _D 1 DR AM 1_ A 3 DR AM 1_A 0 .
DE2-70 Us er Manual 59 SRA M_byt een_n1 SRA M_byt een_n2 SRA M_byt een_n3 SRA M_addr7 SRA M_addr8 SRA M_addr9 SRA M_addr10 SRA M_addr11 SRA M_addr12 SRA M_addr13 SRA M_addr14 SRA M_addr15 SRA M_addr16.
DE2-70 Us er Manual 60 Signal Name FPGA Pin No. Description DRAM0_A[0] PIN_AA4 SDRAM 1 Address[0] DRAM0_A[1] PIN_AA5 SDRAM 1 Address[1] DRAM0_A[2] PIN_AA6 SDRAM 1 Address[2] DRAM0_A[3] PIN_AB5 SDRAM 1.
DE2-70 Us er Manual 61 DRAM0_CKE PIN_AA8 SDRAM 1 Clock Enable DRAM0_CLK PIN_AD6 SDRAM 1 Clock DRAM0_WE_N PIN_W9 SDRAM 1 Write Enable DRAM0_CS_N PIN_ Y10 SDRAM 1 Chip Select DRAM1_A[0] PIN_T5 SDRAM 2 A.
DE2-70 Us er Manual 62 DRAM1_RAS_N PIN_N9 SDRAM 2 Ro w Address Strobe DRAM1_CAS_N PIN_N8 SDRAM 2 Column Address Strobe DRAM1_CKE PIN_L10 SDRAM 2 Clock Enable DRAM1_CLK PIN_G5 SDRAM 2 Clock DRAM1_WE_N PIN_M9 SDRAM 2 Write Enable DRAM1_CS_N PIN_P9 SDRAM 2 Chip Select T able 5.
DE2-70 Us er Manual 63 SRAM_DQ[8] PIN_AK17 SRAM Data[8] SRAM_DQ[9] PIN_AJ17 SRAM Data[9] SRAM_DQ[10] PIN_AH17 SRAM Data[10] SRAM_DQ[11] PIN_AJ18 SRAM Data[11] SRAM_DQ[12] PIN_AH18 SRAM Data[12] SRAM_D.
DE2-70 Us er Manual 64 SRAM_DPA2 PIN_AK20 SRAM Parity Data[2] SRAM_DPA3 PIN_AJ9 SRAM Parity Data[3] SRAM_GW_N PIN_AG18 SRAM Global Write Enable SRAM_OE_N PIN_AD18 SRAM Output En able SRAM_WE_N PIN_AF18 SRAM Write Enable T able 5.20. SSRAM pin assignments.
DE2-70 Us er Manual 65 FLASH_DQ[5] PIN_AB29 FLASH Data[ 5] FLASH_DQ[6] PIN_AA29 FLASH Data[ 6] FLASH_DQ[7] PIN_Y28 FLASH Data[ 7] FLASH_DQ[8] PIN_AF30 FLASH Data[8] FLASH_DQ[9] PIN_AE29 FLASH Data[ 9].
DE2-70 Us er Manual 66 Chapter 6 Examples of Advanced Demonstrations This chapter provides a number of examples of advanced circuits implemented on the DE2-70 board. These circuits provide dem onstrations of the major features on the board, such as its audio and video capabilities, and USB an d Ethernet connectivity .
DE2-70 Us er Manual 67 • Optionally connect a VGA display to the VGA D-SUB connector . When connected, the VGA display should show a pattern of colors • Optionally connect a powered speaker to the stereo audio-out jack • Place toggle switch SW17 in the UP position to hear a 1 kHz humming sound from the audio-out port.
DE2-70 Us er Manual 68 monitor . ITU-R 656 Decoder YCbCr To RGB VGA Controller Even 4:2:2 Odd 4:2:2 MUX YUV 4:2:2 Odd Request 10-bit RGB I2C_SCLK I2C_SDAT Data Vali d DLY0 DLY1 DLY2 TD_DATA TD_HS TD_V.
DE2-70 Us er Manual 69 DE-inte rlace ITU-R 656 YUV 4:2:2 Decoder VGA(LCD/CRT)Monit or Line Out VGA O ut DVD Pl ay e r Video In Line In Audio Output CVBS S- Vi de o YPbPr Output Speaker Figure 6.
DE2-70 Us er Manual 70 described in the section 6.2. The Composite_to_VGA block takes the video signals from the TV decoders as input and generate VGA-interfaced signals as outpu t. The circuit in the FPGA is equipped with two Composite_to_VGA blocks converting the video si gnals from the TV decoder 1 and TV decoder 2 respectively .
DE2-70 Us er Manual 71 RCA type, then an adaptor will be needed to convert to th e m ini-stereo plug supported on the DE2-70 board; this is the same type of plug supported on most computers • Load the bit stream into FPGA. • The detailed configuration for switching video source of main and su b window are listed in T able 6.
DE2-70 Us er Manual 72 SW[16] = OFF SW[17] = OFF; SW[16] = ON Signal display mode Video in 1 SW[17] = ON; SW[16] = OFF PIP display mode Main window: Video in 2 Sub window : Video in 1 SW[17] = ON; SW[16] = ON PIP display mode Main window: Video in 1 Sub window : Video in 2 T able 6.
DE2-70 Us er Manual 73 Nios II CPU Altera System Interconnect Fabric Philips ISP1362 Host Port VGA Controller Frame Buffer USB Mouse ADV7123 Figure 6.5. Block diagram of the USB paintbrush demonstration. Demonstration Setup, File Lo cations, and Instructions Project directory: DE2_70_NIOS_HOST_MOUSE_VGA Bit stream used: DE2_70_NIOS_HOST_MOUSE_VGA.
DE2-70 Us er Manual 74 USB Dri ver VGA Contro ller IP On-Chip Video Frame Buf fer VGA Mo nit o r Figure 6.6. The setup for the USB paintbrush demonstration. 6.5 USB Device Most USB applications and products operate as USB devices, rather than USB hosts.
DE2-70 Us er Manual 75 the user clicks on the Clear button in the window panel of the software driver , the host computer sends a dif ferent USB packet to the b oard, which cau ses the Nios II processor to clear the hardware counter to zero. Figure 6.
DE2-70 Us er Manual 76 USB Driver 7-SEG Contr ol Accumulator PC Figure 6.8. The setup for the USB device demonstration. 6.6 A Karaoke Machine This demonstration uses the microphone-in, line-i n, and line-out ports on the DE2-70 board to create a Karaoke Machine application.
DE2-70 Us er Manual 77 Figure 6.9. Block diagram of the Karaoke Machine demonstration. Demonstration Setup, File Lo cations, and Instructions • Project directory: DE2-70_i2sound • Bit stream used: DE2-70_i2sound.
DE2-70 Us er Manual 78 Clo ck/ Dat a Frequency Genera tor Speaker MP3/Any Audi o O ut put Micr ophone Figure 6.10. The setup fo r the Karaoke Machine. 6.7 Ethernet Packet Sending/Recei ving In this demonstration, we will show how to send and receive Ethern et packets using the Fast Ethernet controller on DE2-70 board.
DE2-70 Us er Manual 79 address in the packet is identical to the MAC address of the DE2- 70 board. If the packet received does have the same MAC address or is a broadcast packet, th e DM9000A will accept the packet and send an interrupt to the Ni os II processor .
DE2-70 Us er Manual 80 Ethernet Driver 10/100M bps CAT 5 Cable Loopback Device Figure 6.12. The setup for the Ethernet demonstration. 6.8 SD Card Music Player Many commercial media/aud io players use a large ex ternal storage device, such as an SD card or CF card, to store music or video f iles.
DE2-70 Us er Manual 81 Figure 6.13 shows the hardware block diagram of this demonstration. The system requires a 50 MHZ clock provided from the boa rd. The PLL generates a 100-MH Z clock for NIOS II processor and the other controllers except for the audio cont roller .
DE2-70 Us er Manual 82 Figure 6.14. Software Stack of th e SD m usic player demonstration. The audio chip should be configured before se nding audio signal to the audio chip.
DE2-70 Us er Manual 83 • Press KEY3 on the DE2-70 board can play the next music file stored in the SD card. • Press KEY2 and KEY1 will increase and decreas e the output music volum e respectively . . Figure 6.16 illustrates the setup for this demonstration.
DE2-70 Us er Manual 84 Figure 6.15 shows the block diagram of the design of the Music Synthesizer . There are four major blocks in the circuit: DEMO_SOUND , PS2_KEYBOARD , ST AFF , and T ONE_GENERA TOR .
DE2-70 Us er Manual 85 • Bit stream used: DE2_70_Synthesizer .sof or DE2-70_Synthesizer .pof • Connect a PS/2 Keyboard to the DE2-70 board. • Connect the VGA output of the DE2-70 board to a VGA monitor (both LCD and CR T type of monitors should work) • Connect the Lineout of the DE2-70 board to a speaker .
DE2-70 Us er Manual 86 I #4 K 5 O #5 L 6 P #6 : 7 “ +1 T able 6.3. Usage of the PS/2 Keyboard’ s keys. Line O u t Keyboard I npu t VGA O ut Music Synthesizer Algor it hms for A ud io Processing VGA( LCD/CRT) Moni tor Keyboar d Speaker CD E F GA BC D EF G A BC D EF G AB Figure 6.
DE2-70 Us er Manual 87 6.10 Audio Recording and Playing This demonstration sho ws how to implement an a udio recorder and player using the DE2-70 board with the built-in Audio CODEC chip. This demons tration is developed based on SOPC Builder and NIOS II IDE.
DE2-70 Us er Manual 88 hardware part is built by SOPC Builder under Quar tus II. The hardware part includes all the other blocks. The “AUDIO Controller” is a user-defined SOPC component. It is designed to send audio data to the audio chip or receive audio data from the audio chip.
DE2-70 Us er Manual 89 • Load the Software Execution File into FPGA. ( note * 1 ) • Configure audio with the toggle switches. • Press KEY3 on the DE2-70 board to start/stop audio recoding ( note *2 ) • Press KEY2 on the DE2-70 board to start/stop au dio playing ( note *3 ) Note: (1).
DE2-70 Us er Manual 90 Chapter 7 Appendix 7.1 Revision History V ersion Change Log V1.0 Initial V ersion (Preliminary) V1.01 1. Add appendix chapter . 2. Modify Chapter 2,3,4,5,6. 7.2 Copyright S tatement Copyright © 2007 T erasic T echnolog ies. All rights reserved.
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