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www.ti.com PRODUCT PREVIEW 1 TMS320DM355 Digital Media System-on-Chip (DMSoC) 1.1 Features TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 encod.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 – IEEE-1149.1 (JTAG) • 337-Pin Ball Grid Array (BGA) Package Boundary-Scan-Compatible (ZCE Suffix), 0.
www.ti.com PRODUCT PREVIEW 1.2 Description TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DM355 is a highly integrated, programmable platfo.
www.ti.com PRODUCT PREVIEW 1.3 Functional Block Diagram Peripherals 64bitDMA/DataBus JT AG 24MHz 27MHz (optional) CCD/ CMOS Module DDR2/MDDR16 CLOCK PLL CLOCKctrl PLLs JT A JT AG I/F.
www.ti.com PRODUCT PREVIEW Contents TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 1 TMS320DM355 Digital Media System-on-Chip 4.2 Recommended Operating Conditions ............... 92 (DMSoC) ....
www.ti.com PRODUCT PREVIEW 2 Device Overview 2.1 Device Characteristics TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-1 provides an overview of the DMSoC.
www.ti.com PRODUCT PREVIEW 2.2 Memory Map Summary TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-3 shows the memory map address ranges of the device. Table 2-3 depicts the expanded map of the Configuration Space (0x01C0 0000 through 0x01FF FFFF).
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-3. DM355 ARM Configuration Bus Access to Peripherals (continu.
www.ti.com PRODUCT PREVIEW 2.3 Pin Assignments 2.3.1 Pin Map (Bottom View) 9 J 8 V SSA_PLL2 7 V DDA33_USB 6 5 4 3 1 H G V DDA13_USB V SS F E D CIN2 C B A VREF CIN3 CIN0 V DDA_PLL2 V SS LCD_OE FIELD VC.
www.ti.com PRODUCT PREVIEW W 9 DDR_CLK 8 DDR_CLK 7 6 5 4 DDR_A05 3 2 DDR_A02 1 V DDR_A07 DDR_A04 DDR_A00 U V SS T PCLK R P N M L K DDR_A1 1 DDR_A09 DDR_A08 V SS DDR_CAS DDR_BA[2] DDR_A12 DDR_A10 DDR_A.
www.ti.com PRODUCT PREVIEW CV DD 19 W 18 DDR_GA TE0 17 DDR_DQ15 16 DDR_DQ13 15 DDR_DQ1 1 14 DDR_DQ10 13 DDR_DQ07 12 DDR_DQ05 1 1 DDR_DQ01 10 DDR_WE EM_A13 V V SS DDR_GA TE1 DDR_DQ14 DDR_DQS[1] DDR_DQ0.
www.ti.com PRODUCT PREVIEW 19 18 17 16 15 14 13 12 11 10 EM_D05 J EM_D02 H EM_CE1 G F E D C V DD B A EM_D03 EM_D01 EM_CE0 EM_WE V SS EM_D00 EM_ADV ASP0_DX V SSA_PLL1 CV DD EM_WAIT ASP0_FSX GIO003 V DD.
www.ti.com PRODUCT PREVIEW 2.4 Pin Functions 2.4.1 Image Data Input - Video Processing Front End TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-5. CCD Controller/Video Input Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW 2.4.2 Image Data Output - Video Processing Back End (VPBE) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-5. CCD Controller/Video Input Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-6. Signals for VPBE Display Modes PIN NAME YCC16 YCC8/ PRGB S.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-7. Digital Video Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION (4) NAME NO.
www.ti.com PRODUCT PREVIEW 2.4.3 Asynchronous External Memory Interface (AEMIF) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-8. Analog Video Terminal Functions TERMINAL TYPE (1) OTHER (2) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW 2.4.4 DDR Memory Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-10. DDR Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW 2.4.5 GPIO TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The General Purpose I/O signals provide generic I/O to external devices. Most of the GIO signals are multiplexed with other functions.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW 2.4.6 Multi-Media Card/Secure Digital (MMC/SD) Interfaces TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DM355 includes two Multi-Media Card/Secure Digital card interfaces that are compatible with the MMC/SD and SDIO protocol.
www.ti.com PRODUCT PREVIEW 2.4.7 Universal Serial Bus (USB) Interface 2.4.8 Audio Interfaces TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The Universal Serial Bus (USB) interface supports the USB2.
www.ti.com PRODUCT PREVIEW 2.4.9 UART Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-14. ASP Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW 2.4.10 I 2 C Interface 2.4.11 Serial Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-15. UART Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW 2.4.12 Clock Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-17. SPI Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW 2.4.13 Real Time Output (RTO) Interface 2.4.14 Pulse Width Modulator (PWM) Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The provides Real Time Output (RTO) interface.
www.ti.com PRODUCT PREVIEW 2.4.15 System Configuration Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-20. PWM Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW 2.4.16 Emulation TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-21. System/Boot Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
www.ti.com PRODUCT PREVIEW 2.5 Pin List TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23 provides a complete pin description list in pin number order.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Po.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Po.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Po.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Po.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Po.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Po.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Po.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State EM_A09 / P17 I/O AEMI V DD PD in L Async EMIF: Address Bus bit[09] PINMUX2[0].
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Po.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State EM_D09 / K18 I/O AEMI V DD in Async EMIF: Data Bus bit[09] PINMUX2[4].
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State EM_WE / J15 I/O AEMI V DD out H Async EMIF: Write Enable PINMUX2[8].
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State MMCSD1_DAT B16 I/O MMC V DD in MMCSD1: DATA3 PINMUX3[9:8].
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State SPI1_SCLK / C13 I/O SPI1 / V DD in SPI1: Clock PINMUX3[24].
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Po.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Po.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State RSV03 L1 A Reserved.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset Description (4) Mux Control ID (1) Supply (2) PD (3) State CV DD R8 PWR Core power (1.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Po.
www.ti.com PRODUCT PREVIEW 2.6 Device Support 2.6.1 Development Tools 2.6.2 Device Nomenclature TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 .
www.ti.com PRODUCT PREVIEW DM355 PREFIX TMX 320 DM355 ZCE TMX = Experimentaldevice TMS = Qualifieddevice DEVICEF AMILY 320 = TMS320 DSP family P ACKAGE TYPE (A) ZCE = 337-pinplasticBGA,withPb-freesolderedballs DEVICE (B ) A.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Digital Media System-on-Chip (DMSoC).
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 SPRUEE7 TMS320DM35x DMSoC Pulse-Width Modulator (PWM) Reference Guide This document describes the pulse-width modulator (PWM) peripheral in the TMS320DM35x Digital Media System-on-Chip (DMSoC).
www.ti.com PRODUCT PREVIEW 3 Detailed Device Description 3.1 ARM Subsystem Overview 3.1.1 Components of the ARM Subsystem TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 This section provides a detailed overview of the DM355 device.
www.ti.com PRODUCT PREVIEW ARM926EJ-S 16KI$ 8KD$ MMU CP15 Arbiter Arbiter I-AHB D-AHB Master IF DMAbus I-T CM D-T CM 16K RAM0 RAM1 16K ROM 8K Arbiter Slav e IF MasterIF CFGbus ARM inter r upt controller (AINT C) control System PLLC2 PLLC1 (PSC) controller sleep Po wer Peripherals .
www.ti.com PRODUCT PREVIEW 3.2.1 CP15 3.2.2 MMU 3.2.3 Caches and Write Buffer TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • Embedded Trace.
www.ti.com PRODUCT PREVIEW 3.2.4 Tightly Coupled Memory (TCM) 3.2.5 Advanced High-performance Bus (AHB) 3.2.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB) 3.
www.ti.com PRODUCT PREVIEW 3.3.2 External Memories 3.3.3 Peripherals 3.4 ARM Interrupt Controller (AINTC) 3.4.1 Interrupt Mapping TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBE.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-1. AINTC Interrupt Connections (continued) Interrupt Acronym .
www.ti.com PRODUCT PREVIEW 3.5 Device Clocking 3.5.1 Overview TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DM355 requires one primary reference clock . The reference clock frequency may be generated either by crystal input or by external oscillator.
www.ti.com PRODUCT PREVIEW ARMsubsystem MPEG/JPEG Coprocessor SYSCLK1 SYSCLK2 VPFE VPBE DAC DDRPHY DDR PLLDIV1(/1) BPDIV(/8) PLL controller2 PLL controller1 PLLDIV3(/n) PLLDIV2.
www.ti.com PRODUCT PREVIEW 3.5.2 Supported Clocking Configurations for DM355-216 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 This section describes the only supported device clocking configurations for DM355-216.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.5.2.2 Supported Clocking Configurations for DM355-216 (36 MHz reference) 3.
www.ti.com PRODUCT PREVIEW 3.5.3 Supported Clocking Configurations for DM355-270 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 This section describes the only supported device clocking configurations for DM355-270.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-7. PLL2 Supported Clocking Configurations for DM355-270 (24 M.
www.ti.com PRODUCT PREVIEW 3.5.4 Peripheral Clocking Considerations TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.5.3.2.2 DM355-270 PLL2 (36 MHz reference) All supported clocking configurations for DM355-270 PLL2 with 36 MHz reference clock are shown in Table 3-5 Table 3-9.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 divided internally by three) to the USB PHY. The USB PHY is capable of accepting only 24 MHz and 12 MHz; thus you must use either a 24 MHz or 36 MHz crystal at MXI1/MXO1.
www.ti.com PRODUCT PREVIEW 3.6 PLL Controller (PLLC) 3.6.1 PLL Controller Module TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 This section describes the PLL Controllers for PLL1 and PLL2.
www.ti.com PRODUCT PREVIEW 3.6.2 PLLC1 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 PLLC1 provides most of the DM355 clocks. Software controls PLLC1 operation through the PLLC1 registers. The following list, Table 3-10 , and Figure 3-3 describe the customizations of PLLC1 in the DM355.
www.ti.com PRODUCT PREVIEW PLLDIV1(/2) PLLDIV2(/4) PLLDIV3(/3) SYSCLK1 (ARMandMPEG/JPEG Coprocessor) SYSCLK2 (peripherals) SYSCLK3 (VPBE) 1 0 PLL 0 1 CLKMODE CLKIN OSCIN PLLEN AUXCLK (P.
www.ti.com PRODUCT PREVIEW 3.6.3 PLLC2 PLLDIV1(/1) 1 0 PLL 0 1 CLKMODE CLKIN OSCIN PLLEN SYSCLK1 (DDRPHY) SYSCLKBP (CLKOUT3) BPDIV(/8) PLLM (programmable) Pre-DIV (programmable) Post-DIV (/1) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 PLLC2 provides the DDR PHY clock and CLKOUT3.
www.ti.com PRODUCT PREVIEW 3.7 Power and Sleep Controller (PSC) arm_clock arm_mreset arm_power AINTC ARM module_power module_mreset MODx module_clock Alwayson domain Interrupt PSC clks PLLC Emulation RESETN VDD DMSoC 3.
www.ti.com PRODUCT PREVIEW 3.9 Pin Multiplexing 3.9.1 Hardware Controlled Pin Multiplexing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • P.
www.ti.com PRODUCT PREVIEW 3.9.2 Software Controlled Pin Multiplexing 3.10 Device Reset TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-13.
www.ti.com PRODUCT PREVIEW 3.11 Default Device Configurations 3.11.1 Device Configuration Pins TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-14. Reset Types (continued) Type Initiator Effect Module Reset ARM software Resets a specific module.
www.ti.com PRODUCT PREVIEW 3.11.2 PLL Configuration 3.11.3 Power Domain and Module State Configuration TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 After POR, warm reset, and max reset, the PLLs and clocks are set to their default configurations.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-16. Module Configuration Default States Module Module Name Po.
www.ti.com PRODUCT PREVIEW 3.11.4 ARM Boot Mode Configuration 3.11.5 AEMIF Configuration 3.12 Device Boot Modes TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-16.
www.ti.com PRODUCT PREVIEW 3.12.1 Boot Modes Overview TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The boot selection pins (BTSEL[1:0]) determine the ARM boot process.
www.ti.com PRODUCT PREVIEW Boot mode ? Reset Boot mode ? Bootfrom NANDflash InternalROM BootOK? No Y es Bootfrom UART Bootfrom MMC/SD BootOK? BootOK? Y es No Invokeloaded Program Invoke OneNAND No Y es 3.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 to static current leakage and occurs regardless of the clock rate. Leakage, or standby power, is unavoidable while power is applied and scales roughly with the operating junction temperatures.
www.ti.com PRODUCT PREVIEW 3.14 64-Bit Crossbar Architecture 3.14.1 Crossbar Connections 3.14.2 EDMA Controller TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DM355 uses a 64-bit crossbar architecture to control access between device processors, subsystems and peripherals.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The EDMA Controller consists of two major blocks: the Transfer Controller (TC) and the Channel Controller (CC).
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 DMA Channels: Can be triggered by: " External events (for exampl.
www.ti.com PRODUCT PREVIEW 3.15 MPEG/JPEG Overview TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-19.
www.ti.com PRODUCT PREVIEW 4 Device Operating Conditions 4.1 Absolute Maximum Ratings Over Operating Case Temperature Range TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 (Unless Otherwise Noted) (3) (4) All 1.
www.ti.com PRODUCT PREVIEW 4.2 Recommended Operating Conditions TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 MIN NOM MAX UNIT CV DD Supply voltage, Core 1.235 1.3 1.365 V V DDA_PLL1 Supply voltage, PLL1 1.
www.ti.com PRODUCT PREVIEW 4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVIS.
www.ti.com PRODUCT PREVIEW 5 Peripheral Information and Electrical Specifications 5.1 Parameter Information Device-Specific Information T ransmissionLine 4.0pF 1.85pF Z0=50 Ω (seenote) T ester PinElectronics Data SheetT imingReferencePoint Output Under T est 42 Ω 3.
www.ti.com PRODUCT PREVIEW 5.1.2 Timing Parameters and Board Routing Analysis TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The timing parameter values specified in this data sheet do not include delays by board routings.
www.ti.com PRODUCT PREVIEW 5.2 Recommended Clock and Control Signal Transition Behavior 5.3 Power Supplies TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 All clocks and control signals should transition between V IH and V IL (or between V IL and V IH ) in a monotonic manner.
www.ti.com PRODUCT PREVIEW 5.3.1 Power-Supply Sequencing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 In order to ensure device reliability, the DM355 requires the following power supply power-on and power-off sequences.
www.ti.com PRODUCT PREVIEW 5.4 Reset 5.4.1 Reset Electrical Data/Timing 1 2 3 RESET BootConfigurationPins (BTSEL[1:0],AECFG[3:0]) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-2.
www.ti.com PRODUCT PREVIEW 5.5 Oscillators and Clocks 5.5.1 MXI1 (24-MHz) Oscillator Crystal 24MHzor 36MHz C1 C2 MXI1/CLKIN MXO1 V SS_MX1 0.1 F 1 F L1 V DD A_PLL 1 V SSA_PLL 1 C L C 1 C 2 (C .
www.ti.com PRODUCT PREVIEW 5.5.2 MXI2 (27-MHz) Oscillator (optional oscillator) Crystal 27MHz C1 C2 MXI2 MXO2 V SS_M X2 L1 V DD A_PLL 2 V SSA_PLL 2 0.1 F 1 F C L C 1 C 2 (C 1 C 2 ) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-3.
www.ti.com PRODUCT PREVIEW 5.5.3 Clock PLL Electrical Data/Timing (Input and Output Clocks) MXI/CLKIN 2 3 4 4 5 1 MXI/CLKIN 2 3 4 4 5 1 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-5. Timing Requirements for MXI1/CLKIN1 (1) (2) (see Figure 5-7 ) DM355 NO UNIT .
www.ti.com PRODUCT PREVIEW CLKOUT1 1 2 4 4 MXI/CLKIN 5 6 3 MXI/CLKIN CLK OUT2 1 2 3 4 5 6 4 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-7. Switching Characteristics Over Recommended Operating Conditions for CLKOUT1 (1) (2) (see Figure 5-9 ) DM355 UNI NO.
www.ti.com PRODUCT PREVIEW 5 6 1 2 3 4 4 MXI/CLKIN CLK OUT3 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-9. Switching Characteristics Over Recommended Operating Conditions for CLKOUT3 (1) (2) (see Figure 5-11 ) DM355 NO.
www.ti.com PRODUCT PREVIEW 5.6 General-Purpose Input/Output (GPIO) 5.6.1 GPIO Peripheral Input/Output Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
www.ti.com PRODUCT PREVIEW GPIx GPOx 4 3 2 1 5.6.2 GPIO Peripheral External Interrupts Electrical Data/Timing EXT_INTx 2 1 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-12. GPIO Port Timing Table 5-12.
www.ti.com PRODUCT PREVIEW 5.7 External Memory Interface (EMIF) 5.7.1 Asynchronous EMIF (AEMIF) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 supports several memory and external device interfaces, including: • Asynchronous EMIF (AEMIF) for interfacing to SRAM.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.7.1.3 AEMIF Electrical Data/Timing Table 5-13. Timing Requirements for Asynchronous Memory Cycles for AEMIF Module (1) (see Figure 5-14 and Figure 5-15 ) DM355 NO UNIT .
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for AEMIF Module (see Figure 5-14 and Figure 5-15 ) (continued) DM355 UNI NO.
www.ti.com PRODUCT PREVIEW EM_CE[1:0] EM_BA[1:0] 13 12 EM_A[13:0] EM_OE EM_D[15:0] EM_WE 10 5 9 7 4 8 6 3 1 EM_CE[1:0] EM_BA[1:0] EM_A[13:0] EM_WE EM_D[15:0] EM_OE 15 1 16 18 20 22 24 17 19 21 23 26 27 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-14.
www.ti.com PRODUCT PREVIEW EM_CE[1:0] 1 1 Asserted Dea sser ted 2 2 14 EM_BA[1:0] EM_A[13:0] EM_D[15:0] EM_OE EM_W AIT SETU P STROBE Extend ed Due to EM_W AIT STR OBE HOLD EM_CE[1:0] 25 Asserted Dea s.
www.ti.com PRODUCT PREVIEW 34 33 35 36 37 30 31 Da Da+1 Da+2 Da+3 Da+4 Da+5 Da+n Da+n+1 EM_CLK EM_CE[1:0] EM_AD V EM_BA0, EM_A[13:0], EM_BA1 EM_D[15:0] EM_OE EM_WAIT 38 39 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-18.
www.ti.com PRODUCT PREVIEW 5.7.2 DDR2 Memory Controller TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DDR2 / mDDR Memory Controller is a dedicated interface to DDR2 / mDDR SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices.
www.ti.com PRODUCT PREVIEW 5.8 MMC/SD 5.8.1 MMC/SD Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DM355 includes two separate MMC/SD Controllers which are compliant with MMC V3.
www.ti.com PRODUCT PREVIEW ST ART XMIT V alid V alid V alid END SD_CLK SD_CMD 13 7 10 9 13 13 13 ST ART XMIT V alid V alid V alid END SD_CLK SD_CMD 10 9 7 1 2 ST ART D0 D1 Dx END SD_CLK SD_DA Tx 7 14 .
www.ti.com PRODUCT PREVIEW 5.9 Video Processing Sub-System (VPSS) Overview 5.9.1 Video Processing Front-End (VPFE) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVI.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • Support for program lens shading correction. • Support for 10-bit to 8-bit A-law compression. • Support for a low-pass filter prior to writing to SDRAM.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.9.1.3 Hardware 3A (H3A) The H3A module is designed to support the control loops for Auto Focus, Auto White Balance and Auto Exposure by collecting metrics about the imaging/video data.
www.ti.com PRODUCT PREVIEW PCLK 2 1 3 4 4 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.9.1.4 VPFE Electrical Data/Timing Table 5-17. Timing Requirements for VPFE PCLK Master/Slave Mode (see Figure 5-23 ) DM355-216 DM355-270 NO.
www.ti.com PRODUCT PREVIEW PCLK (Positive Edge C l ocking ) PCLK (Neg ative Edge Clockin g) 7,9 HD/VD CI[7:0]/YI[7:0]/ CCD[13:0] 8,10 1 1,13 12,14 5 6 C_WE /C_FIELD PCLK (PositiveEdge.
www.ti.com PRODUCT PREVIEW PCLK (PositiveEdgeClocking) 18 20 HD VD PCLK (NegativeEdgeClocking) 5.9.2 Video Processing Back-End (VPBE) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-20.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 blending for that corresponding video pixel) • Ability to resize from VGA to NTSC/PAL (640x480 to 720x576) for both the OSD and video windows • Horizontal rescaling x1.
www.ti.com PRODUCT PREVIEW 1 PCLK 2 3 7 5 6 4 8 EXTCLK 4 8 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • Internal Color Bar Generation (100%/75%) • YUV/RGB modes support HDTV output (720p/1080i) with 74.
www.ti.com PRODUCT PREVIEW VCLKIN (A) (Positive Edge C l ocking ) 9 VCLKIN (A) (Neg ati ve Edg e Clocking ) 10 VCTL (B ) A. VCLKIN=PCLKorEXTCLK B. VCTL=HSYNC,VSYNC,andFIELD VCLKIN (A) (Positive Edge C locking) 13 VCLKIN (A) (Neg ative Edge Clo cki ng ) 1 1 VCTL (B ) A.
www.ti.com PRODUCT PREVIEW VCLK (Positive Edge Clocking ) VCLK (Neg ative Edge Clocking ) 17 VCTL (B ) VDA T A (C) 19 18 22 21 23 24 25 26 VCLKIN (A) A.
www.ti.com PRODUCT PREVIEW DIN<9:0> MSB LSB DACDigitalInput ExampleforExternalCircuit Iout[mA] 1.4mA 0 DACOutputCurrent C BG 0.1 F m VREF V ideoDAC R BIAS 2550 W IBIAS RLO AD 499 W IOUT Buffer VFB TVOUT TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 A.
www.ti.com PRODUCT PREVIEW DIN<9:0> DACDigitalInput C BG 0.1 F m VREF VideoDACandBuffer R BIAS 2550 Ω IBIAS R fb = 1000 Ω IOUT VFB TVOUT R out =1070 Ω TVmonitor .
www.ti.com PRODUCT PREVIEW 5.10 USB 2.0 5.10.1 USB2.0 Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 DM355 includes a US.
www.ti.com PRODUCT PREVIEW t r t f V CR S 90%V OH 10%V OL USB_DM USB_DP t per − t jr V SS_USB_REF USB_R1 USB 10K ±1% W TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-33. USB2.
www.ti.com PRODUCT PREVIEW 5.11 Universal Asynchronous Receiver/Transmitter (UART) 5.11.1 UART Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The contains 3 separate UART modules (1 with hardware flow control).
www.ti.com PRODUCT PREVIEW 3 2 Start Bit DataBits UART_TXDn UART_RXDn 5 DataBits Bit Start 4 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-35.
www.ti.com PRODUCT PREVIEW 5.12 Serial Port Interface (SPI) 5.12.1 SPI Electrical Data/Timing SPIx_CLK (ClockPolarity=0) 1 2 3 SPIx_CLK (ClockPolarity=1) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The contains 3 separate SPI modules.
www.ti.com PRODUCT PREVIEW SPI_CLK (ClockPolarity=0) SPI_CLK (ClockPolarity=1) SPI_DI (Input) SPI_DO (Output) 4 MSBIN DA T A LSBIN LSBOUT MSBOUT DA T A 9 10 8 6 5 7 SPI_E.
www.ti.com PRODUCT PREVIEW SPI_CLK (ClockPolarity=0) SPI_CLK (ClockPolarity=1) SPI_DI (Input) SPI_DO (Output) 13 MSBIN DA T A LSBIN LSBOUT MSBOUT DA T A 17 15 14 16 SPI_E.
www.ti.com PRODUCT PREVIEW 5.13 Inter-Integrated Circuit (I2C) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The inter-integrated circuit (I2C) module provides an interface between and other devices compliant with Philips Semiconductors Inter-IC bus (I 2 C-bus) specification version 2.
www.ti.com PRODUCT PREVIEW 5.13.1 I2C Electrical Data/Timing 10 8 4 3 7 12 5 6 14 2 3 13 Stop Start Repeated Start Stop SDA SCL 1 1 1 9 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.13.1.1 Inter-Integrated Circuits (I2C) Timing Table 5-33.
www.ti.com PRODUCT PREVIEW 23 19 18 22 20 21 17 18 28 Stop Start Repeated Start Stop SDA SCL 16 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-34. Switching Characteristics for I2C Timings (1) (see Figure 5-40 ) DM355 STANDARD NO.
www.ti.com PRODUCT PREVIEW 5.14 Audio Serial Port (ASP) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 DM355 includes two separate ASP controllers. The primary use for the audio serial port (ASP) is for audio interface purposes.
www.ti.com PRODUCT PREVIEW 5.14.1 ASP Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.14.1.1 Audio Serial Port (ASP) Timing Table 5-35. Timing Requirements for ASP (1) (see Figure 5-41 ) DM355 NO.
www.ti.com PRODUCT PREVIEW Bit(n-1) (n-2) (n-3) Bit0 Bit(n-1) (n-2) (n-3) 14 1 1 10 9 3 3 2 8 6 5 4 4 13 (A) 13 (A) A. ParameterNo.13appliestothefirstdatabit only whenXDA TDL Y ≠ 0.
www.ti.com PRODUCT PREVIEW Bit0 Bit(n-1) (n-2) (n-3) (n-4) Bit0 Bit(n-1) (n-2) (n-3) (n-4) M31 M30 M26 M27 M25 M24 CLKX FSX DX DR M33 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-37.
www.ti.com PRODUCT PREVIEW Bit0 Bit(n-1) (n-2) (n-3) (n-4) Bit0 Bit(n-1) (n-2) (n-3) (n-4) M39 M36 M38 M37 M35 M34 CLKX FSX DX DR M40 M42 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-39.
www.ti.com PRODUCT PREVIEW Bit0 Bit(n-1) (n-2) (n-3) (n-4) Bit0 Bit(n-1) (n-2) (n-3) (n-4) M50 M49 M45 M46 M44 M43 CLKX FSX DX DR M52 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-41.
www.ti.com PRODUCT PREVIEW Bit0 Bit(n-1) (n-2) (n-3) (n-4) Bit0 Bit(n-1) (n-2) (n-3) (n-4) M59 M58 M55 M57 M56 M54 M53 CLKX FSX DX DR M62 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-43.
www.ti.com PRODUCT PREVIEW 5.15 Timer 5.15.1 Timer Electrical Data/Timing 1 2 4 4 3 TIM_IN TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The contains four software-programmable timers.
www.ti.com PRODUCT PREVIEW 5.16 Pulse Width Modulator (PWM) 5.16.1 PWM0/1/2/3 Electrical/Timing Data PWM0/1/2/3 1 3 3 2 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DM355 contains 4 separate Pulse Width Modulator (PWM) modules.
www.ti.com PRODUCT PREVIEW 4 VD(CCDC) 4 4 INV ALID INV ALID INV ALID V ALID V ALID V ALID PWM0 PWM1 PWM2 4 INV ALID V ALID PWM3 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-48.
www.ti.com PRODUCT PREVIEW 5.17 Real Time Out (RTO) 5.17.1 RTO Electrical/Timing Data RTO0/1/2/3 1 3 3 2 4 TINT12/TINT34 (Timer3) 4 4 INV ALID INV ALID INV ALID V ALID V ALID V ALID RTO0 4 INV ALID V .
www.ti.com PRODUCT PREVIEW 5.18 IEEE 1149.1 JTAG TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The JTAG (1) interface is used for BSDL testing and emulation of the device. The device requires that both TRST and RESET be asserted upon power up to be properly initialized.
www.ti.com PRODUCT PREVIEW 5.18.1 JTAG Test-Port Electrical Data/Timing RTCK TDO TDI 4 5 TMS 6 7 TCK 1 2 3 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-48. Timing Requirements for JTAG Test Port (see Figure 5-51 ) DM355 NO.
www.ti.com PRODUCT PREVIEW RTCK TDO 13 8 9 10 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-49. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see Figure 5-51 ) DM355 NO.
www.ti.com PRODUCT PREVIEW 6 Revision History TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 This data sheet revision history highlights the technical changes made to the SPRS463 device-specific data sheet to make it an SPRS463A revision.
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 ADDS/CHANGES/DELETES Updated Section 5.9.1 , Video Processing Front-End (VPFE) Updated Section 5.9.1.1 , CCD Controller (CCDC) Updated Section 5.
www.ti.com PRODUCT PREVIEW 7 Mechanical Data 7.1 Thermal Data for ZCE 7.1.1 Packaging Information TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The following table(s) show the thermal resistance characteristics for the PBGA – ZCE mechanical package.
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