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10 Gb/s 3.3V QuadPort™ DSE Family CY7C0430BV CY7C0430CV Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-06027 Rev .
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 2 of 37 Functional Description The Quadport Datapath Switching Element (DSE) family offers four ports that may be clocked at independ ent frequencies from one another . Each port can read or write up to 133 MHz [1] , giving the device up to 10 Gb/s of data throughput.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 3 of 37 counter is loaded with an external address when the port’s Counter Load pin (CNTLD ) i s asserted LOW . When the port’s Counter Increment pin (CNTIN C ) is asserted, the addre ss counter will increment on each subsequent LOW-to- HIGH transition of that port’s clock signal.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 4 of 37 Addr . Read Port 1 Operation-Control Logic Block Diagram R/W P1 CE 0P1 CE 1P1 LB P1 OE P1 UB P1 I/O 9P1 –I/O 17P1 I/O 0P1 –I/O 8P1 .
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 5 of 37 Pin Configuration 272-ball Gri d Array (BGA) To p V i e w Note: 4. Central Leads are for thermal dissi pation only .
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 6 of 37 Selection Guide CY7C0430CV –133 CY7C0430CV –100 Unit f MAX2 133 [1] 100 MHz Max Access T ime (Clock to Data) 4.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 7 of 37 CNTRD P1 CNTRD P2 CNTRD P3 CNTRD P4 Cou nter Readback Input . When asserted LOW , the internal address value of the counter will be read back on the address lines. During CNTRD ope ration, both CNTLD and CNTINC must be HIGH.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 8 of 37 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature .............. ................. . –65 ° C to + 150 ° C Ambient T emperature with Power Applied .
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 9 of 37 AC T est Load Note: 5. T est conditions: C = 10 pF . V TH =1 . 5 V OUTPUT C (a) Normal Load R = 50 Ω Z 0 = 50 Ω [5] 3.0V GND 90% 90% 10% t R t F 10% All Input Pulses (b) Three-St ate Delay V TH =1 .
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 10 of 37 Switching Characteristics Over the Industrial Operating Range [6] Parameter Description CY7C0430BV and CY7 C0430CV Unit –133 –100 Min. Max. Min. Max. f MAX2 [7] Maximum Frequency 133 100 MHz t CYC2 [7] Clock Cycle T ime 7.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 1 1 of 37 t CKLZ [9] Clock HIG H to Output Low-Z 1 1 ns t SINT Clock to INT Set T ime 1 7.5 1 10 ns t RINT Clock to INT Reset T ime 1 7.5 1 10 ns t SCINT Clock to CNTINT Set T ime 1 7.5 1 10 ns t RCINT Clock to CNTINT Reset T ime 1 7.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 12 of 37 Test Clock Test Mode Select TCK TMS Test Data-In TDI Test Data-Out TDO t TCYC t TMSH t TL t TH t TMSS t TDIS t TDIH t TDOX t TDOV Switching W aveforms Master Reset [10] Notes: 10. t S is the set-up time required for all input control signa ls.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 13 of 37 Read Cycle [12, 13, 14, 15, 16] Notes: 12. OE is asynchronousl y controlled; al l other inputs (exclud ing MRST ) are synchronous to the rising clock edge. 13. CNTLD = V IL , MKLD = V IH , CNTINC = x, and MRST = CNTRST = V IH .
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 14 of 37 Bank Select Read [17, 18] Read-to-Write -to-Read (OE = V IL ) [19, 20, 21, 22] Notes: 17. In this depth exp ansion example, B1 repr esents Bank #1 and B2 is Bank #2; Each bank consists of one Qu adPort DSE device from this dat a sheet.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 15 of 37 Read-to-Write -to-Read (OE Controlled) [19, 20, 21, 22] Read with Address Counter Ad vance [23, 24] Notes: 23. CE 0 = OE = LB = UB = V IL ; CE 1 = R/W = CNTRST = MRST = MKLD = MKRD = CNTRD = V IH .
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 16 of 37 Write with Address Counter Advance [24, 25 ] Note: 25. CE 0 = LB = UB = R/W = V IL ; CE 1 = CNTRST = MRST = MKLD = MKRD = CNTRD = V IH.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 17 of 37 Counter Reset [21, 26, 27] Notes: 26. CE 0 = LB = UB = V IL ; CE 1 = MRST = MKLD = MKRD = CNTRD = V IH . 27. No dead cycle exists during counter reset. A Read or W rite cycle may be coincidental with the counter reset.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 18 of 37 Load and R ead Address Co unter [28] Notes: 28. CE 0 = OE = LB = UB = V IL ; CE 1 = R/W = CNTRST = MRST = MKLD = MKRD = V IH . 29. Address in ou tput mode. Host must not be driving addre ss bus after time t CKLZ in next clock cycle.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 19 of 37 Load and R ead Mask Register [32] Notes: 32. CE 0 = OE = LB = UB = V IL ; CE 1 = R/W = CNTRST = MRST = CNTLD = CNTRD = CNTINC =V IH . 33. This is the value of the Mask Register read out on the address lines.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 20 of 37 Port 1 Write to Port 2 Read [34, 35, 36] Notes: 34. CE 0 = OE = LB = UB = CNTLD =V IL ; CE 1 = CNTRST = MRST = M KLD = MKRD = CNTRD = CNTINC =V IH .
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 21 of 37 Counter Interrupt [37, 38, 39] Mailbox Interrup t Timing [40, 41, 42, 43, 44] Notes: 37. CE 0 = OE = LB = UB = V IL ; CE 1 = R/W = CNTRST = MRST = CNTRD = MKRD = V IH . 38. CNTINT is always driven.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 22 of 37 T able 1. Read /Write and Enable Operation (Any Port) [45, 46, 47] Input s Outputs Operation OE CLK CE 0 CE 1 R/W I/O 0 – I/O 17 X H X X High-Z Deselected X X L X High-Z Deselected XL H L D IN Wri te LL H H D OUT Read H X L H X High-Z Outputs Disabled T able 2.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 23 of 37 Master Reset The QuadPort DSE device underg oes a complete reset by taking its Master Reset (MRST ) input LOW .
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 24 of 37 Address Counter Control Operations Counter enable inputs are provided to stall the operation of the address input and utilize the inte rnal address generated by the internal counter for the fast i nterleaved memory applications.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 25 of 37 Counter-Mask Register The burst counter has a mask regi ster that controls when and where the counter wraps.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 26 of 37 address the entire memory array (depend on the value of the mask register) and loop back to location 0.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 27 of 37 The EXTEST , and SAMPLE/PREL OAD instructions can be used to ca pture th e content s of t he Input and Outpu t ring.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 28 of 37 number of TCK cycl es depending on the TC K and CLKBIST frequency . t CYC is total number of TCK cycles required to run MBIST . SPC is the Synchronizati on Padding Cycles (4–6 cycles).
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 29 of 37 T AP Controller St ate Diagram (FSM) [53] Note: 53. The “0”/”1” next to each stat e represents t he value at TMS at the risi ng edge of TCK.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 30 of 37 JT AG/BIST T AP Controller Block Diagram T able 4. Identificatio n Register Definitions Instruction Field Va l u e Description Revisio.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 31 of 37 T able 5. Scan Reg isters Sizes Register Name Bit Size Instruction (IR) 4 Bypass (BYR) 1 Identification (IDR) 32 MBIST Control (MCR) 2 MBIST Result (MRR) 25 MBIST Debug (MDR) 100 Boundary Scan (BSR) 39 2 T able 6.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 32 of 37 001001 chkr_r All ports read topological checkerboard data. 001000 n_ chkr_w Port 1 write inverse topological checkerboard data. 01 10 00 n_chkr_r All ports read inverse topological checkerboard data.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 33 of 37 T able 9. Boundary Scan Order Cell # Signal Name Bump (Ball) ID 2 A0_P4 K20 4 A1_P4 J19 6 A2_P4 J18 8 A3_P4 H20 10 A4_P4 H19 12 A5_P4 .
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 34 of 37 166 IO2_P1 Y5 168 IO3_P1 W5 170 IO4_P1 Y4 172 IO5_P1 W4 174 IO6_P1 Y3 176 IO7_P1 W3 178 IO8_P1 Y2 180 IO0_P2 V9 182 IO1_P2 Y10 184 IO2.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 35 of 37 330 IO13_P2 A4 332 IO14_P2 B4 334 IO15_P2 A3 336 IO16_P2 B3 338 IO17_P2 A2 340 IO9_P1 C9 342 IO10_P1 A10 344 IO1 1_P1 B9 346 IO12_P1 A.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 36 of 37 © Cypress Semi conductor Corpora tion, 2006. The i nformation cont ained here in is subject to ch ange withou t notice. Cypress S emic onductor Corporation assu mes no responsibility for the use of any circuitry o ther than circui try embodied i n a Cypress prod uct.
CY7C0430BV CY7C0430CV Document #: 38-06027 Rev . *B Page 37 of 37 Document History Page Document Title: CY7C0430BV , CY7C0430CV 10 Gb/s 3.3V QuadPort DSE Family Document Number: 38 -06027 REV .
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