Gebruiksaanwijzing /service van het product CY7C1472BV25 van de fabrikant Cypress
Ga naar pagina of 29
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-15032 Rev .
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 2 of 29 Logic Block Diagram – CY7C1470BV25 (2M x 36) Logic Block Diagram – CY7C1472BV25 (4M x 18) A0, A1, A C MODE BW a .
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 3 of 29 Logic Block Diagram – CY7C1474BV25 (1M x 72) A0, A1, A C MODE CE1 CE2 CE3 OE READ LOGIC DQ s DQ P a DQ P b DQ P c .
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 4 of 29 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQa .
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 5 of 29 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm ) Pinout CY7C1470BV25 (2M x 36) CY7C1472BV25 (4M x 18.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 6 of 29 Pin Configurations (continued) CY7C1474BV25 (1M × 72) 209-Ball FBGA (14 x 22 x 1.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 7 of 29 T able 1. Pin Definitions Pin Name IO T ype Pin Description A0 A1 A Input- Synchronous Address In puts Used to Select One of the Address Locations . Sampled at the rising edge of the CLK.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 8 of 29 Functional Overview The CY7C1470BV25, CY7C1472BV25 , and CY7C1474BV25 are synchronous-pipel ined Burst NoBL SRAMs designed specif- ically to eliminate wait states during read or w rite transitions.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 9 of 29 access (read, write, or deselect) is latched into the Address Register (provided the ap propriate control signals are asserted).
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 10 of 29 T a ble 4. T ruth T able The truth table for CY7C1470BV25, CY7C1472BV25, and CY7C1474 BV25 follows.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 1 1 of 29 T able 5. Partial Write Cycle Description The partial write cycle description for CY7C1470 BV25, CY7C1472BV25, and CY7 C1474BV25 follows.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 12 of 29 IEEE 1 149.1 Serial Boun dary Scan (JT AG) The CY7C1470BV25, CY7C1472BV25 , and CY7C1474BV25 incorporates a serial boundary sca n test access port (T AP). This port operates in accordance with IEEE S tandard 1 149.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 13 of 29 Instruction Register Three-bit instructions can be serially loa ded into the instruction register . Thi s register is loaded when it is placed b etween the TDI and TDO balls as shown i n the “T AP Controller Block Diagram” on page 12 .
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 14 of 29 possible to capture all o ther signals and simply ig nore the value of the CLK captured in the boundary scan register . After the data is captured, it is possible to shift out the data by putting the T AP into the Shif t-DR state.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 15 of 29 T AP AC Switching Characteristics Over the Operating Range [9, 10] Parameter Descrip tion Min Max Unit Clock t TCYC.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 16 of 29 2.5V T AP AC T est Conditions Input pulse levels .................... .............. ........... .... V SS to 2.5V Input rise and fall time ............... ..........
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 17 of 29 T able 8. Iden tification Codes Instruction Code Description EXTEST 000 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 18 of 29 Boundary Scan Exit Order (4M x 18) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165 -B all ID 1 D 21.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 19 of 29 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature ...................
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 20 of 29 I SB3 Automatic CE Power Down Current—CMOS Inputs Max. V DD , Device Deselected, V IN ≤ 0.3V or V IN > V DDQ − 0.3V , f = f MAX = 1/t CYC 4.0-ns cycle, 250 MHz 200 mA 5.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 21 of 29 Switching Characteristics Over the Operating R ange. Timing reference is 1.25V when V DDQ = 2.5V . T est conditions shown in (a) of “AC T est Loads and W aveforms” on page 20 unless otherwise noted.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 22 of 29 Switching W aveforms Figure 6 shows read-write timing waveform. [19, 20, 21] Figure 6.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 23 of 29 Figure 7 shows NOP , ST ALL and D ESELECT Cycles waveform. [19, 20, 22] Figure 7. NOP , ST ALL and DESELECT Cycles Figure 8 shows ZZ Mode timing wavefo rm. [23, 24] Figure 8.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 24 of 29 Ordering Information Not all of the speed, package and temperatur e ranges are available. Please contact y our local sales represe ntative or visit www .cypress.com for actual products offered.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 25 of 29 250 CY7C1470BV25-250AXC 51-85 050 100-pin Thin Quad Flat Pack (1 4 x 20 x 1.4 mm) Pb-Free Commercial CY7C1472BV25-250AXC CY7C1470BV25-250BZC 51-85165 165-ball Fin e-Pitch Ball Grid Array (15 x 17 x 1.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 26 of 29 Package Diagrams Figure 9. 100-Pin Thin Plastic Qu ad Flatpack (14 x 20 x 1.4 mm), 51-85050 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 27 of 29 Figure 10. 165-Ball F BGA (15 x 17 x 1 .4 mm), 51-85165 Package Diagrams (continued) A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.45±0.05(165X) Ø0.25 M C A B Ø0.
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Document #: 001-15032 Rev . *D Page 28 of 29 Figure 1 1. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167 Package Diagrams (continued) 51-85167-* * [+] Feedback.
Document #: 001-15032 Rev . *D Re vised February 29, 2008 Page 29 of 29 NoBL and No Bu s Latency are trademar ks of Cypress Semicondu ctor Co rporation. ZBT is a trademark of Integrat ed Device T echn ology , Inc. All products and company names me ntioned in this document may be the tr ademarks of their respe ctive hold er s.
Een belangrijk punt na aankoop van elk apparaat Cypress CY7C1472BV25 (of zelfs voordat je het koopt) is om de handleiding te lezen. Dit moeten wij doen vanwege een paar simpele redenen:
Als u nog geen Cypress CY7C1472BV25 heb gekocht dan nu is een goed moment om kennis te maken met de basisgegevens van het product. Eerst kijk dan naar de eerste pagina\'s van de handleiding, die je hierboven vindt. Je moet daar de belangrijkste technische gegevens Cypress CY7C1472BV25 vinden. Op dit manier kan je controleren of het apparaat aan jouw behoeften voldoet. Op de volgende pagina's van de handleiding Cypress CY7C1472BV25 leer je over alle kenmerken van het product en krijg je informatie over de werking. De informatie die je over Cypress CY7C1472BV25 krijgt, zal je zeker helpen om een besluit over de aankoop te nemen.
In een situatie waarin je al een beziter van Cypress CY7C1472BV25 bent, maar toch heb je de instructies niet gelezen, moet je het doen voor de hierboven beschreven redenen. Je zult dan weten of je goed de alle beschikbare functies heb gebruikt, en of je fouten heb gemaakt die het leven van de Cypress CY7C1472BV25 kunnen verkorten.
Maar de belangrijkste taak van de handleiding is om de gebruiker bij het oplossen van problemen te helpen met Cypress CY7C1472BV25 . Bijna altijd, zal je daar het vinden Troubleshooting met de meest voorkomende storingen en defecten #MANUAl# samen met de instructies over hun opplosinge. Zelfs als je zelf niet kan om het probleem op te lossen, zal de instructie je de weg wijzen naar verdere andere procedure, bijv. door contact met de klantenservice of het dichtstbijzijnde servicecentrum.
