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72-Mbit QDR™-II SRAM 4-W ord Burst Architecture CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-05363 Rev .
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 2 of 32 Logic Block Diagra m (CY7C151 1V18) Logic Block Diagram (CY7C1526V18) 2M x 8 Array CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Read Add.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 3 of 32 Logic Block Diagram (CY7C1513V18) Logic Block Diagram (CY7C1515V18) CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 4 of 32 Pin Configuration The pin configuration for CY7C151 1V18 , CY7C 1526V18, CY7C1513V18 , and CY7C1515V18 follow .
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 5 of 32 CY7C1513V18 (4M x 1 8) 123456789 10 11 A CQ V SS /144M AW P S BWS 1 K NC/28 8M RPS AA C Q B NC Q9 D9 .
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 6 of 32 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks when valid write operations are active.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 7 of 32 CQ Echo Clock CQ Referenced with Respect to C . This is a free running clock and is synchronized to the input clock for output data (C) of the QDR-II. In the single clock mode , CQ is generated wi th respect to K.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 8 of 32 Functional Overview The CY7C151 1V18, C Y7C1526V18, CY7C1513V18, CY7C1515V18 are synchronous pipeline d Burst SRAMs with a read port and a write port. The read port is dedicated to rea d operations and the write port is dedicated to write operations.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 9 of 32 Concurrent T ransactions The read and write ports on the CY7C151 3V18 operates completely independe ntly of one another .
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 10 of 32 Application Example Figure 1 shows four QDR-II used in an application. Figure 1. Application Example T ruth T a ble The truth table for CY7C151 1V18, CY7C1526V 18, C Y7C1513V18, and C Y7C1515V18 follows.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 1 1 of 32 Write Cycle Descriptions The write cycle description table for CY7C151 1V18 and CY 7C1513V18 follows.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 12 of 32 Write Cycle Descriptions The write cycle description t able for CY7C1 515V18 follows.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 13 of 32 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 14 9.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 14 of 32 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister .
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 15 of 32 T AP Controller St ate Diagram The state diagram for the T AP controller follows.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 16 of 32 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [12, 13, 14] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V olt age I OH = − 2.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 17 of 32 T AP AC Switching Characteristics Over the Operating Range [15, 16] Parameter Description Min Max Un.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 18 of 32 Identification R egi ster Definitions Instruction Field Va l u e Description CY7C151 1V18 C Y7C1526V18 CY7C1513V18 C Y7C1515V18 Revision Numb er (31:29) 000 000 000 000 V ersion number .
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 19 of 32 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bum p ID 0 6R 28 10G 56 6A 84 1J.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 20 of 32 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operations. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (All other inputs can be HIGH or LOW).
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 21 of 32 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature ....
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 22 of 32 I DD [21] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200MHz (x8) 655 mA (x9.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 23 of 32 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 24 of 32 Switching Characteristics Over the Operating Range [22, 23] Cypress Parameter Consor tium Parameter .
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 25 of 32 Output T imes t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data V alid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold af ter Output C/C Clock Rise (Active to Active) –0.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 26 of 32 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 8, 29, 30 ] K 1 2 34 5 6 7 RPS WPS A .
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 27 of 32 Ordering Information Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www .
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 28 of 32 250 CY7C151 1V18-250BZC 51-85195 1 65-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1526V18-250BZC CY7C1513V18-250BZC CY7C1515V18-250BZC CY7C151 1V18-25 0BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 29 of 32 167 CY7C151 1V18-167BZC 51-85195 1 65-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1526V18-167BZC CY7C1513V18-167BZC CY7C1515V18-167BZC CY7C151 1V18-16 7BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 30 of 32 Package Diagram Figure 6. 165-ball FBGA (15 x 17 x 1.
CY7C151 1V18, CY7C1526V18 CY7C1513V18, CY7C1515V18 Document Number: 38-05363 Rev . *F Page 31 of 32 Document History Page Document Title: CY7C151 1V18/CY7 C152 6V18/CY7C1513V18/CY7C1515V18, 72-Mb it QDR™-II SRAM 4-Word Burst Archi- tecture Document Number: 38-05363 REV .
Document Number: 38-05363 Rev . *F Revised August 06, 2008 Page 32 of 32 QDR RAMs and Qua d Data Ra te RA Ms comprise a ne w fam i ly of pr od uct s developed by Cypress, Hit a chi, IDT , NEC, an d S am sun g. A ll pr odu ct a nd comp any names mentioned in this document are the tradem arks of their r es pective hold ers.
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