Gebruiksaanwijzing /service van het product CY7C1518JV18 van de fabrikant Cypress
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72-Mbit DDR-II SRAM 2-W ord Burst Architecture CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-12559 Rev .
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 2 of 26 Logic Block Diagram (CY7C1516JV18) Logic Block Diagram (CY7C1527JV18) Wri te Reg Wri te Reg CLK A (21:0) Gen. K K Control Logic Address Register Read Add.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 3 of 26 Logic Block Diagram (CY7C1518JV18) Logic Block Diagram (CY7C1520JV18) Wri te Reg Writ e Reg CLK A (21:0) Gen. K K Control Logic Address Register Read Add.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 4 of 26 Pin Configuration The pin configuration for CY7C1516JV18, CY7C1527 JV18, CY7C1518JV18, and CY7C1520JV18 follow .
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 5 of 26 CY7C1518JV18 (4 M x 18) 123456789 10 11 A CQ AA R / W BWS 1 K NC/14 4M LD AA C Q B NC DQ9 NC A NC.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 6 of 26 Pin Definitions Pin Name IO Pin Descripti on DQ [x:0] Input Output- Synchronous Dat a Input Output S ignals . Inputs are sampled on the rising edge of K and K clocks during valid write operations.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 7 of 26 CQ Output Clock CQ is Referenced with Respect to C . This is a free running clock and is synchronized to the input cl ock for output data (C) of the DDR-II.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 8 of 26 Functional Overview The CY7C1516JV18, CY7C152 7JV18, CY7C1518JV18, and CY7C1520JV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and a half cycles when DOFF pi n is tied HIGH.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 9 of 26 Depth Expansion Depth expansion requires replicating the LD control signal for each bank. All other co ntrol signals can be common between banks as appropriate.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 10 of 26 T ruth T able The truth table for the CY7C1516JV18, CY7C1 527JV1 8, CY7C1518JV18, and CY7C1520JV18 follow s.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 1 1 of 26 Write Cycle Descriptions The write cycle description tabl e for CY7C1527JV18 follows. [2, 8] BWS 0 K K Comments L L–H – During the data portion of a write sequence, th e single byte (D [8:0] ) is written into the device.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 12 of 26 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 13 of 26 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister .
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 14 of 26 T AP Controller St ate Diagram The state diagram for the T AP controller follows.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 15 of 26 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 16 of 26 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Ma.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 17 of 26 Identification R egi ster Definitions Instruction Field Va l u e Description CY7C1516JV18 CY7C1527JV18 CY7C1 518JV18 CY7C1520JV18 Revision Numb er (31:29) 000 000 000 00 0 V ersion numbe r .
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 18 of 26 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 19 of 26 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be power ed up and initialized in a predefined manner to prevent unde fined operations. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (all other inputs can be HIGH or LOW).
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 20 of 26 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature .
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 21 of 26 AC Electrical Characteristics Over the Operating Range [1 1] Parameter Description T est Cond iti ons Min Ty p Max Unit V IH Input HIGH V oltage V REF + 0.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 22 of 26 Switching Characteristics Over the Operating Range [20] Cypress Parameter Consor tium Parameter .
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 23 of 26 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 6, 27, 28 ] READ READ READ NOP NO.
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 24 of 26 Ordering Information Not all of the speed, package, and temper ature ranges are available. Please cont act your local sale s representative or visit www .
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document Number: 001-12559 Rev . *D Page 25 of 26 Package Diagram Figure 6. 165 - B a ll FBGA (15 x 17 x 1.
Document Number: 001-12559 Rev . *D Revised June 25, 2008 Page 26 of 26 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s develope d by Cypress, IDT , NEC, Renesas, and Samsung. A ll pr oduct an d company n ames mentione d in this do cument are the tr ad emarks of their respe ctive hold ers.
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