Gebruiksaanwijzing /service van het product CY7C1541V18 van de fabrikant Cypress
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72-Mbit QDR™-II+ SRAM 4-W ord Burst Architecture (2.0 Cycle Read Latency) CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-05389 Rev .
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 2 of 28 Logic Block Diagram (CY7C1541V18) Logic Block Diagram (CY7C1556V18) 2M x 8 Array CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Read Add. Decode Read Data Reg.
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 3 of 28 Logic Block Diagram (CY7C1543V18) Logic Block Diagram (CY7C1545V18) 1M x 18 Array CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add.
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 4 of 28 Pin Configuration The pin configuration for CY7C1541V18, CY7C 1556 V18, CY7C1543V18, and CY7C15 45V18 follow .
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 5 of 28 CY7C1543V18 (4M x 1 8) 123456789 10 11 A CQ NC/144M A WPS BWS 1 K NC/288M RPS AA C Q B NC Q9 D9 A NC .
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 6 of 28 Pin Definitions Pin Name IO Pin Descripti on D [x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active .
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 7 of 28 ZQ Input Output Imp edance Matching Input . This input is used to tune the dev ice outputs to the system data bus impedance. CQ, CQ and Q [x:0] output impedance are set to 0.
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 8 of 28 Functional Overview The CY7C1541V18, CY7C1556V18, CY7C1 543V18, and CY7C1545V18 are synchronou s pipelined burst SRAMs equipped with a read port and a write p ort.
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 9 of 28 Depth Exp ansion The CY7C1543V18 has a port select in put for each port. This enables for easy depth e xpansion. Both port selects are sampled on the rising edge of the positive input clock only (K).
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 10 of 28 The truth table for CY7C1541V18, CY7C1556V18, CY7C15 43V18, and CY7C1545V18 follows.
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 1 1 of 28 The write cycle description t able for CY7C1 556V18 follows. [3, 1 1] Write Cycle Descriptions BWS 0 K K L L –H – During the Data portion of a write sequence, the single byte (D [8:0] ) is written int o th e de vi ce .
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 12 of 28 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 14 9.
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 13 of 28 between the TDI and TDO pins and shifts the IDCODE out of the device when the T AP controller enters the Shift-DR state.
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 14 of 28 The state diagram for the T AP controller follows. [12] T AP Controller St ate Diag ram TEST -LOGIC .
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 15 of 28 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [13, 14, 15] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 16 of 28 T AP AC Switching Characteristics Over the Operating Range [16, 17] Parameter Description Min Max Un.
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 17 of 28 Identification R egi ster Definitions Instruction Field Va l u e De scription CY7C1541V18 CY7C1556V18 C Y7C1543V18 CY7C15 45V18 Revision Numb er (31:29) 000 000 000 000 V ersio n numbe r .
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 18 of 28 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J .
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 19 of 28 Power Up Sequence in QDR-II+ SRAM QDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operations. During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of st able clock.
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 20 of 28 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature ....
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 21 of 28 I SB1 Automatic Power down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ V IL .
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 22 of 28 Thermal Resist ance T ested initially and after any design or process change that may affect these parameters.
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 23 of 28 Switching Characteristics Over the Operating Range [23, 24] CY Parameter Consor tium Parameter Descr.
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 24 of 28 Switching W aveforms Read/Write/Deselect Sequence [31, 32, 33] Figure 5.
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 25 of 28 Ordering Information Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www .
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 26 of 28 300 CY7C154 1V18-300BZC 51-85195 165-Ball Fine Pi tch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1556V18-300BZC CY7C1543V18-300BZC CY7C1545V18-300BZC CY7C1541V18-300BZXC 51-85195 165-Ball Fine Pi tch Ball Grid Array (15 x 17 x 1.
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Document Number: 001-05389 Rev . *F Page 27 of 28 Package Diagram Figure 6. 165-ball FBGA (15 x 17 x 1.
Document Number: 001-05389 Rev . *F Revised March 06, 2008 Page 28 of 28 QDR RAMs an d Quad Data R ate RAMs comprise a new family of products devel oped by Cypress, IDT , NEC, Renesas, and Samsung. All pr oduct and comp any names ment ioned in this do cument are the tr ad emarks of their respe ctive hold er s.
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