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72-Mbit QDR™-II+ SRAM 4-W ord Burst Architecture (2.5 Cycle Read Latency) with ODT PRELIMINARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1 709 • 408-943-2600 Document Number: 001-15887 Rev .
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 2 of 29 Logic Block Diagram (CY7C2561KV18) Logic Block Diagram (CY7C2576KV18) 2M x 8 Array CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Read Add.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 3 of 29 Logic Block Diagram (CY7C2563KV18) Logic Block Diagram (CY7C2565KV18) 1M x 18 Array CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 4 of 29 Pin Configuration The pin configuration for CY7C2561KV18, CY7C 2576 KV18, CY7C2563KV18, and CY7C2565KV18 follow . [2] 165-Ball FBGA (13 x 15 x 1.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 5 of 29 CY7C2563KV18 (4M x 18) 123456789 10 11 A CQ NC/144M A WPS BWS 1 K NC/288M RPS AA C Q.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 6 of 29 T able 2. Pin Definitions Pin Name IO Pin Descripti on D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks when valid write operations are active.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 7 of 29 K Input Clock Positive Input Clock Input . The rising edge of K is used to capture synchronous inputs to the device and to dri ve out data through Q [x:0] .
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 8 of 29 Functional Overview The CY7C2561KV18, CY7C257 6KV18, CY7C2563KV18, CY7C2565KV18 are synchronous pipelined Burst SRAMs equipped with a read port and a write p ort.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 9 of 29 Read access and write access must be scheduled such th at one transaction is initiated on any clock cycle. If both port s are selected on the same K clock rise, th e arbitration depends on the previous state of the SRAM.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 10 of 29 Application Example Figure 1 shows two QDR-II+ used in an application. Figure 1. Application Example T able 3. T ru th T abl e The truth table for CY7C2561KV18, CY7C2576KV 18, CY7C2563KV18, and CY7C2565KV18 follo ws.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 1 1 of 29 T able 4. Write Cycle Descriptions The write cycle description table for CY7C2561KV18 and CY7C2563KV18 fo llows.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 12 of 29 T able 6. Write Cycle Descriptions The write cycle description tabl e for CY7C2565KV18 follows.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 13 of 29 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA package.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 14 of 29 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister .
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 15 of 29 Figure 2. T AP Controller St ate Diagram The stat e diagram for the T AP controller follows.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 16 of 29 Figure 3. T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [14, 15, 16] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V olt age I OH = − 2.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 17 of 29 T AP AC Switching Characteristics Over the Operating Range [17, 18] Parameter Descr.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 18 of 29 T able 7. Identification Register Definitions Instruction Field Va l u e Description CY7C2561KV18 CY7C2576KV18 CY7 C2563KV18 CY7C2565KV18 Revision Numb er (31:29) 000 000 000 000 V ersion number .
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 19 of 29 T able 10. Boundary Scan Ord er Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bum.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 20 of 29 Power Up Sequence in QDR-II+ SRAM QDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operation s.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 21 of 29 Maximum Ratings Exceeding maximum ratin gs may impair the useful life of the device. These user guidelines are not teste d. S torage T emperature .
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 22 of 29 I SB1 Automatic Power down Current Max V DD , Both Ports Deselected, V IN ≥ V IH .
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 23 of 29 AC T est Loads and W aveforms 1.25V 0.25V R = 50 Ω 5p F INCLUDING JIG AND SCOPE ALL INPUT PULSES Device R L = 50 Ω Z 0 = 50 Ω V REF = 0.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 24 of 29 Switching Characteristics Over the Operating Range [24, 25] Cypress Parameter Conso.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 25 of 29 Switching W aveforms Read/Writ e/Deselect Sequence [32, 33, 34] Figure 6.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 26 of 29 Ordering Information The following table lists all possible speed, package and temperat ure range options supported fo r these devi ces.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 27 of 29 450 CY7C256 1KV18-450BZC 51-851 80 165-Ball Fine Pi tch Ball Grid Array (13 x 15 x 1.
PRELIMIN ARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev . *E Page 28 of 29 Package Diagram Figure 7. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø 0 .
Document Number: 001-15887 Rev . *E Revised April 24, 2009 Page 29 of 29 QDR RAMs an d Quad Dat a Rate RAMs co mprise a ne w family of products d eveloped by Cy press, IDT , NEC, Re nesas, and Sam sung. All pr oduct and co mpany names mentione d in this do cument are the tr ademark s of their re specti ve holders .
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