Gebruiksaanwijzing /service van het product CY7C1361C van de fabrikant Cypress Semiconductor
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9-Mbit ( 256K x 36/512K x 18 ) Flow-Throu g h SRAM CY7C1361C CY7C1363C Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05541 Rev .
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 2 of 31 ADDRESS REGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 ENABLE REGISTER SENSE AMPS OUTPUT BUFFERS INPUT REGISTERS MEMORY ARRAY MODE A [1:0] ZZ.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 3 of 31 Pin Configurations A A A A A 1 A 0 NC NC V SS V DD NC A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 4 of 31 Pin Configurations (continued) A A A A A 1 A 0 NC NC V SS V DD NC NC A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ .
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 5 of 31 Pin Configurations (continued) 234 5 67 1 A B C D E F G H J K L M N P R T U V DDQ NC/288M NC/144M DQP C DQ C DQ D DQ C DQ D AA A A ADSP V.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 6 of 31 Pin Configurations (continued) 165-Ball FBGA Pinout ( 3 Chip Enable) CY7C1361C (256 K x 36) 23 4 567 1 A B C D E F G H J K L M N P R TDO .
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 7 of 31 Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inpu ts used to select one of the address location s. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 [2] are sampled active .
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 8 of 31 V SS Ground Ground for the core of the device . V SSQ I/O Ground Ground for the I /O circuitry . TDO JT AG serial outp ut Synchronous Serial data-out to the JT AG circuit . Delivers d ata on the negative edge of TCK.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 9 of 31 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge o f the clock. Maximum access delay from the clock rise (t CDV ) is 6.5 ns (133-MHz device).
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 10 of 31 ZZ Mode Electrical Characteristics Parameter Description T est Con ditions Min. Max. Un it I DDZZ Sleep mode standby current ZZ > V DD – 0.2V Comm/ind’l 50 mA Automotive 60 mA t ZZS Device operation to ZZ ZZ > V DD – 0.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 1 1 of 31 Partial T ruth T able for Read/Write [3, 8] Function (CY7C136 1C) GW BWE BW D BW C BW B BW A Read H H X X X X R e a d H L HHHH Write By.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 12 of 31 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1361C/CY7C1363C incorpora tes a serial boundary scan test access port (T AP) in the BGA package only . The TQFP package does not offer this functionality .
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 13 of 31 TDI and TDO ba lls as show n in the T ap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE in struction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in th e pre v i o us section.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 14 of 31 PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection o f another boundary scan test operation.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 15 of 31 3.3V T AP AC T est Conditions Input pulse levels ............ .............. .............. ........ V SS to 3.3V Input rise and fall times ......... .............. ......................
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 16 of 31 Scan Register Sizes Register Name Bit Size (x 36) Bit Size (x 18) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (1 19-ball BGA.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 17 of 31 1 19-Ball BGA Boundary Scan Order CY7C1361C (256K x 36) CY7C13 63C (512K x 18) Bit # ball ID Signal Name Bit # ball ID Signal Name Bit #.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 18 of 31 165-Ball FBGA Boundary Scan Order CY7C1361C (256K x 36) CY7C1363C (512K x 18) Bit # ball ID Signal Name Bit # ball ID Signal Name Bit # .
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 19 of 31 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ..... –65°C to + 150°C Ambient T emperature with Power Applied .
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 20 of 31 Cap acitance [15] Parameter Description T est Conditions 100 TQ FP Max. 11 9 B G A Max.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 21 of 31 Switching Characteristics Over the Operating Range [20, 21] Parameter De scription –133 –100 Unit Min. Max. Min. Max. t POWER V DD (T ypical) to the first Access [1 6] 11 m s Clock t CYC Clock Cycle T ime 7.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 22 of 31 Timing Diagrams Read Cycle Timing [22] Note: 22. On this diagram, when CE is L OW: CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW. When CE is HIGH: CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 23 of 31 Write Cycle T iming [22, 23] Note: 23. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW X LOW.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 24 of 31 Read/Write Cycle Timing [22, 24, 25 ] Notes: 24. The data bus (Q) remain s in high-Z following a WRIT E cycl e, unless a new read access is initiated by ADSP or ADSC .
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 25 of 31 ZZ Mode T iming [26, 27] Notes: 26. Device must be deselected when ente ring ZZ mode. See Cycle Descr iptions t ab le for all possible signal conditi ons to deselect the device. 27. DQs are in high -Z when exiting ZZ sl eep mode.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 26 of 31 Ordering Information Not all of the speed, package and temperature ranges are av ailable. Please contact your local sales representative or visit www .cypress .com for actua l products offered .
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 27 of 31 100 CY7C1361C-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Fre e (3 Chip Enable) Commercial CY7C1363C-100AXC CY7C1361C-100AJXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 28 of 31 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 29 of 31 Package Diagrams (continued) 1.27 20.32 2 16 5 4 37 L E A B D C H G F K J U P N M T R 12.00 19.50 30° TYP. 2.40 MAX. A1 CORNER 0.70 REF. U T R P N M L K J H G F E D C A B 21 43 65 7 Ø1.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 30 of 31 © Cypress Semi con duct or Cor po rati on , 20 06 . The information contained he re i n is su bject to change without notice. C ypr ess S em i c on duct or Corpo ration assu mes no resp onsib ility for th e u se of any circuitry o ther than circui try embodied i n a Cypress prod uct.
CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 31 of 31 Document History Page Document Title: CY7C1361C/CY7C1363C 9-Mbit (256K x 36/5 12K x 18) Flow-Through SRAM Document Number: 38-05541 REV .
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