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AMD Geode™ SC3200 Processor Data Book AMD Geode™ SC3200 Processor Data Book February 2007 Publicat ion ID: 32581C.
2 AMD Geode™ SC3200 Processor Data Book © 2007 Advanced Micr o De vices, Inc. All r ights reser ved. The contents of this docu ment are pr o vided in connection with Adv anced Micro Devices , Inc.
AMD Geode™ SC3200 Processor Data Book 3 Contents 32581C Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . .
4 AMD Geode™ SC3200 Processor Data Book Contents 32581C 6.0 Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AMD Geode™ SC3200 Processor Data Book 5 List of Figures 32581C List of Figures Figure 1-1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3-1. Signal Groups .
6 AMD Geode™ SC3200 Processor Data Book List of Figures 32581C Figure 7-6. Capture Video Mode Weave Example Using Two Vid eo Frame Buffers . . . . . . . . . . . . . . . 316 Figure 7-7. Video Block Diagr am . . . . . . . . . . . . . . . . . . . . . .
AMD Geode™ SC3200 Processor Data Book 7 List of Figures 32581C Figure 9-47. AC97 Reset Timi ng Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Figure 9-48. AC97 Sync Timin g Diagram . . . .
8 AMD Geode™ SC3200 Processor Data Book List of Figures 32581C.
AMD Geode™ SC3200 Processor Data Book 9 List of T ables 32581C List of T ab les Table 2-1. SC3200 Memo ry Controller Register Summ ary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 2-2. SC3200 Memo ry Controller Registers .
10 AMD Geode™ SC3200 Processor Data Book List of T ables 32581C Table 5-29. Banks 0 and 1 - Common Control and St atus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 5-30. Bank 1 - CEIR Wakeup Config uration and C ontrol Regist ers .
AMD Geode™ SC3200 Processor Data Book 11 List of T ables 32581C Table 6-22. F3: PCI Heade r Registers fo r Audio Support Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1 Table 6-23. F3BAR0: Audio Support Regis ters Summary . . . . .
12 AMD Geode™ SC3200 Processor Data Book List of T ables 32581C Table 9-19. PCI Timing Para meters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Table 9-20. Measurem ent Condition P arameters .
AMD Geode™ SC3200 Processor Data Book 13 1 Overview 32581C 1.0 Ov er vie w 1.1 General Description The AMD Geode™ SC3200 processor is a member of the AMD Geode f amily of fully integrated x86 system chips .
14 AMD Geode™ SC3200 Processor Data Book Overview 32581C 1.2 Features General Features ■ 32-Bit x86 processor , up to 266 MHz, with MMX instruc- tion set suppor t ■ Memory controller with 64-bit.
AMD Geode™ SC3200 Processor Data Book 15 Overview 32581C ■ PCI Bus Interface: — PCI v2.1 compliant with wak eup cap ability — 32-Bit data path, up to 33 MHz — Glueless interface f or an external PCI device — Fixed priori ty — 3.
16 AMD Geode™ SC3200 Processor Data Book Overview 32581C.
AMD Geode™ SC3200 Processor Data Book 17 2 Architecture Overview 32581C 2.0 Architecture Ov er vie w As illustrated in Figure 1-1 on pa ge 13, the SC3200 pro- cessor contains the following modules i.
18 AMD Geode™ SC3200 Processor Data Book Architecture Overview 32581C T able 2-1. SC3200 Me mor y Contr oller Register Summary GX_B ASE+ Memory Offset Width (Bits) T ype Name/Function Reset V alue 8400h-8403h 32 R/W MC_MEM_CNTRL1. Memory Controller Control Register 1 248C004 0h 8404h-8407h 32 R/W MC_MEM_CNTRL2.
AMD Geode™ SC3200 Processor Data Book 19 Architecture Overview 32581C 4 RFSHTST (T est R efresh). This bit, when set high, generates a refresh r equest.
20 AMD Geode™ SC3200 Processor Data Book Architecture Overview 32581C GX_BASE+8408h-840Bh MC_BANK_CFG (R/W) Reset Value: 41104110h 31:16 RSVD (Reserved). Write as 0070h 15 RSVD (Reserved). Write as 0. 14 SODIMM_MOD_BNK (SODIMM Module Banks - Banks 0 and 1).
AMD Geode™ SC3200 Processor Data Book 21 Architecture Overview 32581C 11 RSVD (Reserved). Write as 0. 10:8 RRD (ACT(0) to A CT(1) Com mand Period, tRRD). Minimum n umber of SDRAM clocks between A CT and ACT command to two different component banks within the same module bank .
22 AMD Geode™ SC3200 Processor Data Book Architecture Overview 32581C 2.1.2 Fast-PCI Bus The GX1 module co mmunicates with the Core Logic mod- ule via a F ast-PCI bus that c an work at up to 66 MHz. The F ast-PCI bus is inter nal for the SC3200 and is connected to the General Configuration Bloc k (see Section 4.
AMD Geode™ SC3200 Processor Data Book 23 Architecture Overview 32581C • Sub-ISA: See Section 3.4.7 "Sub-ISA Interface Signals" on page 57, Section 6.2.5 "Sub-ISA Bus Interface" on page 145, an d Section 4.2 "Multiplexing, Interrupt Selec- tion, and Base Address Registers" on page 70 • GPIO: See Section 3.
24 AMD Geode™ SC3200 Processor Data Book Architecture Overview 32581C.
AMD Geode™ SC3200 Processor Data Book 25 3 Signal Definitions 32581C 3.0 Signal Definitions This section defines the signal s and describes th e external interf ace of the SC3200.
26 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C Figure 3-1. Signal Gr oups (Continued) The remaining subsectio ns of this chapter describe: • Section 3.1 "Ball Assignments": Provides a ball assign- ment diagram and tables listing the signals sor t ed according to ball number and alphabetica lly by signal name.
AMD Geode™ SC3200 Processor Data Book 27 Signal Definitions 32581C 3.1 Ball Assignments The SC3200 is high ly configurable as illustrated in Figure 3-1 on page 25. Strap optio ns and register programming are used to set v a rious modes of operation and specific signals on specific balls.
28 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C Figure 3-2. BGU481 Ball Assignment Di agram S S S S S S S S S 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4.
AMD Geode™ SC3200 Processor Data Book 29 Signal Definitions 32581C T able 3-2. BGU481 Ball Assignme nt - Sort ed by Ball Number Ball No. Signal Name I/O (PU/PD) Buffer 1 Ty p e Pow e r Rail Configur.
30 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C B6 AD23 I/O IN PCI , O PCI V IO Cycle Multiplex ed A23 O O PCI B7 V SS GND --- --- --- B8 RD# O O 3/5 V IO --- CLKSEL0 I (PD 100 ) IN STRP Strap (See T able 3- 4 on page 44.
AMD Geode™ SC3200 Processor Data Book 31 Signal Definitions 32581C C15 V SS GND --- --- --- C16 A V SSPLL2 GND --- --- --- C17 5,2 SLCT I IN T V IO PMR[2 3] 3 = 0 and (PMR[27] = 0 and FPCI_MON = 0) .
32 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C D10 GPIO1 I/ O (PU 22.5 ) IN T , O 3/5 V IO PMR[23] 3 = 0 and PMR[13] = 0 IOCS1# O (PU 22.5 ) O 3/5 V IO PMR[23] 3 = 0 and PMR[13] = 1 TFTD12 O (PU 22.5 ) O 1/4 V IO PMR[23] 3 = 1 D11 TRDE# O O 3/5 V IO PMR[12] = 0 GPIO0 I/O (PU 22.
AMD Geode™ SC3200 Processor Data Book 33 Signal Definitions 32581C F29 TDI I (PU 22.5 ) IN PCI V IO --- F30 GTEST I (PD 22.5 ) IN T V IO --- F31 VPCKIN I IN T V IO --- G1 STOP# I/O (PU 22.
34 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C L29 GPIO35 I/O (PU 22.5 ) IN PCI , O PCI V IO PMR[14] 4 = 0 and PMR[22] 4 = 0 LAD3 I/O (PU 22.5 ) IN PCI , O PCI PMR[14] 4 = 1 and PMR[22] 4 = 1 L30 GPIO34 I/O (PU 22.5 ) IN PCI , O PCI V IO PMR[14] 4 = 0 and PMR[22] 4 = 0 LAD2 I/O (PU 22.
AMD Geode™ SC3200 Processor Data Book 35 Signal Definitions 32581C R17 V SS GND --- --- --- R18 V SS GND --- --- --- R19 V SS GND --- --- --- R28 V SS GND --- --- --- R29 V SS GND --- --- --- R30 V .
36 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C W28 5 MD57 I/O IN T , TS 2/5 V IO --- W29 SDCLK1 O O 2/5 V IO --- W30 V SS GND --- --- --- W31 V IO PWR --- --- --- Y1 IDE_DA T A10.
AMD Geode™ SC3200 Processor Data Book 37 Signal Definitions 32581C AE31 5 MD28 I/O IN T , TS 2/5 V IO --- AF1 IRQ14 I IN TS1 V IO PMR [24] = 0 TFTD1 O O 1/4 PMR[24] = 1 AF2 IDE_CS0# O O 1/4 V IO PMR[24] = 0 TFTD5 O O 1/4 PMR[24] = 1 AF3 SOUT1 O O 8/8 V IO --- CLKSEL1 I (PD 100 ) IN STRP Strap (See T able 3- 4 on page 44.
38 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C AJ12 CASA# O O 2/5 V IO --- AJ13 BA0 O O 2/5 V IO --- AJ14 MA10 O O 2/5 V IO --- AJ15 5 MD32 I/O IN T , TS 2/5 V IO --- AJ16 5 MD33.
AMD Geode™ SC3200 Processor Data Book 39 Signal Definitions 32581C AL20 5 MD44 I/O IN T , TS 2/5 V IO --- AL21 5 MD40 I/O IN T , TS 2/5 V IO --- AL22 CKEA O O 2/5 V IO --- AL23 MA7 O O 2/5 V IO --- .
40 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C T able 3-3. BGU481 Ball Assignment - Sorted Alphabetical ly by Signal Name Signal Name Ball No.
AMD Geode™ SC3200 Processor Data Book 41 Signal Definitions 32581C F_ST OP# U29 F_TRD Y# U30 FP_VDD_ON V30, AB1 FPCI_MON A4 FPCICLK B18 FRAME# D8 GNT0# C5 GNT1# C6 GPIO0 D11 GPIO1 D10, N30 GPIO6 D28.
42 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C MD33 AJ16 MD34 AH16 MD35 AK17 MD36 AJ17 MD37 AH17 MD38 AL17 MD39 AL18 MD40 AL21 MD41 AH20 MD42 AJ20 MD43 AK20 MD44 AL20 MD45 AJ19 M.
AMD Geode™ SC3200 Processor Data Book 43 Signal Definitions 32581C V IO (T otal of 46) A2, A12, A30, B2, B13, B16, B19, B31, C3, C7, C10, C13, C22, C25, C29, D14, D15, D18, D23, G3, G29, K2, K29, M3.
44 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C 3.2 Strap Options Sev eral balls are read at powe r-up that set up the state of the SC3200. These balls are typical ly multiple xed with other functions that are outputs after the power-up sequence is complete.
AMD Geode™ SC3200 Processor Data Book 45 Signal Definitions 32581C 3.3 Multiplexing Configuration The tables that follo w l ist multiplexing options and their configurations. Cer tain multiplexing options ma y be chosen per signal; others are av ailable only for a g roup of signa ls.
46 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C GPIO A CCESS.bus N29 GPIO12 PMR[19] = 0 AB2C PMR[19] = 1 M29 GPIO13 AB2D GPIO U AR T A G 1 GPIO18 PMR[16] = 0 DTR1#/BOUT1 PMR[16 ] .
AMD Geode™ SC3200 Processor Data Book 47 Signal Definitions 32581C V31 GPIO16 PMR[0] = 0 and FPCI_MO N = 0 PC_BEEP PMR[0] = 1 = 0 and FPCI_MON = 0 F_DEVSEL FPCI_MON = 1 GPIO PCI 2 Sub-ISA C9 GPIO19 .
48 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C T able 3-7. Four-Signal/Gr oup Multiplexing Ball No. Default Alternate1 Alternate2 Alternate3 Signal Confi guration Signal Configur.
AMD Geode™ SC3200 Processor Data Book 49 Signal Definitions 32581C 3.4 Signal Descriptions Information in the tables that f ollow may hav e duplica te inf or m ati on in multiple tables . Multipl e references all contain identi - cal information. 3.
50 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C X32I AJ2 I/O Crystal Connections. Connected directly to a 32.768 KHz cr ystal. This clock input is required e ven if the inter- nal RT C is not being used. Some of the inter nal clocks are derived from this clock.
AMD Geode™ SC3200 Processor Data Book 51 Signal Definitions 32581C DQM7 AB31 O Data Mask Control Bits. During memor y read cycles, these outputs control whether SDRAM output buff ers are driven on the MD bus or not. All DQM signals are asser ted during read cycles.
52 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C 3.4.4 TFT Interface Signal s Signal Name Ball No. T ype Description Mux HSYNC A11 O Horizontal Sy nc --- VSYNC B11 O V er tical Sync --- TFTDCK AA1 O TFT Clock. IDE_RST# A10 GPIO17+ IOCS0# TFTDE P2 O TFT Data Enable .
AMD Geode™ SC3200 Processor Data Book 53 Signal Definitions 32581C 3.4.6 PCI Bus Interface Sign als Signal Name BalL No. T ype Description Mux PCICLK A7 I PCI Clock.
54 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C FRAME# D8 I/O Frame Cycle. F rame is dr iven b y the curre nt master to indicate the begin ning and duration of an access. FRAME# is asser ted to indicate the beginn ing of a bus transaction.
AMD Geode™ SC3200 Processor Data Book 55 Signal Definitions 32581C LOCK# H3 I/O Lock Operation. LOCK# i ndicates an atomic operati on that may require multiple transactions to complete. When LOCK# is asser ted, non-exclusiv e transactions ma y pro- ceed to an address that is not currently lock ed (at least 16 bytes must be lock ed).
56 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C REQ1# A5 I Request Li nes. REQ[1:0]# indicate to the arbiter that an agent requires the bus. Each master has its o wn REQ# line . REQ# priorities (in order) are: 1) VIP 2) IDE Channel 0 3) IDE Channel 1 4) A udio 5) USB 6) External REQ0# 7) External REQ1#.
AMD Geode™ SC3200 Processor Data Book 57 Signal Definitions 32581C 3.4.7 Sub-ISA Interface Signals Signal Name Ball No. T ype Descr iption Mux A[23:0] See T able 3-3 on page 40.
58 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C 3.4.8 Low Pin Count (LPC) Bus Interface Signals Signal Name Ball No. T ype Descr iption Mux LAD3 L29 I/O LPC Address-Data. Multiplex ed co mmand, address, bidirectional data, and cycle status.
AMD Geode™ SC3200 Processor Data Book 59 Signal Definitions 32581C IDE_IORD Y0 AD1 I I/O Ready Channels 0 and 1. When de-asser ted, the se signals extend the tr an sf er cycle of any host register access if the required device is not ready to respond to the data transfer request.
60 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C 3.4.11 Seri al P o rts (U ARTs) Interfa ce Signals Signal Name Ball No. T ype Description Mux SIN1 A G2 I Serial I nputs. Receive composite serial data from the communications link (peripheral device, modem or other data transf er device).
AMD Geode™ SC3200 Processor Data Book 61 Signal Definitions 32581C 3.4.12 Parallel Port Interfac e Signals Signal Name Ball No. T ype Description Mux ACK# B18 I Acknowledge. Pulsed low by the printer to in dicate that it has received data from the P arallel P or t.
62 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C STB#/WRITE# A22 O Data Strobe. Whe n low, indicates to the printer that valid data is available at the printer por t. This signal is in TRI- ST A T E after a 0 is lo aded into the co rresponding control register bit.
AMD Geode™ SC3200 Processor Data Book 63 Signal Definitions 32581C 3.4.14 AC97 A udio Inte rface Sign als Signal Name Ball No. T ype Description Mux BIT_CLK U30 I A u dio Bit Clock. The serial bit clock from the codec. Note: If selected as BIT_CLK function but not used, tie BIT_CLK low.
64 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C 3.4.15 Po we r Management I nterface Sign als Signal Name Ball No. T ype Description Mux CLK32 AH8 O 32.768 KHz Output Clock --- GPWIO0 AH6 I /O General Purpose W akeup I/Os. These signals each hav e an i nternal pull-up of 100 K Ω .
AMD Geode™ SC3200 Processor Data Book 65 Signal Definitions 32581C 3.4.16 GPIO Inte rface Signals Signal Name Ball No. T ype Description Mux GPIO0 D11 I/O GPIO P or t 0. Each signal is configured independently as an input or I/O , with or without static pull-u p , and with either open-drain or to tem-pole ou tput type.
66 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C 3.4.17 Deb ug Monitoring Interface Signals Signal Name Ball No. T ype Description Mux FPCICLK B18 O Fast-PCI Bus Monitori ng Signals. When enabled, this group of signals provides f or mo nitoring of the inter nal F ast-PCI bus f or debug pur poses.
AMD Geode™ SC3200 Processor Data Book 67 Signal Definitions 32581C TRST# E29 I JT A G T est Reset. This signal has an inter nal weak pul l- up resistor . F or norma l JT AG operation, this signal should be active at power-up . If the JT AG interf ace is not being used, this signal can be tied low .
68 AMD Geode™ SC3200 Processor Data Book Signal Definitions 32581C 3.4.20 P ower , Ground and No Connections 1 Signal Name Ball No. T ype Description AV SSPLL2 C16 GND Analog PLL2 Gr ound Connection. AV SSPLL3 AK3 GND Analog PLL3 Gr ound Connection.
AMD Geode™ SC3200 Processor Data Book 69 4 General Configuration Block 32581C 4.0 General Configur ation Bloc k The General Configuration bloc k inclu des registers for: • Pin Multiplexing and Mis.
70 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C 4.2 Multiplexing, Inte rrupt Selection, and Base Ad dress Registers The registers described inT able 4-2 are used to deter mine general configuration for the SC3200.
AMD Geode™ SC3200 Processor Data Book 71 General Configuration Block 32581C 25 A C 97CKEN (Enable A C97_CLK Output). This bit enables the output drive of A C97_C LK (ball P31). 0: AC97_CLK output is HiZ. 1: AC97_CLK output is enabled. 24 TFTIDE (TFT/IDE).
72 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C 23 TFTPP (TFT/Parallel P or t). Determines whether cer tain balls are used for TFT or PP/AC B1/FPCI. This bit is set to 1 at power-on if the TFT_PRSNT strap (ball P29) is pulled high.
AMD Geode™ SC3200 Processor Data Book 73 General Configuration Block 32581C 21 IOCSEL (Select I/O Commands ) . Selects ball functions. Ball # 0: I/O Comma nd Signals 1: GPIO Signals Name Add’l Dep.
74 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C 12 TRDESEL (Select TRDE#). Selects ball function. Ball # 0: Sub-ISA Signal 1: GPIO Signal Name Add’l Dependencies Name Add’l Dependencies H1 / D11 TRDE# None GPIO0 None 11 EIDE (Enable IDE Outputs).
AMD Geode™ SC3200 Processor Data Book 75 General Configuration Block 32581C 16 Dela y HSYNC. HSYNC dela y by two TFT clock cycles. 0: There is no delay on HSYNC. 1: HYSNC is delay ed twice by rising edge of TFT clock. Enab les delay between VSYNC and HSYNC suited f or TFT dis- pla y .
76 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C 0 SDBE0 (Slave Disconnect Boundar y Enable). W or ks in conjunction with the GX1 module’s PCI Control Function 2 Regis- ter (Index 41h), bit 1 (SDBE1). Sets boundaries for when the GX1 module is a PCI sla ve.
AMD Geode™ SC3200 Processor Data Book 77 General Configuration Block 32581C 4.3 W A TCHDOG The SC3200 includes a W A TCHDOG function to ser ve as a f ail-safe mechanism in case the system becomes hung.
78 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C W A TCHDOG Interrupt The W A TCHDOG interrupt (if con figured and enabled) is routed to an IRQ signal.
AMD Geode™ SC3200 Processor Data Book 79 General Configuration Block 32581C 4.4 High-Resolution Timer The SC3200 p rovides an accur ate time v a lue that can be used as a time stamp b y system software . This time is called the High-Resoluti on Timer .
80 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C T able 4-4. High-Resolutio n Timer Register s Bit Description Offset 08h-0Bh TIMER Value Register - TMV ALUE (RO) Reset V alue: xxxxxxxxh This register contains the current value of the High-Resolution Timer .
AMD Geode™ SC3200 Processor Data Book 81 General Configuration Block 32581C 4.5 Cloc k Generators and PLLs This section describes the r egisters f or the clocks required by the GX1 module, Core Logic module, and the Video Processor , and how these clocks are generated.
82 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C 4.5.1 27 MHz Cr ystal Os cillator The inter nal oscillator employs an ex ter nal cr ystal con- nected to the on-chip amplifie r . The on-chip amplifier is accessible on the X27I input and X27O output signals.
AMD Geode™ SC3200 Processor Data Book 83 General Configuration Block 32581C 4.5.2 GX1 Module Core Cloc k The core clock is generated by an Analog Delay Loop (ADL) clock generator from the inter nal F ast-PCI clock. The clock can be any whole-n umber multiple of the input clock between 4 and 10.
84 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C 4.5.4 SuperI/ O Clocks The SuperI/O module requires a 48 MHz input for F ast infrared (FIR), U ART , and other functions. This clock is sup- plied by PLL4 using a multiplier value of 576/(108x3) to generate 48 MHz.
AMD Geode™ SC3200 Processor Data Book 85 General Configuration Block 32581C 4.5.7 Clock Registe rs T able 4-8 describes the registers of the clock generator and PLL.
86 AMD Geode™ SC3200 Processor Data Book General Configuration Block 32581C Offset 1Eh-1Fh Core Clock Frequency Control Regi ster - CCFC (R/W) Reset Value: S t rapped V alue This register controls the configuration of the core clock multiplier and the ref erence clocks.
AMD Geode™ SC3200 Processor Data Book 87 5 SuperI/O Module 32581C 5.0 SuperI/O Module The SuperI/O (SIO) module i s a PC98 and ACPI compliant SIO that offers a single-cell solution to the most co mmonly used ISA perip herals.
88 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.1 Features PC98 and A CPI Compliant • PnP Configuration Register str ucture • Flexib le resour ce allocation for all logical de .
AMD Geode™ SC3200 Processor Data Book 89 SuperI/O Module 32581C 5.2 Module Ar chitecture The SIO module comprises a collection of generic func- tional blocks .
90 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.3 Configuration St ructure / Access This section descr ibes the st r ucture of the configuration register file, and the method of ac cessing the configuration registers.
AMD Geode™ SC3200 Processor Data Book 91 SuperI/O Module 32581C Write accesses to unimplemented registers (i.e., accessing the Data register while the I ndex register points to a non- ex i sting reg.
92 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.4 Standard Configur ation Register s As illustrated in Figure 5-4, the Standard Configuration reg- isters are broadly divided i nto .
AMD Geode™ SC3200 Processor Data Book 93 SuperI/O Module 32581C T able 5-3 provides the bit definitions for the Standard Con- figuration registers. • All reser ved bits return 0 on reads, except where noted otherwise. They must not be m odified as such modifica- tion may cause unpredictable results.
94 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C Index 75h DMA Channel Select 1 (R/W) Indicates selected DMA channel for DMA 1 of the logical de vice (1 - the second DMA channel in case of using more than one DMA channel). 7:3 Reserved.
AMD Geode™ SC3200 Processor Data Book 95 SuperI/O Module 32581C 5.4.1 SIO Control and Configuration Register s T able 5-4 lists the SIO Control and Configuration regi sters and T able 5-5 provides their bit f or mats. T able 5-4. SIO Control and C onfiguration Register Map Index T ype Name P ower Rail Reset V a lue 20h RO SID.
96 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.4.2 Logica l Device Control and Configuration As described in Section 5.3.2 "Banked Logical Device Reg- isters" on page 90, each functio nal bloc k is a ssociated with a Logical Device Number (LDN).
AMD Geode™ SC3200 Processor Data Book 97 SuperI/O Module 32581C T able 5-7. RTC Confi guration Register s Bit Description Index F0h RAM Lock Register - RLR (R/W) When any non-reser ved bit in this register is set to 1, it c an be cleared only by hardware reset.
98 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.4.2.2 LDN 01h - Sy stem Wakeup Contr ol T able 5-8 lists registers that are relev ant to the configura- tion of System W a keup Control (SWC). These registers ar e descri bed earlier in T able 5-3 "Standard Configuration Reg- isters" on page 93.
AMD Geode™ SC3200 Processor Data Book 99 SuperI/O Module 32581C 5.4.2.3 LDN 02h - Infrared Communication P or t or Serial P or t 3 T able 5-9 lists the configurati on registers whi ch aff ect the Infrared Communication P or t or Serial Port 3 (IRCP/SP3).
100 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.4.2.4 LDN 03h and 08h - Serial P or ts 1 and 2 Serial P o r ts 1 and 2 are iden tical, e xcep t fo r their reset val- ues. Serial Port 1 is designate d as LDN 03h and Ser ial P or t 2 as LDN 08h.
AMD Geode™ SC3200 Processor Data Book 101 SuperI/O Module 32581C 5.4.2.5 LDN 05h and 06h - A CCESS.bus P or ts 1 and 2 A CC ESS.b us por ts 1 and 2 (ACB1 and A CB2 ) are identi- cal. Each ACB is a tw o-wi re synchronous serial interface compatible with the A CCESS.
102 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.4.2.6 LDN 07h - P ar allel P or t The P arallel P or t suppor ts all IEEE 1284 standard commu- nication modes: Compatibility (known also as Standard or SPP), Bidirectional (known also as PS/2), FIFO , EPP (known also as Mode 4) and ECP (with an optional Extended ECP mode).
AMD Geode™ SC3200 Processor Data Book 103 SuperI/O Module 32581C 5.5 Real-Time Cloc k (R TC) The RTC pro vides timekeeping and calendar management capabilities. The RTC uses a 32.768 KHz signal as the basic clock f or timekeeping. It also includes 242 bytes of batter y-back ed RAM f o r general-pur pose use.
104 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C External Elements Choose C 1 and C 2 capacitors (see Figure 5-5 on page 103) to match the cr ystal’ s load capacitance. The load capacitance C L “seen” by crystal Y is compr ised of C 1 in series with C 2 and in parallel with the parasi tic capacitance of the circuit.
AMD Geode™ SC3200 Processor Data Book 105 SuperI/O Module 32581C 5.5.2.4 Timekeeping Data Format Time is kept in BCD or binar y format, as determined by bit 2 (DM) of Control Register B (CRB), and in either 12 or 24- hour f o rmat, as deter mined by bit 1 of this register .
106 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.5.2.6 P ower Supply The device is supplied from two supply voltages, as shown in Figure 5-8: • System standby pow er supply volta.
AMD Geode™ SC3200 Processor Data Book 107 SuperI/O Module 32581C 5.5.2.7 System P ower States The system power state ma y be No P ow er , P ower On, P ower Off or P ower F ailure. T able 5-18 indicates the power- source combinations for each state .
108 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.5.2.9 Interrupt Handling The RTC has a single Interr upt Request line whi ch handles the following three interrupt condi tions: • P er iodic interrupt. • Alar m interrupt. • Update end interrupt.
AMD Geode™ SC3200 Processor Data Book 109 SuperI/O Module 32581C 5.5.3 RTC Registers The RTC registers can be acce sse d (see Section 5.4.2.1 "LDN 00h - Real-Time Clock" on page 96) at any time dur- ing nor mal operation mode (i.e.,when V SB is within the rec- ommended operation range).
110 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C Index 03h Minutes Alarm Register - MINA (R/W) Reset T ype: V PP PU R 7:0 Minutes Alarm Data. V alues can be 00 to 59 in BCD format, or 00 to 3B in binar y format. When bits 7 and 6 are both set to 1, unconditional match is selected.
AMD Geode™ SC3200 Processor Data Book 111 SuperI/O Module 32581C 3 Reserved. This bit is defined as “Square Wa ve Enable” b y the MC146 818 and is not suppor ted by the R TC. This bit is alwa ys read as 0. 2 Data Mod e . This bit is reset at V PP power-up reset only .
112 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C T able 5-21 . Divider Chain Contr ol / T est Selection DV 2 DV 1 DV 0 Configuration CRA6 CRA5 CRA4 0 0 X Oscillator Disabled 0 1 0 Nor mal Operation 01 1 T e s t 10 X 1 1 X Di vider Chain Reset T able 5-22.
AMD Geode™ SC3200 Processor Data Book 113 SuperI/O Module 32581C 5.5.3.1 Usage Hints 1) Read bit 7 of CRD at each system pow er-up to v ali- date the contents of the RTC registers and the CMOS RAM. When this bit is 0, the contents of these re gis- ters and the CMOS RAM are questionable.
114 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.6 System W akeup Control (SWC) The SWC wak es up the system by sending a pow er-up request to the ACPI controller in response to th.
AMD Geode™ SC3200 Processor Data Book 115 SuperI/O Module 32581C 5.6.2 SWC Regist ers The SWC registers are organized in two banks. The offsets are related to a base address that is deter mined by the SWC Base Address Register in the logical device configu- ration.
116 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C T able 5-29. Banks 0 and 1 - Common Control and Status Register s Bit Description Offset 00h W akeup Events Status Regist er - WKSR (R/W1C) Reset V alu e: 00h This register is set to 00h on power-up of V PP or software reset.
AMD Geode™ SC3200 Processor Data Book 117 SuperI/O Module 32581C T able 5-30. Bank 1 - CEIR W akeup Configuration and Control Register s Bit Description Bank 1, Offset 03h CEIR Wakeup Control Register - IR WCR (R/W) Reset V alue: 00h This register is set to 00h on power-up of V PP or software reset.
118 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C CEIR Wakeup Range 1 Registers These two registers (IR WTR1L and IRWTR1H) define the low and high limits of time range 1 (see T able 5-26 on page 114). The valu es are represented in units of 0.
AMD Geode™ SC3200 Processor Data Book 119 SuperI/O Module 32581C 5.7 A CCESS.bus Interface The SC3200 has two ACCESS .bus (ACB) controllers . A CB is a two-wire synchronous ser ial interface compatible with the ACCESS .bus physical la yer , In tel's SMBus, and Phili ps’ I 2 C™.
120 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.7.3 Acknowledge (A CK) Cycle The ACK cycle consists of two signals: the A CK clock pulse sent by the master with each byte transf erred, and the ACK signal sent by the receiving device (see Figure 5-15).
AMD Geode™ SC3200 Processor Data Book 121 SuperI/O Module 32581C 5.7.4 Acknowledge After Eve ry Byte Ru le According to this rule, the master generates an acknowl- edge clock pulse after each byte transf er, and the receiver sends an acknowledge signal after e very byte received.
122 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C Sending the Address Byte When the device is the active master of the A CCESS.b us (A CBST[1 ] is set), it can send the address on the bus .
AMD Geode™ SC3200 Processor Data Book 123 SuperI/O Module 32581C Master Error Detection The ACB detects illegal Star t or Stop Conditions (i.e., a Star t or Stop Condi tion within the data transfer , or the ackno wl edge cycle) and a confl ict on the data lines o f the A CC ESS.
124 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 5.7.10 ACB Registers Each functional block is associated with a Logical Device Number (LDN) (see Section 5.3 .2 "Banked Logical De vice Registers" on page 90). A CCESS.Bus P or t 1 is assigned as LDN 05h and ACCESS .
AMD Geode™ SC3200 Processor Data Book 125 SuperI/O Module 32581C 2 NMA TCH (Ne w Match). (R/W1C) Wr iting 0 to this bit is ignored. If ACBCTL1[2] is set, an interrupt is sent when this bit is set. 0: Software writes 1 to this bit. 1: Address byte follo ws a Star t Condition or a repeated star t, causing a match or a global-call match.
126 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 4 A C K (Acknowledge). This bit is ignored in transmit mode . When the de vice acts as a receiv er (slav e or master), this bit holds the stop transmitting instruction that is transmitted dur ing the next ac knowledge cycle.
AMD Geode™ SC3200 Processor Data Book 127 SuperI/O Module 32581C 5.8 Legacy Functional Blocks This section bri efly descr ibes the follo wing blocks that pro- vide legacy device functions: • P arallel P or t. (Similar to Par allel P or t in the National Semiconductor PC87338.
128 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C T able 5-35. P arallel P or t Bit Map f or First Leve l Offset Offset Name Bits 76543210 000h DA T AR Data Bits AFIFO Address Bits 00.
AMD Geode™ SC3200 Processor Data Book 129 SuperI/O Module 32581C 5.8.2 U ART Functionality (SP1 and SP2) Both SP1 and SP2 provide U ART functionality . The gene ric SP1 and SP2 suppor t ser ial data communicatio n with remote periphe ral de vice or modem using a wire d inter- f ace.
130 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C T able 5-38 . Bank Selection Encoding BSR Bits Bank Selected 76543210 0xxxxxxx 0 1 0xxxxxx 1 1 1xxxx 1x 1 1 1xxxxx 1 1 11100000 2 11100100 3 T able 5-39. Bank 1 Register Map Offset T ype Name 00h R/W LBGD(L).
AMD Geode™ SC3200 Processor Data Book 131 SuperI/O Module 32581C T able 5-42 . Bank 0 Bit Map Register Bits O f f s e t N a m e 76543210 00h RXD RXD[7:0] (Receiv er Da ta Bits) TXD TXD[7:0] (T ransm.
132 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C T able 5-44 . Bank 2 Bit Map Register Bits O f f s e t N a m e 7 654321 0 00h BGD(L) BGD[7:0] (Lo w Byt e) 01h BGD(H) BGD [15:8] (Hig.
AMD Geode™ SC3200 Processor Data Book 133 SuperI/O Module 32581C 5.8.3 IR Communications P or t (IRCP) / Serial P ort 3 (SP3) Functionalit y This section describes the IRCP/SP3 suppor t registers . The IRCP/SP3 functional block pro vides advanced, v ersa- tile serial communications features with IR capabilities.
134 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C T able 5-47 . Bank Selection Encoding BSR Bits Bank Selected Functionality 76543210 0 xxxxxxx 0 U A R T + I R 1 0 xxxxxx 1 1 1 xxxx1 x 1 1 1 xxxxx1 1 11100000 2 11100100 3 11101000 4 I R O n l y 11101100 5 11110000 6 11110100 7 T able 5-48.
AMD Geode™ SC3200 Processor Data Book 135 SuperI/O Module 32581C T able 5-50. Bank 3 Register Map Offset T ype Name 00h RO MID. Module and Re vi sion Identification 01h RO SH_LCR. Link Control Shadow 02h RO SH_FCR. FIFO Control Shadow 03h R/W BSR. Bank Select 04h-07h --- RSVD .
136 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C T able 5-53. Bank 6 Register Map Offset T ype Name 00h R/W IRCR3. IR Contro l 3 01h R/W MIR_PW . MIR Pulse Width 02h R/W SIR_PW . SIR Pulse Width 03h R/W BSR. Bank Select 04h R/W BFPL.
AMD Geode™ SC3200 Processor Data Book 137 SuperI/O Module 32581C T able 5-56 . Bank 1 Bi t Map Register Bits O f f s e t N a m e 76543210 00h LBGD(L) LBGD[7:0] (Low Byte Data) 01h LBGD(H) LBGD[15:8] (High Byte Data) 02h RSVD RSVD 03h LCR BKSE SBRK STKP EPS PEN STB WLS[1:0] BSR BKSE BSR[6:0] (Bank Select) 04h-07h RSVD RSVD T able 5-57 .
138 AMD Geode™ SC3200 Processor Data Book SuperI/O Module 32581C 06h RFRML(L)/ RFRCC(L) RFRML[7:0] / RFRCC[7:0] (Low Byte Data) 07h RFRML(H)/ RFRCC(H) RSVD RFRML[12:8] / RFRCC[12:8] (High Byte Data) T able 5-59. Bank 4 Bit Map (Continued) Register Bits O f f s e t N a m e 76543210 T able 5-60 .
AMD Geode™ SC3200 Processor Data Book 139 6 Core Logic Mo dule 32581C 6.0 Core Logic Module The Core Logic module is an enh anced PCI-to-Sub-ISA bridge (South Br idge), this module is ACPI-compliant, and provides A T/Sub-ISA functionality . The Core Logic module also contains state-of-the-a r t p ower management.
140 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C Integrated A u dio • A C9 7 V ersion 2.0 compliant interface to audio codecs • Secondar y codec suppor t • AMC97 codec suppo.
AMD Geode™ SC3200 Processor Data Book 141 Core Logic Mo dule 32581C 6.2.1 Fast- PCI Interface to Exte rnal PCI Bus The Core Logic modu le provides a PCI bus interface that is both a slav e for PCI cycles init iated by the GX1 module or other PCI master de vices, and a non-preemptive master f or DMA transf er cycles.
142 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.2.1 Video Re trace Interrupt Bit 7 of the “Serial P acket” can be used to generate an SMI whenev er a video retrace occurs within the GX1 module. This function is nor mally not used for pow e r management but f or SoftV GA routines.
AMD Geode™ SC3200 Processor Data Book 143 Core Logic Mo dule 32581C F or example , if a channel had on e Mode 4 device and one Mode 0 de vice, then the Mode 4 de vice would hav e com- mand timings f or Mod e 0 and data timing f or Mode 4. Th e Mode 0 device would ha ve both command and data timings f or Mode 0.
144 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.3.4 UltraDMA/33 Mode The IDE controller of the Core Logic mod ule suppor ts UltraDMA/33. It utilizes the standard IDE Bus Master func- tionality to interface , initiate and control the transfer .
AMD Geode™ SC3200 Processor Data Book 145 Core Logic Mo dule 32581C 6.2.4 Universal Se rial Bus The Core Logic module provides three complete, indepen- dent USB por ts. Each por t has a Data "Negative" and a Data "P ositive" signal.
146 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.5.1 Sub-ISA Bus Cycles The ISA bus controller issues multiple ISA cycles to satisfy PCI transactions that are larger than 16 bits. A full 32-bit read or write resul ts in two 16-bit ISA transactions or f o ur 8- bit ISA transactions.
AMD Geode™ SC3200 Processor Data Book 147 Core Logic Mo dule 32581C Figure 6-3. PCI to ISA Cyc les with Delay ed T ransaction Enab led 6.2.5.3 Sub-ISA Bu s Data Steering The Core Logic mod ule performs all of the required d ata steerin g from SD[7:0] to SD[15:0] du ring nor mal 8-bit ISA cycles, as well as during DMA and ISA master cycles.
148 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.5.5 ISA DMA DMA transf ers occur between ISA I/O periphe rals and sys- tem memory (i.
AMD Geode™ SC3200 Processor Data Book 149 Core Logic Mo dule 32581C 6.2.5.6 ROM Interface The Core Logic mo dule positi vely decodes memor y addresses 000F0000h-000FFFFFh (64 KB) an d FFFC0000h-FFFFFFFFh (256 KB) at reset.
150 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C Figure 6-6. PCI Change to Sub-ISA and Back 6.2.6 A T Compati bility Logic The Core Logic module integrates: • T wo 8237-equivale.
AMD Geode™ SC3200 Processor Data Book 151 Core Logic Mo dule 32581C DMA T ransfer Modes Each DMA channel can be programmed for single , blo ck , demand or cascade transf er modes. In the most commonly used mode, single transfer mode, one DMA cycle occurs per DRQ and the PCI bus is released after e very cycle.
152 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C DMA Addressing Capability DMA transf ers occur over the entire 32-bit address range of the PCI bus. This is accomplished by using the DMA con- troller’ s 16-bit memor y add ress registers in conjunction with an 8-bit DMA Low P age register and an 8-bit DMA High P age register .
AMD Geode™ SC3200 Processor Data Book 153 Core Logic Mo dule 32581C 6.2.6.3 Programmable Interrupt Contr olle r The Core Logic module con tains two 8259A-equivalent programmab le interrup t controllers, with eight interr upt request lines each, for a total of 16 interr upts.
154 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C PIC Interrupt Sequence A typical A T -compatible interrup t sequence is as follo ws. Any unmasked interrupt generates the inter nal INTR signal to the CPU. The interrupt contro ller then responds to the interrupt acknowledge (INT A) cycles from the CPU .
AMD Geode™ SC3200 Processor Data Book 155 Core Logic Mo dule 32581C 6.2.7.1 I/O P or t 092h System Control I/O P or t 092 h allows f or a f ast keyboard asser tion of an A20# SMI and a fast ke yboard CPU reset. Decoding for this register may be disab led via F0 Index 52h[3].
156 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.9 P ower Mana g ement Logic The Core Logic mo dule integrates advanced pow er man- agement features including idle timers for .
AMD Geode™ SC3200 Processor Data Book 157 Core Logic Mo dule 32581C 6.2.9.2 Sleep States The SC3200 suppor ts f our Slee p states (SL1-SL3) and the Soft Off state (G2 /S5). Thes e states are fully compliant with the ACPI sp ecific ation, revision 1.
158 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.9.3 P ower Planes Control The SC3200 suppor ts up to three power planes. Three sig- nals are used to control these power planes. T able 6-6 describes th e signals and when each is asser ted.
AMD Geode™ SC3200 Processor Data Book 159 Core Logic Mo dule 32581C P ower Button The power b utton (PWRBTN# ) input provides two e vents: a wak e request, a nd a sleep request.
160 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.10 P ower Management Programming The power management resources provided by a com- bined GX1 module and Core Logic module base d system suppor ts a high efficiency power management implementa- tion.
AMD Geode™ SC3200 Processor Data Book 161 Core Logic Mo dule 32581C The automatic speedup events (video and IRQ) f or Sus- pend Modulation should be used together with software- controlled speedup r.
162 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.10.3 Peripheral P ower Manag ement The Core Logic module provides peripheral power man- agement using a combination of device idle timers, address traps, and general pur pose I/O pins.
AMD Geode™ SC3200 Processor Data Book 163 Core Logic Mo dule 32581C P ower Managem ent SMI Status Repor ting Registers The Core Logic mod ule updates status registers to reflect the SMI sources. P ower management SMI sources are the de vice idle timers, address traps, and general purpos e I/O pins.
164 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.10.4 Po w er Manageme nt Programming Summary T able 6-9 provides a programming register summar y for the power management timers, tr aps, and functions. For com- plete bit inform ation regarding th e registers listed in T able 6-9, ref er to Section 6.
AMD Geode™ SC3200 Processor Data Book 165 Core Logic Mo dule 32581C 6.2.11 GP IO Interface Up to 64 GPIOs in the in the Core Logi c module are pro- vided f or system control.
166 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C Physical Region Descriptor T able Address Bef ore the bus master starts a master transfer it must be pro- grammed with a pointer (PRD T able Address register ) to a Ph ysical Region Descr iptor T able.
AMD Geode™ SC3200 Processor Data Book 167 Core Logic Mo dule 32581C 4) Read the SMI Status register to clear the Bus Master Error and End of P age bits (bits 1 and 0). Set the correct directi on to the Read or Write Co ntrol bit (Command register bit 3).
168 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.12.2 AC97 Codec Interface The AC97 codec (e.g., LM4548) is the master of the serial interf ace and generates the clocks to Core Logic module. Figure 6-13 shows the signal connections between two codecs and the SC3 200: • Codec1 can be AC97 Re v .
AMD Geode™ SC3200 Processor Data Book 169 Core Logic Mo dule 32581C 6.2.12.3 VSA T echnolo gy Support Hard ware The Core Logic mod ule incor porates the requi red hard- ware in order to suppor t the Vir tual System Arch itecture (VSA) technology f or cap ture and playbac k of audio using an external codec.
170 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C In F ast Path Write, the Core Logic modul e responds to writes to the following addresses: 388h, 38Ah, 38Bh, 2x0h, 2x2h, and 2x8h. T able 6-38 on page 262 shows the bit formats of the sec- ond lev el SMI status repor ting registers and the F ast Path Read/Write programming bits.
AMD Geode™ SC3200 Processor Data Book 171 Core Logic Mo dule 32581C 6.2.12.4 IRQ Configuration Registers The Core Logic modul e provides the ability to set an d clear IRQs inter nally through software control. If the IRQs are configured for softw are control, they do not respond to ex ter nal hardware.
172 AMD Geode™ SC3200 Processor Data Book Core Logic Mo dule 32581C 6.2.12.6 LPC Interface Signal De finitions The LPC specification lists seven required and six optional signals for supporti ng the LPC interface. Man y of the sig- nals are the same sign als found on the PCI interf ace and do not require any new pins on the host.
AMD Geode™ SC3200 Processor Data Book 173 Core Logic Module - PCI Configuration Space an d Access Methods 32581C 6.3 Register Descriptions The Core Logic modul e is a multi-function module.
174 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Re gister Summary 32581C 6.3.2 Register Su mmary The tables in this subsection summarize the registe rs of the Core Logic module. Included in the tables are the regis- ter’ s reset values and page ref erenc es where the bit f or- mats are f ound.
AMD Geode™ SC3200 Processor Data Book 175 Core Logic Module - Register Summar y 32581C 6Ch-6Fh 32 R/W ROM Mask Register 0000FFF0h P age 198 70h-71h 16 R/W IOCS1# Base Address Register 0000h Page 199.
176 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Re gister Summary 32581C B8h 8 RO DMA Shadow Register xxh P age 215 B9h 8 RO PIC Shadow Register xxh P age 215 BAh 8 RO PIT Shado w R eg.
AMD Geode™ SC3200 Processor Data Book 177 Core Logic Module - Register Summar y 32581C T able 6-15 . F0B AR0: GPIO Support Register s Summar y F0BAR0+ I/O Offset Width (Bits) T ype Name Reset Va l u.
178 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Re gister Summary 32581C T able 6-17. F1: PCI Header Registe rs f or SM I Status and A CPI Su ppor t Summary F1 Index Width (Bits) T ype.
AMD Geode™ SC3200 Processor Data Book 179 Core Logic Module - Register Summar y 32581C T able 6-19. F1B AR1: ACPI Support Reg isters Summary F1BAR1+ I/O Offset Width (Bits) T ype Name Reset Va l u e.
180 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Re gister Summary 32581C T able 6-20. F2: PCI Header Register s for IDE Contr oller Suppor t Summary F2 Index Width (Bits) T ype Name Re.
AMD Geode™ SC3200 Processor Data Book 181 Core Logic Module - Register Summar y 32581C T able 6-21 . F2BAR4: IDE Controller Support Register s Summary F2BAR4+ I/O Offset Width (Bits) T ype Name Rese.
182 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Re gister Summary 32581C T able 6-23. F3BAR0: A udi o Suppor t Registers Summar y F3BAR0+ Memory Offset Width (Bits) T ype Name Reset Va.
AMD Geode™ SC3200 Processor Data Book 183 Core Logic Module - Register Summar y 32581C T able 6-24. F5 : PCI Header Registers for X-Bus Expansion Suppo rt Summar y F5 Index Width (Bits) T ype Name R.
184 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Re gister Summary 32581C T able 6-26. PCIUSB: USB PCI Confi guration Regis ter Summary PCIUSB Index Width (Bits) T ype Name Reset V alue.
AMD Geode™ SC3200 Processor Data Book 185 Core Logic Module - Register Summar y 32581C T able 6-27. USB_BAR: USB Controller Regist ers Summary USB_BAR0 +Memory Offset Width (Bits) T ype Name Reset V.
186 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Re gister Summary 32581C T able 6-28. ISA Legacy I/O Re gister Summary I/O P ort T ype Name Reference DMA Channel Control Registers (T a.
AMD Geode™ SC3200 Processor Data Book 187 Core Logic Module - Register Summar y 32581C 487h R/W DMA Channel 0 High P age Register P age 300 489h R/W DMA Channel 6 High P age Register P age 300 48Ah .
188 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 6.4 Chipset Register Space The Chipset Register Space of the Core Logic module is comprised of six separate functions (F0-F5), each with its own register space .
AMD Geode™ SC3200 Processor Data Book 189 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 4 Memory Write an d In validate. Allow the Core Logic module to do memory write and invalidate cycles , if the PCI C ache Line register (F0 Index 0Ch) is set to 32 bytes (08h).
190 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 08h Device Revision ID Register (RO) Reset V alue: 00h Index 09h-0Bh PCI Class Co de Register (RO) Reset V alue: 060100h Index 0Ch PCI Cache Line Siz e Register (R/W) Reset V alue: 00h 7:0 PCI Cache Line Size Register .
AMD Geode™ SC3200 Processor Data Book 191 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 40h PCI Function Control Register 1 (R/W) Reset V alue: 39h 7:6 Reserved. Must be set to 0. 5 Reserved. Must be set to 0. 4 PCI Subtractive Decode .
192 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 1 P ower Management Configuration T rap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI Function 1 (F1) register space, an SM I is generated.
AMD Geode™ SC3200 Processor Data Book 193 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 2 IDE Reset. Reset IDE bus . 0: Disab le. 1: Enab le (drive ID E_RST # low ). Write 0 to clear. This bit is lev el-sensitive and must be cleared after the reset is enab led.
194 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 4Ch-4Fh T op of System Memory (R/W ) Rese t V alue: FFFFFFFFh 31:0 T op of System Memory . Highest address in system used to deter mine acti ve decode for e xter nal PCI mastered memor y cycles.
AMD Geode™ SC3200 Processor Data Book 195 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 52h ROM/A T Logic Control Register (R/W) Re set V alue: 98h 7 Snoop Fast Keyboar d Gate A20 an d Fast Reset. Enab les the sno op logic associat ed with keyboard commands f or A20 Mask and Reset.
196 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 54h-59h Reser ved Reset V alue: 00h Index 5Ah Decod e Control Register 1 (R/W) Re set V alue: 01h Indicates PCI positive or negativ e decodi ng f or various I/O por ts on the ISA bus.
AMD Geode™ SC3200 Processor Data Book 197 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 4 Secondary IDE C ontroller P ositive Decode . Selects PCI positive or subtr active decoding f or accesses to I/O po rts 170h- 177h and 376h-377h (excluding writes to 377h).
198 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 60h-63h ACPI Contr ol Re gister (R/W) Reset V alue: 00000000h 31:8 Reserved. Must be set to 0. 7 SUSP_3 V Shut D own PLL5. Allow interna l SUSP_3V to shut down PLL5.
AMD Geode™ SC3200 Processor Data Book 199 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 70h-71h IOCS1# Base Address Re gister (R/W) Reset Value: 0000h 15:0 I/O Chip Select 1 Base Address.
200 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 78h-7Bh DOCCS# Base Address Register (R/W) Reset V alue: 00000000h 31:0 DiskOnChip Chip Select Base Address.
AMD Geode™ SC3200 Processor Data Book 201 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 1 Idle Timers. Device idle timers. 0: Disab le. 1: Enab le. Note: Disab l e at this lev el does n ot reload the timers on the enable. The timers are disab led at their current counts.
202 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 3 Keyboar d/Mouse Idle Timer Ena ble. T urn on K eyboard/Mouse Idle Timer Coun t Register (F0 Index 9Eh) and generate an SMI when the timer expires .
AMD Geode™ SC3200 Processor Data Book 203 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 82h Po wer Management Enable Register 3 (R/W) Re set V alue: 00h 7 Video Access T rap.
204 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 1 Floppy Disk Access T rap. 0: Disab le. 1: Enab le. If this bit is enabled and an access occurs in the address ranges listed below , an SMI is generated.
AMD Geode™ SC3200 Processor Data Book 205 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 2 Video Retrace Interrupt SMI. Allow SMI generation whenev er video retrace occurs. 0: Disab le. 1: Enab le. This inf or mation is decoded from the serial conn ection (PSERIAL r egister , bit 7) from the GX1 module.
206 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 85h Second Level PME/SMI Status Mirror Register 2 (RO) Reset Value: 00h The bits in this register c ontain second lev el status repor ting.
AMD Geode™ SC3200 Processor Data Book 207 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 86h Second Level PME/SMI Status Mirror Register 3 (RO) Reset Value: 00h The bits in this register c ontain second lev el status repor ting.
208 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 87h Second Level PME/SMI Status Mirror Register 4 (RO) Reset Value: 00h The bits in this register cont ain second lev el status repor ting.
AMD Geode™ SC3200 Processor Data Book 209 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 89h General Purpose Timer 1 Control Register (R/W) Reset V alue: 00h 7 General Purpose Timer 1 TImebase . Selects timebase for General Purpose Timer 1 (F0 Index 88h).
210 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 8Ah General Purpose Timer 2 Count Register (R/W) Reset V alu e: 00h 7:0 GPT2_COUNT . This field rep resents the load value f or General Purpose Timer 2 .
AMD Geode™ SC3200 Processor Data Book 211 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 8Eh V GA Timer Count Register (R/W) Re set V alue: 00h 7:0 V GA Tim er Load V alue . This field represents the load value for V GA Timer .
212 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 96h Su spend Configuration Register (R/ W) Re set V alue: 00h 7:3 Reserved. Must be set to 0. 2 Suspend Mode Conf iguration. Special 3V Suspend mode to suppor t powering down the GX1 module dur ing Suspend.
AMD Geode™ SC3200 Processor Data Book 213 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index 9Eh-9Fh Keyboard / Mouse Idle Timer Count Register (R/W) Rese t V alue: 0000h 15:0 Keyboar d / Mouse Idle Timer Coun t.
214 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index A Ch-ADh Secondary Hard Disk Idle Timer Count Reg ister (R/W) Reset V alue: 0000h 15:0 Secondary Hard Disk Idle Timer Count.
AMD Geode™ SC3200 Processor Data Book 215 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index B8h DMA Shadow Register (RO) Re set V alue: xxh 7:0 DMA Sha dow . This 8-bit port seq uences through the follo wing list of shadowed DMA Controller registers.
216 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index BBh R T C Index Shadow Register (R O) Reset V alue: xxh 7:0 RTC Index Shadow . The R T C Shadow register contains the last written value of the R TC Index register (I/O P or t 070h).
AMD Geode™ SC3200 Processor Data Book 217 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index CCh User Defined Device 1 Control Register (R/W) Reset V alue: 00h 7 Memory or I/O Mapp ed. Deter mines how User Defined Device 1 is mapped.
218 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Index ECh Timer T est Register (R/W) Reset V alue: 00h 7:0 Timer T est V alue . The Timer T est register is in tended only for test and deb ug pur poses.
AMD Geode™ SC3200 Processor Data Book 219 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 4 User Defined Device Idle Timer 1 (UDEF1) SMI Status. Indicates whether or not an SMI was caused by e xpiration of User Defined Device 1 (UDEF1) Idle Timer Count Register (F0 Inde x A0h).
220 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 3 Keyboar d/M ouse Access T rap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the ke yboard or mouse.
AMD Geode™ SC3200 Processor Data Book 221 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 2 Codec SD A T A_IN SMI Status. Indicates whether or not an SMI was ca used by AC97 Codec producing a positiv e edge on SD A T A_IN. 0: No .
222 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 6.4.1.1 GPIO Supp ort Registers F0 Inde x 10h, Base Address Register 0 (F0BAR0) poin ts to the base address of where the GPIO run time and configu- ration registers are located.
AMD Geode™ SC3200 Processor Data Book 223 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Offset 10h-13h GPDO1 — GPIO Data Out 1 Register (R/W) Reset V alue: FFFF FFFFh 31:0 GPIO Data Out. Bits [31:0] of this register correspond to GPIO63-GPIO32 signals, respective ly .
224 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 5:0 Signal Select. Selects the GPIO signal to be configured in the Bank se lected via bit 5 setting (i.e., Bank 0 or Bank 1). See T able 4-2 on page 70 f or GPIO ba ll muxing options.
AMD Geode™ SC3200 Processor Data Book 225 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 4 PME Edge/Level Select. Selects the type (edge or lev el) of the signal that issues a PME from the selected GPIO signal. 0: Edge input.
226 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 6.4.1.2 LPC Support Registers F0 Inde x 14h, Base Address Register 1 (F0BAR1) poin ts to the base address of the regist er space that contains the configuration registers for LPC suppor t.
AMD Geode™ SC3200 Processor Data Book 227 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 8 IRQ8# Source. Selects the interface source of the IRQ8# signal. 0: ISA - IRQ8# inter nal signal. (Connected to inter nal RTC .) 1: LPC - SERIRQ (ball J31).
228 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 14 IRQ14 P olar ity . If LPC is selected as the interface source f or IRQ14 (F0BAR1+I/O Offset 00h[14] = 1), this bit allows signal polarity s election.
AMD Geode™ SC3200 Processor Data Book 229 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 2 SMI# P o larity . This bit allows signal polar ity se lection of the SMI# generated from LPC. 0: Active high. 1: Active lo w . 1 IRQ1 Polarity .
230 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 2 DRQ2 Source. Selects the interface source of the DRQ2 signal. 0: ISA - DRQ2 (unava ilable e xter nally). 1: LPC - LDR Q# (ball L28).
AMD Geode™ SC3200 Processor Data Book 231 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 1 LPC Serial Port 0 Addressing. Serial P or t 0 addresses. See bit 16 for decode . Address selection made via F0BAR1+I/O Offset 14h[4:2].
232 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C Offset 18h-1Bh LAD_D1 — LPC Address D ecode 1 Register (R/W) Reset V alue: 00000000h 31:16 Reserved. Must be set to 0. 15:9 Wide Generic Base Address Select.
AMD Geode™ SC3200 Processor Data Book 233 Core Logic Module - Bridg e, GPIO, and LPC Registers - Function 0 32581C 3 LPC Timeout Err or Status. Indicates whether or not an error was generated by a timeout on LPC . 0: No . 1: Y es. Write 1 to clear. 2 LPC Error Write Status.
234 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 6.4.2 SMI Status an d A CPI Regi sters - Function 1 The register space design ated as Function 1 (F1) is used to configure the PCI por tion of suppor t hardware for the SMI Status and ACPI Support registe rs.
AMD Geode™ SC3200 Processor Data Book 235 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C 6.4.2.1 SMI Status Suppor t Registers F1 Index 10h, Base Address Register 0 (F1BAR0), p oints to the base address f or SMI Status register locations.
236 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 6 SMI Source is a V GA Timer Event. Indicates whether or not an SMI was caused by the e xpiration of the V GA Timer (F0 Index 8Eh). 0: No .
AMD Geode™ SC3200 Processor Data Book 237 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C 12 SMI Source is NMI. (Read to Clear) Indicates whether or not an SMI was caused by NMI activity . 0: No . 1: Y es. 11 SMI Source is IRQ2 of SIO Module .
238 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 1 SMI Source is A udio Subsystem. (Read Only , Read Does Not Clear) Indicates whethe r or not an SMI was caused by the audio subsystem.
AMD Geode™ SC3200 Processor Data Book 239 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C 0 SMI Source is Expired General Purpose Timer 1. Indicates whether or not an SMI wa s caused by the e xpiration of Gen- eral Pur pose Timer 1 (F0 Index 88h).
240 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C Offset 08h-09h SMI Speedup Disable Register (Read to Enable) Reset V alue: 0000h 15:0 SMI Speedup Disable.
AMD Geode™ SC3200 Processor Data Book 241 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Offset 22h-23h Second Level ACPI PME/SMI Status Register (RC) Reset V alue: 0000h The bits in this register cont ain second lev el of SMI status repor ting.
242 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 21 EXT_SMI5 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an asser tion of EXT_SMI5. 0: No . 1: Y es. T o enable SMI generation, set bit 5 to 1.
AMD Geode™ SC3200 Processor Data Book 243 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C 10 EXT_SMI2 SMI Status. (Read Only) Indicates whether or not an SMI was caused b y an asser tion of EXT_SMI2. 0: No . 1: Y es. T o enable SMI generation, set bit 2 to 1.
244 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 0 EXT_SMI0 SMI Enable. When this bit is asser ted, allow EXT_SMI0 to generate an SMI on negative-edge e vents. 0: Disab le. 1: Enab le.
AMD Geode™ SC3200 Processor Data Book 245 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C 6.4.2.2 A CPI Suppor t Registers F1 Index 40h, Base Address Register 1 (F1BAR1), p oints to the base addre ss of wher e the ACPI Suppor t registers are located.
246 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 0 PWRBTN_DBNC_DIS (Power Button Debounce). When enabled, a high-to-low or lo w- to-high transition of greater than 15.8 ms is required on PWRBTN# before it is recognized.
AMD Geode™ SC3200 Processor Data Book 247 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C 4 BM_STS (Bus Master Status). Indicates if PME was caused by a system bus master requesting the system bus. 0: No . 1: Y es. For the PME to gener ate an SCI, set F1BAR1+I/O Offset 0Ch[1] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1.
248 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 13 SLP_EN (Sleep Enable). (Write Only) Allow the system to sequence into the sl eeping state associated with the SLP_TYPx (bits [12:10]).
AMD Geode™ SC3200 Processor Data Book 249 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Offset 0Fh ACPI_BIOS_EN Register (R/W) Re set V alue: 00h 7:2 Reserved. Must be set to 0. 1 BIOS_RLS (BIOS Release). (Write Only) When this bit is asser ted, allow the BIOS to release control o f the global lock.
250 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 7 Reserved. Must be set to 0. 6 USB_STS. Indicates if PME was caused b y a USB interr upt ev ent. 0: No . 1: Y es. Write 1 to clear. For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[6] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1.
AMD Geode™ SC3200 Processor Data Book 251 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Offset 12h-13h GPE0_EN — General Purpose E ven t 0 Enable Register (R/W) Reset V alue: 0000h In order for the A CPI ev ents described below to generate an SCI, the SCI_EN bit must also be set (F1BAR1+I/O Offset 0Ch[0 ] = 1) .
252 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C Offset 14h GPWIO Control Register 1 (R/W) Re set V alue: 00h 7:4 Reserved. Must be set to 0. 3 Reserved. 2 GPWIO2_POL. Select GPWIO2 polarity .
AMD Geode™ SC3200 Processor Data Book 253 Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Offset 16h GPWIO Data Register (R/W) Reset V alue: 00h This register contains the direct values of the GPWIO2-GPWIO0 pins. Write operations are valid only f or bits defin ed as outputs .
254 AMD Geode™ SC3200 Processor Data Book Core Logic Module - SMI Sta tus and A C PI Registers - Function 1 32581C 3:0 SCI_IRQ_ROUTE. SCI is routed to: 0000: Disable 0100: IRQ4 1000: IRQ8 1100: IRQ1.
AMD Geode™ SC3200 Processor Data Book 255 Core Logic Module - IDE Controller Registers - Function 2 32581C 6.4.3 IDE Controller Regis ters - Function 2 The register space design ated as Function 2 (F2) is used to configure Channels 0 and 1 and the PCI por tion of sup- por t hardware fo r the IDE controllers.
256 AMD Geode™ SC3200 Processor Data Book Core Logic Module - IDE C ontroller Registers - Function 2 32581C Index 30h-3Fh Reserved Reset V alue: 00h Index 40h-43h Channel 0 Drive 0 PI O Register (R/W) Reset V alue: 00009172h If Index 44h[31] = 0, F or mat 0.
AMD Geode™ SC3200 Processor Data Book 257 Core Logic Module - IDE Controller Registers - Function 2 32581C Index 44h-47h Channel 0 Drive 0 DMA C ontrol Register (R /W) Reset V alue: 00077771h The structure of this register depends on the value of bit 20.
258 AMD Geode™ SC3200 Processor Data Book Core Logic Module - IDE C ontroller Registers - Function 2 32581C Index 50h-53h Channel 1 Drive 0 PI O Register (R/W) Reset V alue: 00009172h Channel 1 Drive 0 Programmed I/O Control Register . See F2 Index 40h f or bit descr iptions.
AMD Geode™ SC3200 Processor Data Book 259 Core Logic Module - IDE Controller Registers - Function 2 32581C 6.4.3.1 IDE Controller Support Registers F2 Index 20h, Base Address Register 4 (F2BAR4), p oints to the base address o f where the registers for IDE control- ler configuration are located.
260 AMD Geode™ SC3200 Processor Data Book Core Logic Module - IDE C ontroller Registers - Function 2 32581C Offset 08h IDE Bus Master 1 Co mmand Register — Secondar y (R/W) Reset V alue: 00h 7:4 Reserved. Must be set to 0. Must retur n 0 on reads.
AMD Geode™ SC3200 Processor Data Book 261 Core Logic Module - Audio Registers - Function 3 32581C 6.4.4 Audio Register s - Function 3 The register designated as Func tion 3 (F3) is used to con- figure the PCI por tion of suppor t hardware for the audio registers.
262 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Audio Registers - Function 3 32581C 6.4.4.1 A udio Suppor t Registers F3 Index 10h, Base Address Register 0 (F3BAR0), p oints to the base address of where the registers for audio sup- por t are located.
AMD Geode™ SC3200 Processor Data Book 263 Core Logic Module - Audio Registers - Function 3 32581C 16 Codec Status V alid. (Rea d Only) Indicates if the status in bits [15:0] of this r egister is valid. This bi t is high during slots 3 to 11 of the AC97 frame (i.
264 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Audio Registers - Function 3 32581C 4 Audio Bus Master 2 SMI Status. Indicates if an SMI was caused by an e vent occurring on Audio Bus Master 2. 0: No . 1: Y es. SMI generation is enabled when A udio Bus Maste r 2 is enabled (F3BAR0+Memory Offset 30h[0] = 1).
AMD Geode™ SC3200 Processor Data Book 265 Core Logic Module - Audio Registers - Function 3 32581C 4 Audio Bus Master 2 SMI Status. Indicates if an SMI was caused by an e vent occurring on Audio Bus Master 2. 0: No . 1: Y es. SMI generation is enabled when A udio Bus Maste r 2 is enabl ed (F3BAR0+Memory Offset 30h[0] = 1).
266 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Audio Registers - Function 3 32581C 12 DMA T rap SMI Status. (Read to Clear) Indicates if an SMI was caused by a trapped I/O access to the DMA I/O T rap. 0: No . 1: Y es. (See the note included in the general descr iption of this register abov e.
AMD Geode™ SC3200 Processor Data Book 267 Core Logic Module - Audio Registers - Function 3 32581C 5 Low MPU I/O T rap. If this bit is enabled and an access occurs at I/O Port 300h-301h, an SMI is gene rated. 0: Disab le. 1: Enab le. T op le vel SMI status is repor ted at F1BAR0+I/O Offset 00h/02h[1].
268 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Audio Registers - Function 3 32581C 7 IRQ7 Intern al. Configures IRQ7 for internal (so ftware) or e xternal (hardware) use. 0: Exter nal. 1: Internal. 6 Reserved. Must be set to 0. 5 IRQ5 Intern al.
AMD Geode™ SC3200 Processor Data Book 269 Core Logic Module - Audio Registers - Function 3 32581C 20 Mask Internal IRQ4. (Write Only) 0: Disab le. 1: Enab le. 19 Mask Internal IRQ3. (Write Only) 0: Disab le. 1: Enab le. 18 Reserved. (Write Only) Must be set to 0.
270 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Audio Registers - Function 3 32581C 1 Assert Masked Internal IRQ1. 0: Disab le. 1: Enab le. 0 Reserved. Must be set to 0. Offset 20h A udio Bus Master 0 Command Re gister (R/W) Re set V alue: 00h Audio Bus Master 0: Output to codec; 32-bit; Left and Right Channels; Slots 3 and 4.
AMD Geode™ SC3200 Processor Data Book 271 Core Logic Module - Audio Registers - Function 3 32581C Offset 28h A udio Bus Master 1 Command Re gister (R/W) Re set V alue: 00h Audio Bus Master 1: Input from codec; 32-Bit; Left and Right Channels; Slots 3 and 4.
272 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Audio Registers - Function 3 32581C Offset 30h A udio Bus Master 2 Command Re gister (R/W) Re set V alue: 00h Audio Bus Master 2: Output to codec; 16-Bit; Slot 5. 7:4 Reserved. Must be set to 0.
AMD Geode™ SC3200 Processor Data Book 273 Core Logic Module - Audio Registers - Function 3 32581C Offset 38h A udio Bus Master 3 Command Re gister (R/W) Re set V alue: 00h Audio Bus Master 3: Input from codec; 16-Bit; Slot 5. 7:4 Reserved. Must be set to 0.
274 AMD Geode™ SC3200 Processor Data Book Core Logic Module - Audio Registers - Function 3 32581C Offset 40h A udio Bus Master 4 Command Re gister (R/W) Re set V alue: 00h Audio Bus Master 4: Output to codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memor y Offset 08h[19] selects slot).
AMD Geode™ SC3200 Processor Data Book 275 Core Logic Module - Audio Registers - Function 3 32581C Offset 48h A udio Bus Master 5 Command Re gister (R/W) Re set V alue: 00h Audio Bus Master 5: Input from codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memory Offset 08h[20] sele cts slot).
276 AMD Geode™ SC3200 Processor Data Book Core Logic Module - X-Bus Expansi on Interface - Function 5 32581C 6.4.5 X-Bus Expansion Interface - Function 5 The register space design ated as Function 5 (F5) is used to configure the PCI por t ion of suppor t hardware for accessing the X-Bus Expansion suppor t registers.
AMD Geode™ SC3200 Processor Data Book 277 Core Logic Module - X-Bus Expansion Interface - Fu nction 5 32581C Index 1Ch-1Fh Base Address Register 3 - F5BAR3 (R/W) Reset V alue: 00000000h Reserved. Reser ved f or possible future use by the Core Logic module.
278 AMD Geode™ SC3200 Processor Data Book Core Logic Module - X-Bus Expansi on Interface - Function 5 32581C Index 44h-47h F5B AR1 Mask Address Regis ter (R/W) Reset V alue: 00000000h T o use F5BAR1, the mask register should be programmed first.
AMD Geode™ SC3200 Processor Data Book 279 Core Logic Module - X-Bus Expansion Interface - Fu nction 5 32581C Index 64h-67h Scratchpad: Usually used f o r Co nfiguration Block Address (R/W) Reset V alue: 00000000h BIOS writes a value, of t he Configuration Bloc k Address.
280 AMD Geode™ SC3200 Processor Data Book Core Logic Module - X-Bus Expansi on Interface - Function 5 32581C 6.4.5.1 X-Bus Expansio n Suppor t Registers F5 Index 10h, Base Address Register 0 (F5BAR0) set the base address that allows PCI access to addi tional I/O Con- trol suppor t registers.
AMD Geode™ SC3200 Processor Data Book 281 Core Logic Module - X-Bus Expansion Interface - Fu nction 5 32581C Offset 04h-07h I/O Control Regi ster 2 (R/W) Reset V alue: 00000002h 31:2 Reserved. Write as read. 1 Video Processor Access Enable. Allows access to video processor using F4BAR0.
282 AMD Geode™ SC3200 Processor Data Book Core Logic Module - USB Con troller Registers - PCIUSB 32581C 6.4.6 USB Controller Registers - PCIUSB The registers designated as PCIUSB are 32-bit registers decoded from the PCI address bits [7 :2] and C/BE[3:0]#, when IDSEL is high, AD[10:8] select the app ropriate func- tion, and AD[1:0] are 00.
AMD Geode™ SC3200 Processor Data Book 283 Core Logic Module - USB Controller Registers - PCIUSB 32581C Index 06h-07h Status Register (R/W) R eset V alue: 0280h The PCI specification defines this register to record status in f ormation for PCI rela ted ev ents.
284 AMD Geode™ SC3200 Processor Data Book Core Logic Module - USB Con troller Registers - PCIUSB 32581C Index 14h-2Bh Reserved Reset V a lue: 00h Index 2Ch-2Dh Subsystem V en dor ID (RO) Reset V alu.
AMD Geode™ SC3200 Processor Data Book 285 Core Logic Module - USB Controller Registers - PCIUSB 32581C T able 6-42. USB_B AR+Memory Offset: USB Co ntroller Regi sters Bit Description Offset 00h-03h HcRevision Register (R O) Reset V alue = 00000110h 31:8 Reserved.
286 AMD Geode™ SC3200 Processor Data Book Core Logic Module - USB Con troller Registers - PCIUSB 32581C 6 RootHubStatusChang e. This bit is set when th e content of HcRhStatus or the content of any HcRhP or tStatus register has changed. 5 FrameNumberOverflow .
AMD Geode™ SC3200 Processor Data Book 287 Core Logic Module - USB Controller Registers - PCIUSB 32581C 6 RootHubStatusChang eEnable. 0: Ignore. 1: Disable interrupt generation due to Root Hub Status Change. 5 FrameNumberOverflowEnable. 0: Ignore. 1: Disable interrupt generation due to Fr ame Numbe r Ov erflow .
288 AMD Geode™ SC3200 Processor Data Book Core Logic Module - USB Con troller Registers - PCIUSB 32581C Offset 34h-37h HcFmInterval Register (R/W) Reset V alue = 00002EDFh 31 FrameIntervalT oggle (Read On ly). This bit is toggled by HCD when it loads a new v alue into F rameInter val.
AMD Geode™ SC3200 Processor Data Book 289 Core Logic Module - USB Controller Registers - PCIUSB 32581C 7:0 NumberDownstreamP or ts (Read Only). USB suppor ts three downstream por ts. Note: This register is only reset by a pow er-on rese t (PCIRST#).
290 AMD Geode™ SC3200 Processor Data Book Core Logic Module - USB Con troller Registers - PCIUSB 32581C Offset 54h-57h HcRhPortStatus[1] Register (R/W) Reset V alue = 0000000 0h 31:21 Reserved. Read/Wr ite 0s. 20 P or tResetStatusChang e. This bit indicates that the por t reset signa l has completed.
AMD Geode™ SC3200 Processor Data Book 291 Core Logic Module - USB Controller Registers - PCIUSB 32581C 1 Read: PortEnableStatus. 0: P or t disabled. 1: P or t enabled. Write: SetP ortEnable. Writing a 1 sets PortEnableStatus. Writing a 0 has no effect.
292 AMD Geode™ SC3200 Processor Data Book Core Logic Module - USB Con troller Registers - PCIUSB 32581C 3 Read: Po rtOverCurrentInd icator . This bit reflects the state of the OVRCUR pi n dedicated to this por t. This field is only valid if NoOverCurrentProtection is cleared and Ov erCurre ntProtectionMode is set.
AMD Geode™ SC3200 Processor Data Book 293 Core Logic Module - USB Controller Registers - PCIUSB 32581C 8 Read: Po rtPowerS tatu s. This bit reflects the power state of the port regardless of the power s witching mode. 0: P or t pow er is off. 1: P or t pow er is on.
294 AMD Geode™ SC3200 Processor Data Book Core Logic Module - USB Con troller Registers - PCIUSB 32581C 1 EmulationInterrupt (Read Only). This bit is a static decode of the emulation interr upt condition.
AMD Geode™ SC3200 Processor Data Book 295 Core Logic Module - ISA Legacy Register Space 32581C 6.4.7 ISA Legacy Register Space The ISA Legacy registers reside in the ISA I/O address space in the address range from 000h to FFFh and are accessed through typical input/ output instructions (i.
296 AMD Geode™ SC3200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32581C 2 Channel 2 T erminal Co unt. Indicates if TC was reached. 0: No . 1: Y es. 1 Channel 1 T erminal Co unt. Indicates if TC was reached. 0: No . 1: Y es. 0 Channel 0 T erminal Co unt.
AMD Geode™ SC3200 Processor Data Book 297 Core Logic Module - ISA Legacy Register Space 32581C I/O Port 00Bh DMA Channel Mode Register , Channels 3:0 (WO) 7:6 T r ansfer Mode. 00: Demand. 01: Single. 10: Bloc k. 11: Cascade. 5 Address Direction. 0: Increment.
298 AMD Geode™ SC3200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32581C I/O Port 0D0h (R/W) Read DMA Status Register , Channels 7:4 Note: Channels 5, 6, and 7 are not suppor ted. 7 Channel 7 Request. Indicates if a request is pending.
AMD Geode™ SC3200 Processor Data Book 299 Core Logic Module - ISA Legacy Register Space 32581C I/O Port 0D2h Software DMA Request Register , Channels 7:4 (W) Note: Channels 5, 6, and 7 are not suppor ted. 7:3 Reserved. Must be set to 0. 2 Request T y pe.
300 AMD Geode™ SC3200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32581C I/O Port 0DEh DMA Write Mask Register Command, Channels 7:4 (W) Note: Channels 5, 6, and 7 are not suppor ted. T able 6-43. DMA Chan nel Control Registers (Continued) Bit Description T able 6-44.
AMD Geode™ SC3200 Processor Data Book 301 Core Logic Module - ISA Legacy Register Space 32581C T able 6-45. Programmable Inter val Timer Regist ers Bit Description I/O Port 040h Write PIT Timer 0 Counter 7:0 Counte r V alue. Read PIT Timer 0 Statu s 7 Counter Ou tput.
302 AMD Geode™ SC3200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32581C I/O Port 042h Write PIT Timer 2 Counter (Speaker) 7:0 Counte r V alue. Read PIT Timer 2 Status (Spea ker) 7 Counter Ou tput. State of counter output signal.
AMD Geode™ SC3200 Processor Data Book 303 Core Logic Module - ISA Legacy Register Space 32581C T able 6-46. Programmab le Interrupt Contr oller Registers Bit Description I/O Po rt 020h / 0A0h Master / Slave PIC ICW1 (WO) 7:5 Reserved. Must be set to 0.
304 AMD Geode™ SC3200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32581C 2 IRQ2 / IRQ10 Mask. 0: Not Masked. 1: Mask. 1 IRQ1 / IRQ9 Mask. 0: Not Masked. 1: Mask. 0 IRQ0 / IRQ8 Mask. 0: Not Masked. 1: Mask. I/O Port 020h / 0A0h Master / Slave PIC OCW2 (WO) 7:5 Rotate/EOI Codes.
AMD Geode™ SC3200 Processor Data Book 305 Core Logic Module - ISA Legacy Register Space 32581C 3 IRQ3 / IRQ11 Pending. 0: Y es. 1: No . 2 IRQ2 / IRQ10 Pending. 0: Y es. 1: No . 1 IRQ1 / IRQ9 Pending. 0: Y es. 1: No . 0 IRQ0 / IRQ8 Pending. 0: Y es. 1: No .
306 AMD Geode™ SC3200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32581C T able 6-47. Keyboa rd Controll er Register s Bit Description I/O Port 060h External Keyboar d Controller Data Register (R/W) Keyboar d C ontroller Data Register .
AMD Geode™ SC3200 Processor Data Book 307 Core Logic Module - ISA Legacy Register Space 32581C T able 6-48. Real-Time Cloc k Registers Bit Description I/O Po rt 070h RTC Address Register (WO) This register is shadowed within the Core Logic module and is read through the RTC Shadow Register (F0 Inde x BBh).
308 AMD Geode™ SC3200 Processor Data Book Core Logic Module - ISA Le gacy Register Space 32581C 3 IRQ3 Edge or L evel Sensitive Select. Selects PIC IRQ3 sensitivity configuration. 0: Edge . 1: Le vel. 2:0 Reserved . Must be set to 0. I/O Port 4D1h Interrupt Edg e/Level Select Register 2 (R/W) Re set V alue: 00h Notes: 1.
AMD Geode™ SC3200 Processor Data Book 309 7 Video Processor Module 32581C 7.0 Video Processor Module The Video Processor module co ntains a high performance video back-end accelerator , a video/graphics Mixer/ Blender , a Video Input Port (VIP), suppor ting a TFT inter- f ace.
310 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C 7.1 Module Ar chitecture Figure 7-1 shows a top-lev el block diagram of the Video Processor . For inf or mation abou t the relationship between the Video Processor an d the other modules of th e SC3200, see Section 2.
AMD Geode™ SC3200 Processor Data Book 311 Video Processor Module 32581C 7.2 Functional Description T o understand why the Video Processor functions as it does, it is first impor tant to understand the difference between video and graphics. Video is pictures in motion, which usua lly star ts out in an encod ed f or mat (i.
312 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C Figure 7-2. NTSC 525 Lines, 60 Hz, Odd Field Figure 7-3. NTSC 525 Lines, 60 Hz, Even Field V er t ical Retrace - Logical Lines.
AMD Geode™ SC3200 Processor Data Book 313 Video Processor Module 32581C 7.2.1 Video Inp ut P or t (VIP) The VIP block is designed to interface the SC3200 with e xterna l video processors (e.g., Philips PNX1300 or Sigma Designs EM8400) or external TV decode rs (e.
314 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C The GenLock control hardware is used to synch ronize the video input’ s fiel d with the GX1 module’ s graphics frame .
AMD Geode™ SC3200 Processor Data Book 315 Video Processor Module 32581C Figure 7-5. Capture Video Mode Bob Example Using On e Video Frame Buffer We av e The Wea ve method assembles the odd field and e ven field together to form the complete frame, and then renders the “wea ved” frames to the displa y de vice.
316 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C 3) Field Interrupt. When the field interr upt occurs on the completion of a n odd field, the interr upt must program the Video Data Odd Base Address with the other buff er’s address.
AMD Geode™ SC3200 Processor Data Book 317 Video Processor Module 32581C 7.2.2 Video Block The Video block rece ives video data from the VIP block or the GX1 module’ s video frame buffer . Th e video data is for- matted and scaled and then sent to the Mixer/Blender .
318 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C 7.2.2.2 Horizontal Downscal er with 4 -T ap Fi ltering The Video Processor implements up to 8:1 hor izontal downscaling with 4-tap filter ing for horizontal inter polati on. Filter ing is performed on vi deo data input to the Video Pro- cessor .
AMD Geode™ SC3200 Processor Data Book 319 Video Processor Module 32581C 7.2.2.3 Line Buffer s After the data has been option ally horizontally downscaled the video data is stored in a 3- line buff er . Each li ne is 360 D WORDs, which means a line width of up to 720 pixels can be stored.
320 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C 7.2.3 Mixer/Blende r Block The Mixer/Blender bloc k of the Video Pro cessor module perf orm s all the necessar y functions to proper ly mix/blend the video data and the graphics data.
AMD Geode™ SC3200 Processor Data Book 321 Video Processor Module 32581C 7.2.3.1 YUV to RGB CSC in Video Data Path This CSC must be enabled if the video data is in the YUV color space. The CSC_FOR_ VIDEO bit, F4BAR0+Memor y Offset 4Ch[10], controls this CSC .
322 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C 7.2.3.4 Color/Chroma K ey and Mixer/Blender The Mixer/Blender takes each pix el of the graphics and video data streams and mi x es o r blends them together . Mixing is simply choosing the graphics pix el or the video pixel.
AMD Geode™ SC3200 Processor Data Book 323 Video Processor Module 32581C Mixing/Blendin g Operation T able 7-2 on page 323 shows the tr uth table used to create th e flow diagram, Figure 7-12 on page 3 24, that the Mixer/ Blender logic uses to deter mine each pixels disposition.
324 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C Figure 7-12. Color Ke y and Alpha Blending Logic Color register enabled f or this window “Graphics 2 inside Video” is enab.
AMD Geode™ SC3200 Processor Data Book 325 Video Processor Module 32581C 7.2.4 TFT I nterface The TFT interf ace can be programmed to one of two sets of balls: IDE balls or Par allel P or t balls. PMR[23] of the Gen- eral Co nfigur ation registers prog ram where the TFT inte r- f ace e xists (see T able 4-2 on page 70).
326 AMD Geode™ SC3200 Processor Data Book Video Processor Module 32581C 7.2.5 Integrated PL L The integrated PLL can gen erate frequencies up to 135 MHz from a single 27 MH z source. The clock frequency is programmable using two registers . Figure 7-14 shows the bloc k di agram of the Video Processor integ rated PLL.
AMD Geode™ SC3200 Processor Data Book 327 Video Processor Module - Register Summary 32581C 7.3 Register Descriptions The register space for accessing and configur ing the Video Processor is located in the Co re Logic Chipset Register Space (F0-F5).
328 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Register Summary 32581C 28h-2Bh 32 R/W Miscellaneous Register 00001400h Page 336 2Ch-2Fh 32 R/W PLL2 Clock Select Register 00000000.
AMD Geode™ SC3200 Processor Data Book 329 Video Processor Module - Register Summary 32581C T able 7-5. F4BAR2: VIP Support Registers Summary F4BAR2+ Memory Offset Width (Bits) T ype Name Reset Va l .
330 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C 7.3.2 Video Processo r Register s - Function 4 The register space design ated as Func.
AMD Geode™ SC3200 Processor Data Book 331 Video Processor Module - Video Processor Registers - Function 4 32581C Index 3Dh Interrupt Pin Register (R/W) Reset V alue: 03h This register selects which interrupt pin the device uses. VIP uses INTC# after reset.
332 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C 7.3.2.1 Video Proc essor Support Registe rs - F4B AR0 F4 Index 10h, Base Address Re gister 0 (F4BAR0) sets th e base address that allows PCI access to the Video Proces- sor suppor t registers, not including VIP .
AMD Geode™ SC3200 Processor Data Book 333 Video Processor Module - Video Processor Registers - Function 4 32581C 0 VID_EN (Video Enable). Enables video acceleration hardware .
334 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C Offset 08h-0Bh Video X P osition Register (R/W) Reset V alue: 00000000h Provides the windo w X position. Th is register is programmed relativ e to CRT horiz ontal sync input (not ph ysical screen position ).
AMD Geode™ SC3200 Processor Data Book 335 Video Processor Module - Video Processor Registers - Function 4 32581C Offset 14h-17h Video Color Key Re gister (R/W) Reset V alue: 00000000h Provides the video color k ey .
336 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C Offset 28h-2Bh Mis cellaneous Register (R/W) Reset V alue: 00001400h Configuration and control register for miscell aneous characteristics of the Video Processor.
AMD Geode™ SC3200 Processor Data Book 337 Video Processor Module - Video Processor Registers - Function 4 32581C Offset 3Ch-3Fh Video Downscaler Cont r o l Register (R/W) Reset V alue: 00000000h Controls the characteristics of the inte grated video do w nscaler .
338 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C Offset 4Ch-4Fh Video De-Interlacing and Al ph a Control Register (R/W) Reset V alue: 00060000h 31:22 Reserved. 21:20 ALPHA3_WIN_PRIORITY (Alpha Wind ow 3 Priority).
AMD Geode™ SC3200 Processor Data Book 339 Video Processor Module - Video Processor Registers - Function 4 32581C 8 GFX_INS_VIDEO (Graphics Inside Video).
340 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C Offset 60h-63h Alpha Window 1 X P osi tion Register (R/W) Reset V alue: 00000000h Not.
AMD Geode™ SC3200 Processor Data Book 341 Video Processor Module - Video Processor Registers - Function 4 32581C Offset 70h-73h Alpha Window 2 X P osi tion Register (R/W) Reset V alue: 00000000h Not.
342 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C Offset 80h-83h Alpha Window 3 X P osi tion Register (R/W) Reset V alue: 00000000h Not.
AMD Geode™ SC3200 Processor Data Book 343 Video Processor Module - Video Processor Registers - Function 4 32581C Offset 90h-93h Video Request Register (R/W) Reset V al ue: 001B0017h 31:28 Reserved. Set to 0. 27:16 VIDEO_X_REQ (Video Horizontal Request).
344 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C Offset 420h-423h GenLock Regi ster (R/W) Reset V alue: 00000000h 31:24 Reserved. Must be set to 0. 23 ODD_T O (Odd Fie ld Time Ou t). Indicates CGENTO 0 (F4BAR0+Memor y Offset 43Ch[15:0]) has expired.
AMD Geode™ SC3200 Processor Data Book 345 Video Processor Module - Video Processor Registers - Function 4 32581C 7.3.2.2 VIP Support Registers - F4BAR2 F4 Inde x 18h, Base Address Register 2 (F4BAR2) poin ts to the base address of where the VIP Configuration registers are located.
346 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C 10 Auto-Flip. Video port operation mo de. 0: The video por t automatically detects the e ven and odd fi elds based on the VP_HREF and VP_VSYNC_IN signals or the CCIR656 control codes.
AMD Geode™ SC3200 Processor Data Book 347 Video Processor Module - Video Processor Registers - Function 4 32581C 8 Video Data Captur e Active. (Read Only) 0: Video data is not being stored to memor y . 1: Video data is now being stored to memor y . 7:1 Reserved.
348 AMD Geode™ SC3200 Processor Data Book Video Processor Module - Video Processor Registers - Function 4 32581C Offset 40h-43h VBI Data Odd Base Register (R/W) Reset V alue: 00000000h This register specifies the base address in graphics memor y where VBI data for odd fields are stored.
AMD Geode™ SC3200 Processor Data Book 349 8 Debu gging and Monitoring 32581C 8.0 Deb ugging and Monitor ing 8.1 T estability (JT A G) The T est Access P or t (T AP) allows board le vel interconnec- tion verification and chip production tests. An IEEE- 1149.
350 AMD Geode™ SC3200 Processor Data Book Debu gging and Monitoring 32581C.
AMD Geode™ SC3200 Processor Data Book 351 9 Electrical Specifications 32581C 9.0 Electr ical Specifications This chapter provides inf or mation abo ut: • General electrical specificatio ns • DC characteristics • A C character istics All voltage v alues in this chap ter are with respect to V SS unless otherwise noted .
352 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.1.4 Operating Conditions T able 9-3 lists the various power supplies of the SC3200 and provides the device operating conditions . Notes: 1) All power sources except V BA T must be connected, even if the function is not used.
AMD Geode™ SC3200 Processor Data Book 353 Electrical Specifications 32581C T able 9-4 indicates whic h power r ails are used for each signal of the SC3 200 e xter nal interface. P ow er planes not listed in this table are interna l, and are not related to signals of the e xte rnal interface.
354 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.1.5.3 Definition of Sy stem Conditions f or Measuring On P ara meters The SC3200’ s current is highly depende nt on two func- tional characteristics, DCLK (DOT clock) and SDRAM fre- quency .
AMD Geode™ SC3200 Processor Data Book 355 Electrical Specifications 32581C 9.1.6 Ball Capacitance and Inductance T able 9-8 gives ball capacitance and inductance values . T able 9-7. DC Characteristics f or Active Idle, Sleep, a nd Off States Symbol ParameterNote 1 Min T yp Max Unit Comments I CC3IDLE f CL K = 233 MHz, I/O Current @ V IO = 3.
356 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.1.7 Pull-Up and Pull- Down Resistors The follo wing table lists input balls that are internal ly con- nected to a pull-up (PU) or pull-d own (PD) resistor . If these balls are not used, they do not require connection to an e xternal PU or PD resistor .
AMD Geode™ SC3200 Processor Data Book 357 Electrical Specifications 32581C 9.2 DC Characteristics T able 9-10 descri bes the signal buffer types of the SC3200.
358 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.2.1 IN AB DC Characteristics 9.2.2 IN BTN DC Characteristics 9.2.3 IN PCI DC Characteristics Note that the b uffer type f or PCICLK (ball A7) is IN T - not IN PCI . Symbol P a rameter Min Max Unit Comments V IH Input Hi gh V oltage 1.
AMD Geode™ SC3200 Processor Data Book 359 Electrical Specifications 32581C 9.2.4 IN STRP DC Characteristics 9.2.5 IN T DC Characteristics 9.2.6 IN TS DC Characteristics 9.2.7 IN TS1 DC Characteristics Symbol P a rameter Min Max Unit Comments V IH Input Hi gh V oltage 0.
360 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.2.8 IN USB DC Characteristics Figure 9-1. Differential Input Sensitiv ity f or Common Mode Range 9.2.9 O AC9 7 DC Characteristics 9.2.10 OD n DC Characteristics Symbol P a rameter Min Max Unit Comments V IH Input Hi gh V oltage 2.
AMD Geode™ SC3200 Processor Data Book 361 Electrical Specifications 32581C 9.2.11 OD PCI DC Ch aracteristic s 9.2.12 O p/n DC Characterist ics 9.2.13 O PCI DC Characteristics 9.2.14 O USB DC Characteristics 9.2.15 TS p/n DC Characteristic s 9.2.15.1 Exceptions 1) I OH is valid f or a GPIO pin only when it is not configured as op en-drain.
362 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3 A C Characteristics The tables in this section list the following A C character is- tics: • Output delays • Input s.
AMD Geode™ SC3200 Processor Data Book 363 Electrical Specifications 32581C 9.3.1 Memor y Controller Int erface The minimum input setup and hold ti mes described i n Figure 9- 3 (legend C an d D) define the smallest acce ptable sampling window during which a synchronou s input signal must be stable to ensure correct operation.
364 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C T able 9-12. Memory C ontroller Timing Parameters Symbol P a rameter Min Max Unit Comments t 1 Control output valid from SDCLK[3:0] -3.0 + (x * y) 0.1 + (x * y) ns Note 1, Note 2 t 2 MA[12:0], BA[1.
AMD Geode™ SC3200 Processor Data Book 365 Electrical Specifications 32581C Figure 9-4. Memory Controller Output V alid Timing Diagram Figure 9-5. Read Data In Setup and Hold Timing Diagram SDCLK[3:0.
366 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.2 Video Port Figure 9-6. Video Input P or t Timing Diagram T able 9-13.
AMD Geode™ SC3200 Processor Data Book 367 Electrical Specifications 32581C 9.3.3 TFT I nterface Figure 9-7. TFT Timing Diagram T able 9-14. TFT Timing P arameters Symbol P aramete r Min Max U nit Co.
368 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.4 ACCESS.b us Interface The f ollowing tab les describe the timing f or the ACCESS .bus sig nals. Notes: 1) All ACCESS.b u s timing is not 100% tested. 2) In this table t CLK = 1/24MHz = 41.
AMD Geode™ SC3200 Processor Data Book 369 Electrical Specifications 32581C Figure 9-8. A CB Signals: Rising Time and F alling Timing Diagram Figure 9-9.
370 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9 -10. A CB Star t Condit ion Timing Diagram Figure 9-11. ACB Data Bit Timing Dia gram t CSTRsi t DHCsi Star t Condi.
AMD Geode™ SC3200 Processor Data Book 371 Electrical Specifications 32581C 9.3.5 PCI Bus In terface The SC3200 is complia nt with PCI Bus Rev . 2.1 specifica- tions. Rele vant information from the PCI Bus specifications is provided below . All parameters in T a ble 9-17 are not 100% tested.
372 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-13. V/I Curve s for PCI Output Signals Pull-Up Pull-Down T est P oint V IO 0.9 V IO DC Drive P oint AC Drive P oint 0.3 V IO 0.6 V IO 0.1 A C Drive P oint DC Drive P oint T est P oint V IO Equation A fo r V IO >V OUT >0.
AMD Geode™ SC3200 Processor Data Book 373 Electrical Specifications 32581C Figure 9-14. PCICLK Timing and Measurement P oints T able 9-18. P CI Clock P a rameters Symbol Parameter Min Max Unit Comme.
374 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-15. Load Circuits for Ma ximum Time Measurements T able 9-19. PCI Timing Parameters Symbol Parameter Min Max U nit.
AMD Geode™ SC3200 Processor Data Book 375 Electrical Specifications 32581C 9.3.5.1 Measurement and T est Conditions Figure 9 -16. Outpu t Timing Measur ement Cond itions T able 9-20. Measurement Condition P arameters Symbol V alue Unit Comments V TH 0.
376 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-17. Input Timing Measurement Conditions Figure 9-18. PCI Reset Timing V TEST V TEST Input V alid t SU t H V TEST V.
AMD Geode™ SC3200 Processor Data Book 377 Electrical Specifications 32581C 9.3.6 Sub-ISA Int erface All output timing is guaranteed for 50 pF load, unle ss other- wise specified. The ISA Clock divisor (defined in F0 Index 50h[2:0] of the Core Logic module) is 011.
378 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C t RD Y A2 IOCHRD Y valid after IOR#/MEMR#/ RD#/DOCR# /IOW#/M EMW#/WR#/ DOCW# F E 8 M, I/O 366 9-19 9-20 t IOCSA IOCS[1:0]#/.
AMD Geode™ SC3200 Processor Data Book 379 Electrical Specifications 32581C Figure 9-19. Sub-ISA Read Operation Timing Diagram t RDx t ARx Valid Valid Valid Data t RCUx t RA t RVDS t RDH t HZ A[23:0].
380 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-20. Sub-ISA Write Opera tion Timing Diagram t WRx t AWx Valid Valid Valid Data t WCUx t WA t DH A[23:0]/BHE# TRDE#.
AMD Geode™ SC3200 Processor Data Book 381 Electrical Specifications 32581C 9.3.7 LPC Interface Figure 9-21. LPC Output Timing Diagram Figure 9-22. LPC Input Timing Diagram T able 9-22.
382 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.8 IDE Interfa ce Figure 9-23. IDE Reset Timing Diagram T able 9-23. IDE Genera l Timing P arameters Symbol Parameter Min Max Unit Comments t IDE_F ALL IDE signals fall time (from 0.
AMD Geode™ SC3200 Processor Data Book 383 Electrical Specifications 32581C T able 9-24. IDE Register T ransf er to/fr om Device Timing P arameters Symbol P arameter Mode Unit Comments 01235 t 0 Cycl.
384 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-24. Register T ransf er to/fr om Device Timing Diagram ADDR valid 1 WRITE READ t 0 t 1 t 2 t 9 t 2i t 3 t 5 t 6z t.
AMD Geode™ SC3200 Processor Data Book 385 Electrical Specifications 32581C T able 9-25. IDE PIO Data T ransfer to/ fr om Device Timing Parameters Symbol P arameter Mode Unit Comments 01234 t 0 Cycle.
386 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9- 25. PIO Data T ransfer to/from Device Timing Diagram ADDR valid 1 WRITE IDE_DATA[15:0] READ IDE_DATA[15:0] t 0 t .
AMD Geode™ SC3200 Processor Data Book 387 Electrical Specifications 32581C T able 9-26 . IDE Multiw ord DMA Data T ransfer Timing P arameters Symbol P arameter Mode Unit Comments 012 t 0 Cycle time .
388 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-26. Multiwor d DMA Data T ransfer Timing Diagram t M t N t L t j t K t D t I t E t Z t F t G t G t H t 0 IDE_CS[1:.
AMD Geode™ SC3200 Processor Data Book 389 Electrical Specifications 32581C T able 9-27 . IDE UltraDMA Data Bu rst Timin g Parameter s Symbol P arameter Mode 0 Mode 1 Mode 2 Unit Comments Min Max Min.
390 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C All timing parameters are measured at the connector of the device to which the parameter applies. For e xample, the sender stops generating STROBE edges t RFS after the negation of DMARD Y .
AMD Geode™ SC3200 Processor Data Book 391 Electrical Specifications 32581C Figure 9-28. Sustained UltraDMA Data In Bur st Timing Diagram t DS t DH t DS t DH t DH t DVH t DVS t DVH t DVS t DVH t 2CYC.
392 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-29. Host P ausing an UltraDMA Data In Burst Timing Diagram t RP IDE_D A T A[15:0] (de vice) t RFS t SR IDE_IRD Y0 .
AMD Geode™ SC3200 Processor Data Book 393 Electrical Specifications 32581C Figure 9-30. Device T erminating an Ultr aDMA Da ta In Burst Timing Dia gram IDE_D A T A[15:0] (de vice) IDE_CS[0:1]# IDE_A.
394 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-31. Host T erminatin g an UltraDMA Data In Bur st Timing Diagram IDE_D A T A[15:0] (de vice) IDE_CS[0:1]# IDE_ADDR.
AMD Geode™ SC3200 Processor Data Book 395 Electrical Specifications 32581C Figure 9-32. Initiating an UltraDMA Data Out Burst Timing Diagram IDE_D A T A[15:0] (de vice) IDE_CS[0:1]# IDE_ADDR[2:0] t .
396 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-33. Sustained UltraDMA Data Out Bur st Timing Diagram t DS t DH t DS t DH t DH t DVH t DVS t DVH t DVS t DVH t 2CY.
AMD Geode™ SC3200 Processor Data Book 397 Electrical Specifications 32581C Figure 9 -34. Device Pausing an Ult raDMA Da ta Out Burst Tim ing Diagram t RP IDE_D A T A[15:0] (host) t RFS t SR IDE_IOR0.
398 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-35. Host T erminating an UltraDMA Data Out Bur st Timing Diagram IDE_D A T A[15:0] (host) IDE_CS[0:1]# IDE_ADDR[2:.
AMD Geode™ SC3200 Processor Data Book 399 Electrical Specifications 32581C Figure 9-3 6. Device T erminating an UltraDMA Data Out Burst Timing Diagram IDE_D A T A[15:0] (host) IDE_CS[0:1]# IDE_ADDR[.
400 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.9 Universal Se rial Bus (USB) Interface T able 9-28 . USB Timing Parameters Symbol P arameter Min Ma x Unit Figur e Com.
AMD Geode™ SC3200 Processor Data Book 401 Electrical Specifications 32581C t USB_DJU22 Source diff e rential driver jitter for paired transactions –150 15 0 ns 9-38 Function (downstream), Note 4 t USB_SE2 Source EOP width 1.
402 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-37. Data Signal Rise and F all Timing Diagram Figure 9-38. Source Differenti al Data Jitter Ti ming Diagram Rise T.
AMD Geode™ SC3200 Processor Data Book 403 Electrical Specifications 32581C Figure 9-39. EOP Width Timing Diagram Figure 9-40 . Receiver J itter T oleran ce Timing Di agram EOP Width Data Crossov er .
404 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.10 Se rial P o rt (U ART) Figure 9-41. U ART , Sharp-IR, SIR, and C onsumer Remote Co ntrol Timing Diagram T able 9-29.
AMD Geode™ SC3200 Processor Data Book 405 Electrical Specifications 32581C 9.3.11 Fast IR Port Figure 9-42. Fast IR (MIR and FIR) Timing Dia gram T able 9- 30.
406 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.12 Parallel Port Interfa ce Figure 9-43. Standar d Parallel P or t T ypical Data Exchange Timing Diagram T able 9-31 .
AMD Geode™ SC3200 Processor Data Book 407 Electrical Specifications 32581C Figure 9-44. Enhanced P arallel P or t Timing Diagram T able 9- 32. Enhanced P arallel P ort Timing P arameters Symbol P arameter Min Max EPP 1.
408 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.12.1 Extende d Capab ilities P or t (ECP) Figure 9-45. ECP Forward Mode Timing Diagram T able 9-33.
AMD Geode™ SC3200 Processor Data Book 409 Electrical Specifications 32581C Figure 9-46. ECP Reverse Mod e Timing Diagram T able 9-34. ECP Reverse Mod e Timing Parameter s Symbol P a rameter Min Max .
410 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.13 Audio Interface (A C97) Figure 9-47. A C97 Reset Timing Dia gram Figure 9-48. A C97 Sync Timing Diagram T able 9-35. AC Reset Timing Parameters Symbol P aramete r Min T yp Max Unit Comments t RST_LO W AC97_RST# activ e low pulse width 1.
AMD Geode™ SC3200 Processor Data Book 411 Electrical Specifications 32581C Figure 9-49. A C97 Cloc ks Diagram T able 9-37. A C97 Clocks P arameters Symbol Parameter Min T yp Max Unit Comments F BIT_CLK BIT_CLK frequency 12.288 MHz t CLK_PD BIT_CLK period 81.
412 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-50. AC97 Data TIming Diagram T able 9-38 . A C97 I/O Timing Parameters Symbol Parameter Min T yp Max Unit Comments t AC 97_S Input setu p to f alling edge of BIT_CLK 15.
AMD Geode™ SC3200 Processor Data Book 413 Electrical Specifications 32581C Figure 9-51. AC97 Rise and F all Timing Diagram T able 9-39. A C97 Signal Rise and Fall Timi ng P arameters Symbol Paramete.
414 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C Figure 9-52. A C97 Low P ower Mode Timing Diagram T able 9- 40. A C97 Low P ower Mode Timing Parameter s Symbol Parameter Min T yp Max Unit Comments t s2_pdow n End of Slot 2 to BIT_CLK, SD A T A_IN low 1.
AMD Geode™ SC3200 Processor Data Book 415 Electrical Specifications 32581C 9.3.14 Po we r Management I nterface LED# Cycle time: 1 s ± 0.1 s, 40%-60% duty cycle . Figure 9-53. PWRBTN# T rigger and ONCTL# Timing Diagram Figure 9-54. GPWIO and ONCTL# Timing Diagram T able 9-41.
416 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.15 Po we r-Up Sequencing Figure 9-55. Po wer-Up Sequenci ng With PWRBTN# Timing Diagr am T able 9-43.
AMD Geode™ SC3200 Processor Data Book 417 Electrical Specifications 32581C Figure 9-56. P ower -Up Sequencing Without PWRBTN# Timing Diagram A CPI is n on-functional and all ACPI outputs are undefi ned when the power-up sequence does not include u sing the power button.
418 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C 9.3.16 JT A G Interface Figure 9-57. TCK Measurement P oints and Timing Diagram T able 9-45 .
AMD Geode™ SC3200 Processor Data Book 419 Electrical Specifications 32581C Figure 9-58. JT A G T est Timing Diagram TCK t 8 Input Output TDO TDI, t 11 t 13 t 9 t 7 t 6 t 12 t 10 TMS Signals Signals.
420 AMD Geode™ SC3200 Processor Data Book Electrical Specifications 32581C.
AMD Geode™ SC3200 Processor Data Book 421 10 Pac kage Specifications 32581C 10.0 P ac kage Specifications 10.1 Thermal Characteristics The junction-to-case ther mal resistance ( θ JC ) of the pac k- ages shown in T able 10-1 can be used to calculate the junction (die) temperature under any given circumstance.
422 AMD Geode™ SC3200 Processor Data Book Pac kage Specificatio ns 32581C 10.1.1 Heatsi nk Considerations T able 10-2 on page 421 shows the maximum allowed ther- mal resistance of a heatsink for par ticular operating envi- ronments.
AMD Geode™ SC3200 Processor Data Book 423 Pac kage Specifications 3258 1C 10.2 Physical Dimensions The figures in this section provide the mechanical package outl ine f o r the BGU481 (481-T er minal Ball Grid Arra y Cavity Up) package. Figure 10-2.
424 AMD Geode™ SC3200 Processor Data Book Pac kage Specificatio ns 32581C Figure 10-3. BGU481 P ackage - Bottom Vie w.
AMD Geode™ SC3200 Processor Data Book 425 Appendix A: Suppor t Document ation 32581C Appendix A Suppor t Documentation A.1 Order Inf ormation Ordering P a rt Numb er (AMD OPN) 1 1. The “F” suffix denotes the Pb-free (lead-free) package. See Section 10.
426 AMD Geode™ SC3200 Processor Data Book Appendix A: Data Bo ok Revision History 32581C A.2 Data Book Revision History This document is a repo r t of the revi sion/creation process of the data book fo r the AMD Geode™ SC320 0 processor . Any re vi sions (i.
AMD Geode™ SC3200 Processor Data Book 427 Appendix A: Data Book Revision Histor y 32581C C (F ebruar y 2 007) T able 9-3 "Operating Conditions" on page 352: Change maximum VCORE and VSBL values from 1.
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