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AMD SB600 Register Reference Manual (Public Version) Technical Reference Manual Rev. 3.03 P/N: 46155_sb600 _rrg_pub_3.03 ©2008 Advanced Micro De vices, Inc.
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© 2008 Advanced Micro De vices, Inc. Table of Contents AMD SB600 Register Referen ce Manual Proprietary Page 3 Table of Contents 1 Introducti on .........................................................................................................
© 2008 Advanced Micro De vices, Inc. List of Figures AMD SB600 Register Referen ce Manual Proprietary Page 4 2.5 AC ’97 Controller Func tional Descriptions ................................................................................. 198 2.5.1 Audio Registers (Device 20, Func tion 5) .
© 2008 Advanced Micro De vices, Inc. List of Figures AMD SB600 Register Referen ce Manual Proprietary Page 5 List of Figures Figure 1 SB600 PCI In ternal De vices .......................................................................................
© 2008 Advanced Micro De vices, Inc. List of Tables AMD SB600 Register Referen ce Manual Proprietary Page 6 List of Tables Table 1-1: Register Descripti on Table Nota tion—Exa mple ...................................................................
© 2008 Advanced Micro De vices, Inc. About this Manual AMD SB600 Register Referen ce Manual Proprietary Page 7 1 Introduction 1.1 About this Manual This manual is a register referen ce guide for the AMD SB600 Southbridge. It integrates the key I/O, communications, an d audio features required in a st ate-of-t he-art PC into a single device.
© 2008 Advanced Micro De vices, Inc. Nomenclature and Conventions AMD SB600 Register Referen ce Manual Proprietary Page 8 Register Information Value/Content in the Example Register name Latency Timer.
© 2008 Advanced Micro De vices, Inc. Features of the SB600 AMD SB600 Register Referen ce Manual Proprietary Page 9 1.3 Features of the SB600 CPU Interface Supports both Single and Dual core AMD C.
© 2008 Advanced Micro De vices, Inc. Features of the SB600 AMD SB600 Register Referen ce Manual Proprietary Page 10 AC Link interface Supports for both audio an d modem codecs Compliant with AC-97 co dec Rev.
© 2008 Advanced Micro De vices, Inc. Block Diagram s AMD SB600 Register Referen ce Manual Proprietary Page 11 1.4 Block Diagrams This section contains two block diag rams for the SB600. Figure 1 shows the SB600 intern al PCI devices with their assigned bus, device, and function numbers.
© 2008 Advanced Micro De vices, Inc. Block Diagram s AMD SB600 Register Referen ce Manual Proprietary Page 12 SATA Controller AC97 Audio IDE LPC PCI Bridge SMBUS /ACPI AB AC97 Modem HD Audio PORT 1 P.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 13 2 Register Descriptions: PCI Devices 2.1 SATA Registers (Device 18, Function 0) Note: Some SATA functions are controlled by, and associ at ed with, certain PCI configuration registe rs in the SMBus/ACPI device.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 14 Register Name Offset A ddress Serial ATA Capability Re gister 0 7.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 15 Status - RW - 16 bits - [PCI_Reg:06h] Field Name Bits Default Description Reserved 2:0 Reserved. Interrupt Status 3 0b Interrupt status bit.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 16 Revision ID/Class Code - R - 32 bits - [PCI_Reg:08h] Field Name Bits Default Description Note: This field is only writeable when PCI_Reg:40h[0] is set.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 17 Base Address 2 - RW - 32 bits - [PCI_ Reg:18h] Field Name Bits Default Description Resource Type Indicator 0 1b T his bit is wired to 1 to indicate that the base address field in this register maps to I/O space.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 18 Min_gnt - R - 8 bits - [PCI_Reg :3Eh ] Field Name Bits Default Description Minimum Grant 7:0 00h This register specif ies the de sired settings for how long of a burst the SATA controller needs .
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 19 MSI Control - RW- 32 bits - [PCI_ Reg : 50h] Field Name Bits Default Description Capability ID 7:0 05h Read-Only. Capability ID.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 20 PCI Power Management Control And St atus - RW- 16 bits - [P CI_Re.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 21 PHY Port0 Control - RW- 32 bits - [PCI _Reg:88h] Field Name Bits Default Description Port0 PHY 23:0 B40014h PHY port0 fine-tune register.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 22 PHY Port1 Control - RW- 32 bits - [PCI _Reg:8Ch] Field Name Bits Default Description TX pre-emphasis driver swing 7:5 000b Port1 Tx driving swing[7:5] is valid for b oth SATA 3G and 1.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 23 PHY Port3 Control - RW- 32 bits - [PCI _Reg:94h] Field Name Bits Default Description Port3 PHY 23:0 B40014h PHY port3 fine-tune register.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 24 2.1.2 BAR0/BAR2/BAR1/BAR3 Registers (SATA I/O Register for IDE mode) BAR0/BAR2 uses 8 bytes of I/O spac e. BAR0 is used for Primary chann el and BAR2 is used for Second ary channel during IDE native mode.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 25 Bus-master IDE Status - RW - 8 bits - [IO_Reg: BAR4 + 0 2/0Ah ] Field Name Bits Default Description Bus Master Active 0 0b Bus Master IDE active.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 26 HBA Capabilities – R - 32bi ts [Mem _reg: ABAR + 00h] Field Name Bits Default De scription Number of Ports(NP) 4:0 00011b 0’s based valu e indicating the maximum number of ports supported by the HBA silicon.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 27 HBA Capabilities – R - 32bi ts [Mem _reg: ABAR + 00h] Field Name Bits Default De scription Supports Port Multiplier (SPM) 17 1b Indicates whether the HBA ca n support a Port Multiplier.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 28 HBA Capabilities – R - 32bi ts [Mem _reg: ABAR + 00h] Field Name Bits Default De scription Supports Native Command Queu ing (SNCQ) 30 1b Indicates whether the HBA su pports Serial ATA native command queuing.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 29 Global HBA Control – RW - 32bits [Mem_reg: ABAR + 0 4h] Field Name Bits Default De scription AHCI Enable (AE) 31 0b When set, indicates that communication to the HBA shall b e via AHCI mechanisms.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 30 Command Completion Coalescing Control(CCC_CTL) - RW – 32 bits [M em_reg: ABAR + 14h] Field Name Bits Default De scription CCC Interrupt (INT) 7:3 1Fh Read Only Specifies the interrupt used by the CCC featur e.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 31 2.1.4.2 Port Registers (On e Set Per Port) The algorithm for the .
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 32 Port-N FIS Base Address Upper –RW – 32 bi ts [Mem_reg : ABAR .
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 33 Port–N Interrupt Status - RW - 32 bits [Mem_reg: ABA R + po rt .
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 34 Port-N Interrupt Enable - RW -32 bits [Mem_reg: ABAR + port offset + 14h ] Field Name Bits Default De scription Cold Presence Detect Enable (CPDE) 31 0b When set, GHC.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 35 Port-N Command and Status - R - 32 bits [Mem _r eg: ABAR + port offs et + 18h] Field Name Bits Default De scription Current Command Slot (CCS) 12:8 00h T his field is valid when P0CMD.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 36 Port-N Command and Status - R - 32 bits [Mem _r eg: ABAR + port offs et + 18h] Field Name Bits Default De scription Device is ATAPI (ATAPI) 24 0b RW When set to ‘1’, the connected device is an ATAPI device.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 37 Port-N Command and Status - R - 32 bits [Mem _r eg: ABAR + port o.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 38 Port-N Task Fike Data – R – 32 bits [Mem_reg : ABAR + port offset + 20h ] Field Name Bits Default De scription Status (STS) 7:0 7Fh Contains the latest copy of the ta sk file status register.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 39 Port-N Serial ATA Status – R – 32 bits [Mem_r eg: ABAR + port.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 40 Port-N Serial ATA Control – RW – 32 bi ts [Mem _reg: ABAR + p.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 41 Port-N Serial ATA Error – RW – 32 bits [Mem_reg: ABAR + por t.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 42 Port-N Serial ATA Error – RW – 32 bits [Mem_reg: ABAR + por t.
© 2008 Advanced Micro De vices, Inc. SATA Registers (Device 18, Function 0 ) AMD SB600 Register Referen ce Manual Proprietary Page 43 Port-N Serial ATA Activ e – RW – 32 bits [Mem _reg: ABAR + port offset + 34 h] Field Name Bits Default De scription Device Status (DS) 31:0 00000000h This field is bit significant.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 44 2.2 OCHI USB 1.1 and EH CI USB 2.0 Controllers Note: Some USB functions are cont rolled by, and associat ed with, certain PCI confi guration registers in the SMBus/ACPI device.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 45 Register Name Offset Address Device / Vendor ID 00h Command 04h.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 46 Device / Vendor ID – R - 32 bits - [PCI _Reg : 00h] Field Nam.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 47 Status – R - 16 bits - [PCI _Reg : 06h] Field Name Bits Defau.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 48 Bar_OHCI – RW - 32 bits - [PCI_ Reg : 10h] Field Name Bits Default Description PM 3 0b Prefetch memor y. A constant va lue of ‘0’ indicates that there is no support for “prefetchable memory”.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 49 Config Timers / MSI Disable (OHCI0 only ) – RW - 16 bits - [P.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 50 Over Current Control 1 (OHCI0 only ) – R - 32 bits - [PCI_Reg : 58h] Field Name Bits Default Description Port5 OverCurrent Control 23:20 Fh The register is to control the OverCurrent pin mapp ing for Port-5.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 51 Target Timeout Control (OHCI0 only ) – RW - 32 bits - [PCI_ R.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 52 Register Name Offset Address HcBulkCurrentED 2Ch HcDoneHead 30h.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 53 HcControl - 32 bits - [MEM_Reg : 04h ] Field Name Bits Default HCD HC Description IE 3 0b RW R IsochronousEnable This bit is used by HCD to enable/disabl e processing of isochronous Eds.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 54 HcControl - 32 bits - [MEM_Reg : 04h ] Field Name Bits Default HCD HC Description IR 8 0b RW R InterruptRouting This bit determines the rout ing of interrupts generate d by events registered in HcInterruptStatu s.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 55 HcCommandStatus - 32 bits - [MEM_Reg : 08h] Field Name Bits Default HCD HC Description CLF 1 0b RW RW ControlListFilled This bit is used to indicate whether there are any TDs on the Control list.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 56 HcInterruptStatus – RW - 32 bits - [MEM_Reg : 0Ch ] Field Nam.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 57 HcInterruptEnable - 32 bits - [MEM_ Re g : 10h] Field Name Bits Default HCD HC Description RD 3 0b RW W 0 - Ignore 1 - Enable interrupt generati on due to Resume Detect.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 58 HcPeriodCurrentED - 32 bits - [MEM_Reg : 1Ch] Field Name Bits D.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 59 HcBulkCurrentED - 32 bit s - [MEM_ Reg : 2Ch] Field Name Bits Default HCD HC Description BCED 31:4 0000000 h RW RW BulkCurrentED This is advanced to the next ED after the HC has served the present one.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 60 HcFmRemaining - 32 bit s - [MEM_ Reg : 38h] Field Name Bits Default HCD HC Description FR 13:0 0000h R RW FrameRemaining This counter is decremented at each bit time.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 61 HcRhDescriptorA - 32 bi ts - [MEM _Reg : 48h] Field Name Bits Default HCD HC Description NDP 7:0 02h R R NumberDownstreamPorts These bits specify the number of downstream ports supported by the Root Hub.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 62 HcRhDescriptorB - 32 bi ts - [MEM _Reg : 4Ch] Field Name Bits Default HCD HC Description DR 15:0 0000h RW R DeviceRemovable Each bit is dedicated to a port of the Root Hub.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 63 HcRhStatus - 32 bits - [M EM_Reg : 50h] Field Name Bits Default.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 64 HcRhPortStatus - 32 bits - [MEM_Reg : 50h+4*(1:N DP)] Field Name Bits Default HCD HC Description PES 1 0b RW RW (Read) PortEnableStatus This bit indicates whether the port is enable d or disabled.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 65 HcRhPortStatus - 32 bits - [MEM_Reg : 50h+4*(1:N DP)] Field Nam.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 66 HcRhPortStatus - 32 bits - [MEM_Reg : 50h+4*(1:N DP)] Field Name Bits Default HCD HC Description CSC 16 0b RW RW ConnectStatusChange This bit is set whenever a connect or disconnect event occurs.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 67 standard OpenHCI descriptor-ba sed accesses.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 68 2.2.2.3 Programming Interface The following modification is nee.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 69 Table 2-4 HceInput Registers HceInput – RW - 32 bits Field Name Bits Default Description InputData 7:0 00h This register holds data that is written to I/O ports 60h and 64h.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 70 HceControl Register Table 2-7 HceControl Register HceControl - 32 bits Field Name Bits Reset Description EmulationEnable 0 0b When set to 1, t he HC is enabled for legac y emulation.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 71 Base Address – BAR_EHCI 10h Subsystem ID / Subsystem Vendor I.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 72 Status – R - 16 bits - [PCI _Reg : 06h] Field Name Bits Default Description Reserved 2:0 Reserv ed Interrupt Status 3 0b This bit reflects the state of the interrupt in the device/function.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 73 Miscellaneous – RW - 32 bits - [PCI_Reg : 0Ch] Field Name Bit.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 74 Interrupt Line - RW - 32 bits - [PCI_ Reg : 3Ch] Field Name Bits Default Description Interrupt Line 7:0 00h The Interrupt Line is a fiel d used to communicate interrupt line routing information.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 75 EHCI Misc Control – RW - 32 bits - [PCI_Reg : 50h ] Field Name Bits Default Description Disable Async QH Cache on OUT xfer 25 0b Set to 1 to disable async QH/QT D cache during OUT xfer.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 76 PME Control – RW - 32 bits - [PCI_R eg : C0h] Field Name Bits Default Description DSI 21 0b Read only.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 77 PME Data / Status – RW - 32 bits - [PCI _Reg : C4h] Field Name Bits Default Description B2_B3# 22 1b Read only.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 78 DBUG_PRT Control – R - 32 bits - [PCI_Reg : E4h ] Field Name .
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 79 USBLEGCTLS TS – RW - 32 bits - [PCI_Reg : EECP + 04h] Field N.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 80 CAPLENGTH – R - 8 bits - [MEM_ Reg : 00h] Description This register is used as an offset to add to register base to find the beginning of the Operational Re gister Space.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 81 HCSPARAMS – R - 32 bits - [MEM_ Reg : 04h] Field Name Bits Default Description Reserved 19:17 These bits are reserve d and should be set to zero.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 82 HCSP-PORTROUTE – R - 60 bits - [M EM_Reg : 0Ch] Description This optional field is valid only if Port Routing Rules field in the HCSPA RAMS register is set to a one.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 83 USBCMD – RW - 32 bits - [EOR_ Reg : EHCI_EOR + 00h ] Field Name Bits Default Description Host Controller Reset (HCRESET) 1 0b T his control bit is used by software to reset the host controller.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 84 USBCMD – RW - 32 bits - [EOR_ Reg : EHCI_EOR + 00h ] Field Na.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 85 USBSTS - RW - 32 bits - [E OR_Reg : EHCI_EO R + 04h] Field Name Bits Default Description Port Change Detect 2 0b Port Change Detect.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 86 USBINTR –RW - 32 bits - [E OR_Reg : EHCI_EOR + 08h] Field Nam.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 87 ASYNCLISTADDR –RW - 32 bits - [EOR_ Reg : EHCI_EOR + 18h] Field Name Bits Default Description Reserved 4:0 These bits are reserved an d their value h as no effect on operation.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 88 PORTSC (1-N_PORTS) – RW - 32 bits - [EOR_Reg : EHCI_E OR + (44h~68h )] Field Name Bits Default Description Force Port Resume 6 0b 1 = Resume detected/driven on port.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 89 PORTSC (1-N_PORTS) – RW - 32 bits - [EOR_Reg : EHCI_E OR + (44h~68h )] Field Name Bits Default Description Port Reset 8 0b 1 = Port is in Reset.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 90 PORTSC (1-N_PORTS) – RW - 32 bits - [EOR_Reg : EHCI_E OR + (4.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 91 USB PHY Status 0 – RW - 32 bits - [EOR_Reg : EHCI_EOR + 88h] Field Name Bits Default Description PORT0_PHYStatus 7:0 00h Read only.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 92 UTMI Control – RW - 32 bits - [EO R_ Reg: EHCI_EOR + 94h] Field Name Bits Default Description VBusy 17 0b RO – T o block software write to [16:8] when port r outer is updating the field.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 93 Control register (EHCI_PCI_CF G xE4[28:16], default = 0E0h) , regardless of the value in register (MEM_Reg: 00h).
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 94 Control / Status – RW - 32 bits - [DBUG_Reg : DBase + 00h] Field Name Bits Default Description Enabled 28 0b This bit is a one if t he debug port is enabled for operation.
© 2008 Advanced Micro De vices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Referen ce Manual Proprietary Page 95 Data Buffer – RW - 64 bits - [DBug_Reg : DBase + 08h/0Ch ] Fi.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 96 2.3 SMBus Module and ACPI Block (Device 20, Function 0) Some registers in the SMBus/ACPI PC I configuration space (PCI_reg, see section 2.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 97 2.3.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 98 Register Name Configuration Offset IDE_GPIO_In A4h GP.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 99 Command- RW - 16 bits - [PCI_Reg: 04h] Field Name Bits Default Description Parity Error Response 6 0b This bit controls the device’s response to parit y errors.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 100 Revision ID/Class Code - R - 32 bits - [PCI_Reg: 08h] Field Name Bits Default Description RevisionID 7:0 11h / 12h / 13h This field reflects the ASIC revision.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 101 Base Address 2- R - 3 2 bits - [P CI_Reg: 18h] Field.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 102 Interrupt Line - R - 8 bits - [PCI_Reg : 3Ch] Field Name Bits Default Description Interrupt Line 7:0 00h This module does not generate interrupt.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 103 DmaLimit- RW - 8 bits - [ P CI_Reg: 42h] Field Name .
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 104 GPIO_52_to_49_Cn trl - RW – 1 6 bits - [PCI_Reg: 5.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 105 GPIO_64_to_61_Cn trl - RW – 1 6 bits - [PCI_Reg: 5.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 106 SmartPowerControl1B - RW – 8 bits - [PCI_Reg: 5Dh].
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 107 MiscEnable- RW - 8 bits - [PCI_Reg : 6 2h] Field Name Bits Default Description USB_Fast_SMI_Disable 5 0b For K8 s ystem, legacy USB can request SMI# to be sent out early before IO completion.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 108 Features Enable- RW - 32 bits - [P CI_Reg: 64h] Field Name Bits Default Description Smi_Gevent_En 12 0b Enable all the events with the capability of doing both SMI# and SCI to SMI# assertion.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 109 UsbEnable - RW - 8 bits - [PCI_ Reg: 68h] Field Name.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 110 TestMode- RW - 16 bits - [PCI_ Reg: 6C] Field Name Bits Default Description DMA_Timing 0 0b To be used by BIOS only; when set, legac y DMA will insert 1 extra idle clock in bet ween requests.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 111 GPIO_69_68_66_65_Cn trl - RW – 16 bits - [PCI_Re g.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 112 SmartPowerControl2A - RW – 8 bits - [PCI_Reg: 98h].
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 113 SmartPowerControl2C - RW – 8 bits - [PCI_Reg: 9Ah] Field Name Bits Default Description SmartVoltEnable2 7 0b Enab le bit for the Sm artPower2 function.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 114 GPIO_12_to_4_Cntrl – RW – 32 bits - [PCI_ Reg: A.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 115 SATA_Cntrl - RW – 16 bits - [PCI_Reg: ACh] Field Name Bits Default Description ExtendIntrToWakeTime 18:16 000b This is used in K8 system to extend the interrupt break event status.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 116 UsbIntMap - RW - 16 bits - [PCI_ Reg: BEh] Field Nam.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 117 IoDrvSth - RW - 32 bits - [PCI_ Reg: C0h] Field Name.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 118 I2CShadow1- RW - 8 bits - [PCI_ Reg: D4h] Field Name.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 119 MwaitSts- R - 8 bits - [P CI_Reg : F7h] Field Name Bits Default Description Mwait_cpu1_sts 1 0b Set to 1 b y MWAIT wi th addr[19:18] = Mwai t_physical _ID[3:2] and addr[17:16] = Mwait_logical_ID[1:0].
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 120 2.3.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 121 AudioGpioControl – RW - 32 bits - [Exten d_Reg: 04h] Field Name Bits Default Description AudioGpioOut0OeB 0 1b When ACZ_SDIN0 is configured as GPIO, this bit represents the output enable.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 122 AudioGpioControl – RW - 32 bits - [Exten d_Reg: 04.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 123 2.3.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 124 SMBusSlaveStatus - RW - 8 bits - [SM BUS:01h] Field .
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 125 SMBusSlaveControl - RW - 8 bits - [S MBUS:08h] Field.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 126 2.3.3 Legacy ISA and ACPI Controller 2.3.3.1 Legacy Block Regis ters There are two sets of registers in the ACPI/SMBus module.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 127 Register Name Offset A d dress Dma2_Ch6Cnt CAh Dma2_.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 128 Dma_Status- RW – 8 bits - [IO_Reg: 0 8h] Field Nam.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 129 IntrCntrl1Reg2- RW – 8 b its - [IO_Reg: 21h] Field.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 130 Tmr1CntrlWord - RW – 8 bits - [IO_Re g: 43h] Field.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 131 RtcDataPort - RW – 8 bits - [IO_Reg: 71h ] Field N.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 132 Dma_Page_Reserv ed4- RW – 8 bits - [IO_Reg: 8 8h] .
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 133 IntrCntrl2Reg1- RW – 8 b its - [IO_Reg: A0h] Field.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 134 Dma_Ch7Cnt - RW – 8 bits - [IO_ Reg: CEh] Field Na.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 135 NCP_Error - RW – 8 bits - [IO_Reg: F0h] Field Name Bits Default Description NCP_Error register: In addition to the WarmBoot function, writing to this port will assert IGNNE# if FERR# is true.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 136 Pci_Intr_Data - RW – 8 bits - [IO_Reg: C01h ] Fiel.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 137 GpmPort - RW – 8 bits - [ I O_Re g: C52h] Field Na.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 138 IdRegister - R – 8 bits - [IO_Reg: 0 0h] Field Nam.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 139 2.3.3.1.3 System Reset Registe r (IO CF9) Note: Refer to PM IO reg x85 for a detailed description. This re gister has been desig ned to be dual-port accessible.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 140 Register Name Offset Address AcpiPmaCntBlkLo 2Ch Acp.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 141 Register Name Offset Address SOS3ToS5Enable2 78h SOS.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 142 MiscControl - RW – 8 bits - [PM_R eg: 00h] Field Name Bits Default Description Reserved 3 0b SmiReq 4 0b Software initiated SMI#.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 143 SmiWakeUpEv entStatus2 - RW – 8 bits - [PM_Re g : 06h] Field Name Bits Default Description SmiWakeUpEventStatus2 register.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 144 PmTmr1CurValue - R – 8 bits - [PM_Reg: 0Ch] Field .
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 145 AcpiEn - RW – 8 bits - [PM_Reg: 10 h] Field Name Bits Default Description EOSEnale 0 0b Set 1 by software and clear by hardware.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 146 Programlo0RangeLo - RW – 8 bits - [PM_Reg : 14 h] Field Name Bits Default Description ProgramIo0Mask 3:0 0h These four bits are us ed to m ask the least 4 bits of the 16 bit I/O.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 147 ProgramIo2RangeLo - RW – 8 bits - [PM_Reg: 18h] Field Name Bits Default Description ProgramIo2RangeLo register.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 148 IOMonitorStatus - RW – 8 bits - [PM_Reg: 1Dh] Fiel.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 149 AcpiPm1CntBlkHi - RW – 8 bits - [PM _Reg: 23h] Field Name Bits Default Description AcpiPm1CntBlkHi register.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 150 AcpiSmiCmdLo - RW – 8 bits - [PM_Reg: 2Ah] Field N.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 151 GPMConfig0 – RW – 8 bits - [PM_Reg: 32h] Field N.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 152 GPMConfig2- RW – 8 bits - [PM_Reg: 34h] Field Name.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 153 GEvtLevelConfig - RW – 8 bits - [PM_ Reg : 36h] Fi.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 154 GPMLevelConfig1 - RW – 8 bits - [P M_Reg: 38h] Fie.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 155 OthersConfig- RW – 8 bits - [PM_Reg : 3Ch] Field N.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 156 AD23_Pull_UpB - RW – 8 bits - [PM_Reg: 41h ] Field Name Bits Default Description AD23_Pull_UpB 0 0b This bit controls integrated pull-up for AD[23].
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 157 TPRESET2 - RW – 8 bits - [PM_Reg: 52h] Field Name .
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 158 Reserved – 8 bits - [PM_Reg: 57h ] Field Name Bits.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 159 SmiSciSts2 - RW – 8 bits - [PM_Reg: 5Ch] Field Nam.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 160 MwaitEnable - RW – 8 bits - [PM_Reg : 5Eh] Field Name Bits Default Description MwaitEnable register This register is used only in the P4 system.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 161 SwitchVoltageTime - RW – 8 bits - [PM_Reg: 63 h] F.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 162 MiscEnable67 – RW – 8 bits – [PM_Re g:67 h] Field Name Bits Default Description TempPolarity 6:5 00b T emperature polarity control for THRMT RIP and TALERT respectively.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 163 WatchDogTimerBase2 – RW – 8 bits – [PM_Reg:6Eh.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 164 C4Control – RW – 8 bits – [PM_Reg:72h] Field N.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 165 S0S3ToS5Enable0 – RW – 8 bits – [PM_Reg:76h] F.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 166 NoStatusControl0 – RW – 8 bits – [P M_Reg:7Ah].
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 167 SMAF1 – RW – 8 bits – [PM_Reg:81h] Field Name .
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 168 ThermThrotCntl – RW – 8 bits – [PM_Reg :86h] F.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 169 LdtAgpTimeCntl – RW – 8 bits – [PM_Reg:8Ah] Field Name Bits Default Description LdtAgpTimeCntl register for ACPI C state in the K8 s ystem.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 170 FakeAsrEn– RW – 8 bits – [PM_Reg:8Fh] Field Name Bits Default Description MaskNbBmStsSet 5 0b When set, BmStsSet message from NB will not cause wake up from C state.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 171 K8C1ePort - RW - 16 bits - [PM_Reg: 99:98 h] Field Name Bits Default Description K8C1ePort 15:0 0000h This register defines the 16 bit IO address fo r the K8 C1e support.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 172 AutoArbDisWaitTime - R W - 8 bits - [PM_Reg: 9Fh] Fi.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 173 ProgramIo5RangeHi - RW – 8 bits - [PM_Reg: A3 h] F.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 174 PIO7654Enable - RW – 8 bits - [PM_Reg: A8h] Field Name Bits Default Description ProgramIo5Enable 1 0b Enables IO monitoring for ProgramIO5 (defined by index A2 , A3).
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 175 C3Count - R – 8 bits - [PM_Reg: B4h] Field Name Bits Default Description C3Count 7:0 00h T he value shows the amount of time the CPU spends in C 3.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 176 2.3.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 177 Pm1Enable - RW - 16 bits - [AcpiPm E vtBlk:02h] Field Name Bits Default Description Reserved 13:11 000b PciExpWakeDis 14 1b T his bit disables t he inputs to the PciExpWakeStatus from waking the system.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 178 CLKVALUE - RW - 3 2 bits - [CpuControl:00h ] Field N.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 179 EVENT_STATUS - RW - 32 bits - [AcpiGpe0Blk:00h] Fiel.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 180 SmiCmdStatus - RW - 8 bits – [Sm i Cm dBlk: 01h] Field Name Bits Default Description This register is located at the base a ddress defined by AcpiSmiCmd + offset 1.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 181 2.3.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 182 2.3.5 ASF SM bus Host Interface Registers The ASF SM bus host register block is resid ent in the Io space whose base defined at offset 58h/59h of config space.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 183 HostControl – RW - 8 bits - [ASF_IO: 02h] Field Name Bits Default Description PECEnable 7 0b 0: PEC disable 1: PEC enable, enable CRC checki ng when ASF HC presents as SM master and SM slave.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 184 StatusMask0– RW - 8 bits - [ASF_IO: 0Bh] Field Nam.
© 2008 Advanced Micro De vices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Referen ce Manual Proprietary Page 185 SlaveMisc- RW - 8 bits - [ASF_I O: 0 Dh] Field Name .
© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 186 2.4 IDE Controller (Device 20, Function 1) 2.
© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 187 Device ID - R - 16 bits - [PCI_Reg:02h ] Field Name Bits Default .
© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 188 Status - RW - 16 bits - [PCI_Reg:06h] Field Name Bits Default Description DEVSEL- Timing 10:9 01b DEVSEL- timing – Read only bits indicating DEVSEL- timing when performing a positive decode.
© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 189 Master Latency Timer - RW - 8 bits - [PCI_Reg:0Dh] Field Name Bits Default Description Reserved 2:0 0h They are not used and wired to 0.
© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 190 Base Address 2 - RW - 32 bits - [PCI_ Reg:18h] Field Name Bits Default Description Reserved 31:16 0000h Reserved. Al ways read as 0’s.
© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 191 Interrupt Pin - R - 8 bits - [PCI_Reg:3 Dh] Field Name Bits Default Description Interrupt Pin 7:0 01h Hard-wired to 01h.
© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 192 IDE Legacy DMA (Multi-words DMA) Timi ng Modes - RW - 32 bits - [.
© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 193 IDE Ultra DMA Status - R W- 8 bits - [PCI_Reg:55h] Field Name Bits Default Description IDE Ultra DMA Status Register: This register s pecifies the Ultra DMA status for primary channel.
© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 194 IDE Internal Control - RW- 16 bits - [PCI_R eg:62h] Field Name Bi.
© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 195 IDE Dynamic Clocking - RW- 2 0 bits - [PCI_Reg:6Ch ] Field Name Bits Default Description IDE Power Down Counter 19:0 FFFFFh The IDE po wer down counter can be programmed to shut down the IDE clock.
© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 196 Bus-master IDE Command - RW - 8 bits - [IDE:00h] Field Name Bits Default Description Bus Master IDE Start/Stop 0 0b Bus Master IDE Start (1)/Stop (0).
© 2008 Advanced Micro De vices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Referen ce Manual Proprietary Page 197 Address (hex) Name and Function Compatibility Mode Native Mode (O.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 198 2.5 AC ’97 Controller Functional Descriptions 2.5.1 Audio Registers (Device 20, Function 5) The PCI based registers for Audio are de fined accord ing to the PCI 2.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 199 CMD- RW - 16 bits - [PCI_ Reg : 04h] Field Name Bits Default Description IO Space 0 0b I/O Access Enable. Memory Space 1 0b Memor y Access Enable.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 200 Revision ID/Class Code - R - 32 bits - [PCI_Reg: 08h] Field Name Bits Default Description Revision ID 7:0 00h Revision ID.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 201 Base Address Reg 1- RW - 32 bits – [P CI_Reg: 14h] Field Name Bits Default Description Reserved 7:4 0h Always 0; meaning t hat the IO mapped registers occupy 256 bytes.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 202 MSI Capability Register Set IDs- R – 16 bits – [PCI_Reg: 40h] Field Name Bits Default Description Capability ID 7:0 05h Rea d only.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 203 UnMask Latency Timer Expiration W - 32 bits - [PCI_Reg: 5 0.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 204 Interrupt - RW - 32 bits - [MEM_Reg : 00h] Field Name Bits Default Description in DMA Overflow 0 0b Input Channel overflow on the next AC'97 clock - out of FIFO space.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 205 Interrupt Enable- RW - 32 bits - [ME M _Re g: 04h] Field Na.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 206 Audio Command- RW - 32 bits - [MEM_Reg: 08 h] Field Name Bi.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 207 Slot Request- R - 32 bits - [MEM_Reg: 14h] Field Name Bits .
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 208 Input DMA DT Current- R - 32 bits - [M EM_Reg: 2Ch] Field Name Bits Default Description in DMA DT current 31:0 0000_ 0 000h Pointer to the currently accessing memor y address for the input DMA.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 209 Output DMA DT Size and State - R - 32 bits - [MEM_ Reg : 48h] Field Name Bits Default Description Out DMA DT size 15:0 0000h Data size of DT for Output DMA.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 210 SPDIF Channel DT Current- R - 32 bit s - [MEM_ Reg: 5Ch] Field Name Bits Default Description SPDIF DT current 31:0 0000_0 000h SPDIF Channel currently accessed memor y address.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 211 Output DMA Fifo info- R - 32 bits - [MEM_Reg: 8C h] Field Name Bits Default Description Out FIFO Used 6:0 00h Number of filled FIFO entries of output DMA.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 212 Audio Phy Semaphore Reg- RW - 8 bi ts - [MEM _Reg: A8h] Field Name Bits Default Description Audio Phy semaphore 0 0b PHY is ready for Audio to acc ess: 0 = PHY is not ready for Audio to access.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 213 2.5.2 Modem Registers (Device 20, Function 6) The PCI based registers for Modem are defined ac cording to the PCI 2.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 214 CMD- RW - 16 bits - [PCI_ Reg : 04h] Field Name Bits Default Description IO Space 0 0b I/O Access Enable. Memory Space 1 0b Memor y Access Enable.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 215 Cache Line Size - RW - 8 bits - [PCI_ Reg : 0Ch] Field Name Bits Default Description Cache Line Size 7:0 00h Cach e Lien Size.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 216 Subsystem ID & Subsy stem Vendor ID - W/R - 32 bits - [PCI_Reg: 2Ch] Field Name Bits Default Description Subsystem Vendor ID 15:0 0000h Subsystem Vendor ID.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 217 MSI Message Control Register- RW - 16 bits - [PCI_Reg : 42h.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 218 2.5.2.2 Modem M emory M apped Registers All the AC’97 Controller modem registers are mapped to memory.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 219 Interrupt - RW - 32 bits - [MEM_Reg : 00h] Field Name Bits .
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 220 Modem Command - RW - 32 bits - [ M EM_Re g: 08h] Field Name.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 221 Modem Command - RW - 32 bits - [ M EM_Re g: 08h] Field Name Bits Default Description Modem Command Register: Controls the operatio n of Audio Controller.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 222 Counter - R - 32 bits - [M EM_Reg : 18h] Field Name Bits Default Description Slot Counter 3:0 0h The current sl ot number (0-12) which the AC97 controller handling.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 223 Output DMA 1/2/3 Threshold – RW - 3 2 bits - [MEM_Reg: 34.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 224 Output DMA2 DT Start– R - 32 bits - [MEM_Reg: 50h] Field Name Bits Default Description out DMA2 DT start 31:0 0000_0000h Pointer to t he start of data associated with current DT for the Output DMA2.
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 225 Output DMA 1/2/3 FIFO Info– R - 32 bits - [MEM_ Reg: 70h] Field Name Bits Default Description out DMA3 Used 14:10 00h Number of filled FIFO entries of Output DMA3 (FIFO size 6).
© 2008 Advanced Micro De vices, Inc. AC ’97 Controller Functional De scriptions AMD SB600 Register Referen ce Manual Proprietary Page 226 Modem Fifo Flush– W - 32 bits - [ME M_Re g: 88h] Field Name Bits Default Description Output DMA3 Fifo Flush 2 0b Writing to this bit flushes modem output DMA3 fifo, i.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 227 2.6 HD Audio Controllers Registers Note: Some HD Audio functions are controlled by, and asso ciated with, certain PCI c onfiguration registers in the SMBus/ACPI device.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 228 PCI Command – RW – 16 bits – [PCI_Reg : 04h ] Field Name Bits Default Description Reserved 0 0b Reserved. Memory Space Enable 1 0b Enables the H D Audio controller to respond to PCI memory space access.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 229 Latency Timer – R – 8 bits – [PCI_Reg : 0Dh] Field Name Bits Default Description Latency Timer 7:0 00h Hardwired to “0”.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 230 Interrupt Line – RW – 8 bits – [PCI_Re g: 3Ch] Field Name Bits Default Description Interrupt Line 7:0 00h This register is used to communic ate to software the interrupt line that the interrupt pin is connected to.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 231 Power Management Capabilities – R – 16 bits – [PCI_Reg: 52h] Field Name Bits Default Description Version 2:0 010 b Hardwired to 010b.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 232 MSI Message Lower Address – RW - 32 bits – [P CI_Reg: 64h] Field Name Bits Default Description MSI Message Lower Address 31:2 00000000 h Lower Address used for MSI Message.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 233 Register Name Address Offset Immediate Command Input Interface 64h Immed.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 234 Register Name Address Offset Control 140h Status 143h Link Position in C.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 235 Output Payload Capability – R – 16 bits - [Mem _Reg: Base + 04h] Field Name Bits Default Description Output Payload Capabilit y 15:0 003Ch Hardwired to 3Ch.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 236 Wake Enable – RW – 16 bits - [Mem_ Reg : Base + 0Ch] Field Name Bits Default Description Wake Enable 3:0 0h This field controls which SDIN signals may generate a wake event in response to a codec State Ch ange event.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 237 Input Stream Payload Capability – R – 16 bits - [Mem_Reg: Base + 1Ah.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 238 Interrupt Status – RW – 32 bits - [Mem_Reg : Base + 24h] Field Name Bits Default Description Stream Interrupt Status 7:0 00h A “1” indicate s that an interrupt condition occ urred on the corresponding stream.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 239 CORB Upper Base Addre ss – RW – 32 bits – [Mem_Reg : Base + 44h] Field Name Bits Default Description CORB Upper Base Address 31:0 00000000 h Upper 32 bits address of the CORB.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 240 CORB Status – RW – 8 bits – [Mem_ Reg: Base + 4Dh ] Field Name Bit.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 241 RIRB Response Interrupt Count – RW – 16 bits – [Mem_Reg: Base + 5 .
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 242 Immediate Command Output Interface – RW – 32 bits – [Mem _ Reg: Ba.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 243 DMA Position Lo wer Base Address – RW – 32 bits – [Mem_Reg: Base +.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 244 Stream Descriptor Control – RW – 24 bits Input Stream 0 - [Mem_Reg: .
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 245 Stream Descriptor Status – RW – 8 bits Input Stream 0 - [Mem_Reg: Ba.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 246 Stream Descriptor Cyclic Buffer Length – RW – 3 2 bits Input Stream .
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 247 Stream Descriptor FIFO Size – R – 16 bits Input Stream 0 - [Mem_Reg:.
© 2008 Advanced Micro De vices, Inc. HD Audio Controllers Regi sters AMD SB600 Register Referen ce Manual Proprietary Page 248 Stream Descriptor BDL Pointer Lo wer Base Address – RW – 32 bits Inp.
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 249 3 Register Descriptions: PCI Bridges 3.1 LPC ISA Bridge (Device 20, Function 3) Note: Some LPC functions are controlled by, and asso ciat ed with, certain PCI configuration registers in the SMBus/ACPI device.
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 250 Register Name Offset Address Rom Protect 1 54h Rom Protect 2 58h .
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 251 CMD- RW - 16 bits - [PCI_ Reg : 04h] Field Name Bits Default Description SERR# Enable 8 0b SERR# enable - If set to 1, the LPC bridge asserts SERR# when it detects as address parity error.
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 252 Latency Timer - R - 8 bit s - [PCI_Reg: 0Dh ] Field Name Bits Default Description Latency Timer 7:0 00h Latency Timer.
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 253 IO Port Decode Enable Register 1- RW - 8 bits - [PCI_Re g: 44 h] .
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 254 IO/Mem Port Decode Enable Register 5- RW - 8 bits - [PCI_Reg : 48.
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 255 Rom Protect 0 - RW - 32 bits - [P CI_Reg: 50h] Field Name Bits Default Description Write Protect 0 0b W hen this bit is set, the memory range defined by this register is write-protected.
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 256 LPC ROM Address Range 1 (Star t Address ) - RW - 16 bits - [PCI_R.
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 257 Firmware Hub Select – RW* - 32 bits - [PCI_Reg: 70h] Field Name Bits Default Description FWH_D8_IDSEL 15:12 4h IDSEL for two 512 KB FWH memory ranges.
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 258 Miscellaneous Control Bits- RW - 8 bi ts - [PCI_Reg: 78h ] Field Name Bits Default Description Msi On 1 0b W hen this bit is set to 1, it turns on LPC MSI capability.
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 259 MSI Capability Register- R - 32 bits - [PCI_Reg: 80h] Field Name Bits Default Description CAP Fixed 17 1b CAP F ixed.
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 260 TMKBC_Remap Regis ter- RW - 16 bits - [P CI_R eg: 8Ch] Field Name Bits Default Description TMKBC_Remap 15:8 00h This register defines the remap address [15: 8] on the LPC bus.
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 261 Register Name Offset Address SPI_FakeID 1Ch SPI_Cntrl0 Register- .
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 262 SPI_RestrictedCmd2 Register- RW - 32 bits - [Mem_Reg 08h] Field N.
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 263 SPI_CmdValue1 Register- RW - 32 bits - [Mem_Re g 14h] Field Name Bits Default Description WREN 7:0 06h T his is used to compare against the opcode sent out by the MAC.
© 2008 Advanced Micro De vices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Referen ce Manual Proprietary Page 264 3.1.4 Features of the LPC Block Bus Speed: LPC bus—33MHz Suppor.
© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 265 3.2 Host PCI Bridge Registers (Device 20, Function 4) Note: Some PCI functions are controlle d by, and associat ed with, certain PCI configuration registers in the SMBus/ACPI device.
© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 266 Register Name Offset A ddress Additional Priorit y 49.
© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 267 Status- RW - 16 bits - [PCI_Reg : 06h] Field Name Bits Default Description Capabilities List 4 0b Read only.
© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 268 Primary Bus Number- RW - 8 bits - [PCI_Reg: 18 h] Field Name Bits Default Description Primary Bus Number 7:0 00h Bus number of the PCI bus to which the primary interface is connected.
© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 269 Secondary Status- RW - 1 6 bits - [PCI_Reg: 1Eh] Field Name Bits Default Description Received Secondar y Target Abort 12 0b Received Target Abort on the secondar y bus, write clears it.
© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 270 IO Limit Upper 16 bits- RW - 16 bits - [PCI_ Reg: 32h.
© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 271 Bridge Control- RW - 16 b its - [PCI_Reg: 3Eh] Field .
© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 272 CLKCTRL- RW - 8 bits - [ P CI_Reg: 42h] Field Name Bits Default Description PCICLKStopEnable 0 0b 33MHz PCICLKs request bit; when ‘1,’ 33 MHz PCI Clocks are requested to stop.
© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 273 PCICLK Enable Bits- RW - 8 bits - [PC I _Reg: 4Ah] Field Name Bits Default Description PCICLK4Enable 0 1b 33MHz PCICLK4 enable.
© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 274 Dual Address Cycle Enable and PCIB_CLK_Stop Ov erride.
© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 275 Prefetch Size Control - 32 bits - [PCI_ Reg: 60h] Fie.
© 2008 Advanced Micro De vices, Inc. Host PCI Bridge Registers (Device 20, Functio n 4) AMD SB600 Register Referen ce Manual Proprietary Page 276 Misc Control Register - 32 bits - [P CI_Reg: 64h] Fie.
© 2008 Advanced Micro De vices, Inc. GPIO/GPOC AMD SB600 Register Referen ce Manual Proprietary Page 277 4 Register Descriptions: General Purpose Functions/Interrupt Controllers/Support Function Pins 4.1 GPIO/GPOC Note: Some GPIO functions are controlled by, and a ssoci ated with, certain PCI configuration registers in the SMBus/ACPI device.
© 2008 Advanced Micro De vices, Inc. GPIO/GPOC AMD SB600 Register Referen ce Manual Proprietary Page 278 Pin Name (Note 1) Multi-function Selection Output Enable (On SMBus Controller) Bus 00h/ Dev14h.
© 2008 Advanced Micro De vices, Inc. GPIO/GPOC AMD SB600 Register Referen ce Manual Proprietary Page 279 Pin Name (Note 1) Multi-function Selection Output Enable (On SMBus Controller) Bus 00h/ Dev14h.
© 2008 Advanced Micro De vices, Inc. GPIO/GPOC AMD SB600 Register Referen ce Manual Proprietary Page 280 Pin Name (Note 1) Multi-function Selection Output Enable (On SMBus Controller) Bus 00h/ Dev14h.
© 2008 Advanced Micro De vices, Inc. GPIO/GPOC AMD SB600 Register Referen ce Manual Proprietary Page 281 Pin Name (Note 1) Multi-function Selection Output Enable (On SMBus Controller) Bus 00h/ Dev14h.
© 2008 Advanced Micro De vices, Inc. GPIO/GPOC AMD SB600 Register Referen ce Manual Proprietary Page 282 Pin Name (Note 1) Multi-function Selection Output Enable (On SMBus Controller) Bus 00h/ Dev14h.
© 2008 Advanced Micro De vices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Referen ce Manual Proprietary Page 283 4.2 GEVENT/GPE/GPM/ExtEvent 4.2.1 GEVENT as GPIO GEVENT[1:0] are inputs only. Their status ca n be read from PM I/O Reg 92h Bit[1:0].
© 2008 Advanced Micro De vices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Referen ce Manual Proprietary Page 284 Pin Name (*Note 1) Multi-Function Selection Configure Bit 00 – SCI or SMI# 01 .
© 2008 Advanced Micro De vices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Referen ce Manual Proprietary Page 285 Pin Name (*Note 1) Multi-Function Selection Configure Bit 00 – SCI or SMI# 01 .
© 2008 Advanced Micro De vices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Referen ce Manual Proprietary Page 286 Pin Name (*Note 1) Multi-Function Selection Configure Bit 00 – SCI or SMI# 01 .
© 2008 Advanced Micro De vices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Referen ce Manual Proprietary Page 287 4.2.3.2 GPM pins as Outpu t For GPM[7:0], follow this sequence - 1. Set index register 0C50h to 13h (Misc. Control ). 2. Set CM Data register 0C51h Bits [7:6] = 01b to set Input/Out control.
© 2008 Advanced Micro De vices, Inc. THRMTRIP/TALERT AMD SB600 Register Referen ce Manual Proprietary Page 288 4.3 THRMTRIP/TALERT 4.3.1 Thermal Trip – THRMTRIP The thermal trip function is multiplexed on the G EVENT2 pin. The THRMTRIP status cannot be used to generate SCI or SMI#.
© 2008 Advanced Micro De vices, Inc. Real Time Clock (RTC) AMD SB600 Register Referen ce Manual Proprietary Page 289 4.4 Real Time Clock (RTC) Note: Some RTC functions are cont rolled by, and associat ed with, certain P CI confi guration registers in the SMBus/ACPI device.
© 2008 Advanced Micro De vices, Inc. Real Time Clock (RTC) AMD SB600 Register Referen ce Manual Proprietary Page 290 . Figure 5 Register Bank Definition and Memory Address Ma pping The analog portion consists of two majo r parts: one is a 256-byte CMOS RAM and the other a 44-bit ripple counter.
© 2008 Advanced Micro De vices, Inc. Real Time Clock (RTC) AMD SB600 Register Referen ce Manual Proprietary Page 291 Register Name Offset A ddress Register A 0Ah Register B 0Bh Register C 0Ch Registe.
© 2008 Advanced Micro De vices, Inc. Real Time Clock (RTC) AMD SB600 Register Referen ce Manual Proprietary Page 292 Hours - RW – 8 bits - [RTC_Reg: 04h ] Field Name Bits Default Description Hours register Hours Alarm- RW – 8 bits - [RT C_ Reg : 05h] Field Name Bits Default Description Hours Alarm 7:0 00h Binary-C ode-Decimal format.
© 2008 Advanced Micro De vices, Inc. Real Time Clock (RTC) AMD SB600 Register Referen ce Manual Proprietary Page 293 Register A - RW – 8 bits - [RTC_Reg: 0Ah ] Field Name Bits Default Description R.
© 2008 Advanced Micro De vices, Inc. Real Time Clock (RTC) AMD SB600 Register Referen ce Manual Proprietary Page 294 Register C - R – 8 bits - [RTC_Reg: 0Ch] Field Name Bits Default Description Update Ended Interrupt Flag(UF ) 4 0b T his bit is set to one after each update cycle.
© 2008 Advanced Micro De vices, Inc. Real Time Clock (RTC) AMD SB600 Register Referen ce Manual Proprietary Page 295 Extended RAM Address Port - RW – 8 bits - [RT C_Reg: 50h] Field Name Bits Default Description ExtendedRAMAddr 6:0 00h Becaus e only 7 address bits are used in por t x70, only lower 128 bytes are accessibl e through port x71.
© 2008 Advanced Micro De vices, Inc. IOXAPIC Registers AMD SB600 Register Referen ce Manual Proprietary Page 296 4.5 IOXAPIC Registers Note: Some IOXAPIC functions are controlled by, and associated with, certain PCI c onfiguration registers in the SMBus/ACPI device.
© 2008 Advanced Micro De vices, Inc. IOXAPIC Registers AMD SB600 Register Referen ce Manual Proprietary Page 297 4.5.2 Indirect Access Registers Software needs to first select the regist er to access using the IO Register Sele ct Register, and then read or write using the IO Window Regi ster.
© 2008 Advanced Micro De vices, Inc. IOXAPIC Registers AMD SB600 Register Referen ce Manual Proprietary Page 298 Redirection Table Entry [0–23 ] [Indirect Address Offset = 11/1 0H–3F/3EH] RW Fiel.
© 2008 Advanced Micro De vices, Inc. Appendix A: AC97 Audio FAQs AMD SB600 Register Referen ce Manual Proprietary Page 299 Appendix A: AC97 Audio FAQs Q: What is the descriptor table (DT) data stru cture in memory? A: Data Pointer (first dword); Size, Status (2nd dwor d) ; Next descriptor pointer (3rd dword).
© 2008 Advanced Micro De vices, Inc. Appendix B: Revision History AMD SB600 Register Referen ce Manual Proprietary Page 300 Appendix B: Revision History Date Rev.
Een belangrijk punt na aankoop van elk apparaat AMD SB600 (of zelfs voordat je het koopt) is om de handleiding te lezen. Dit moeten wij doen vanwege een paar simpele redenen:
Als u nog geen AMD SB600 heb gekocht dan nu is een goed moment om kennis te maken met de basisgegevens van het product. Eerst kijk dan naar de eerste pagina\'s van de handleiding, die je hierboven vindt. Je moet daar de belangrijkste technische gegevens AMD SB600 vinden. Op dit manier kan je controleren of het apparaat aan jouw behoeften voldoet. Op de volgende pagina's van de handleiding AMD SB600 leer je over alle kenmerken van het product en krijg je informatie over de werking. De informatie die je over AMD SB600 krijgt, zal je zeker helpen om een besluit over de aankoop te nemen.
In een situatie waarin je al een beziter van AMD SB600 bent, maar toch heb je de instructies niet gelezen, moet je het doen voor de hierboven beschreven redenen. Je zult dan weten of je goed de alle beschikbare functies heb gebruikt, en of je fouten heb gemaakt die het leven van de AMD SB600 kunnen verkorten.
Maar de belangrijkste taak van de handleiding is om de gebruiker bij het oplossen van problemen te helpen met AMD SB600 . Bijna altijd, zal je daar het vinden Troubleshooting met de meest voorkomende storingen en defecten #MANUAl# samen met de instructies over hun opplosinge. Zelfs als je zelf niet kan om het probleem op te lossen, zal de instructie je de weg wijzen naar verdere andere procedure, bijv. door contact met de klantenservice of het dichtstbijzijnde servicecentrum.
