Gebruiksaanwijzing /service van het product AD9883A van de fabrikant Analog Devices
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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use.
REV. 0 –2– AD9883A–SPECIFICA TIONS Test AD9883AKST-110 AD9883AKST-140 Parameter Temp Level Min Typ Max Min Typ Max Unit RESOLUTION 8 8 Bits DC ACCURACY Differential Nonlinearity 25 ° CI ± 0.5 +1.25/–1.0 ± 0.5 +1.35/–1.0 LSB Full VI +1.35/–1.
REV. 0 –3– AD9883A Test AD9883AKST-110 AD9883AKST-140 Parameter Temp Level Min Typ Max Min Typ Max Unit DIGITAL OUTPUTS Output Voltage, High (V OH ) Full VI V D – 0.1 V D – 0.1 V Output Voltage, Low (V OL ) Full VI 0.1 0.1 V Duty Cycle DATACK Full IV 45 50 55 45 50 55 % Output Coding Binary Binary POWER SUPPLY V D Supply Voltage Full IV 3.
REV. 0 AD9883A –4– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.
REV. 0 –5– AD9883A PIN CONFIGURATION GND GREEN <7> GREEN <6> GREEN <5> GREEN <4> GREEN <3> GREEN <2> GREEN <1> GREEN <0> GND V DD BLUE <7> BLU.
REV. 0 AD9883A –6– PIN FUNCTION DESCRIPTIONS Pin Name Function OUTPUTS HSOUT Horizontal Sync Output A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be programmed via serial bus registers.
REV. 0 AD9883A –7– PIN FUNCTION DESCRIPTIONS (continued) Pin Name Function CLAMP External Clamp Input This logic input may be used to define the time during which the input signal is clamped to ground.
REV. 0 AD9883A –8– At that point the signal should be resistively terminated (75 Ω to the signal ground return) and capacitively coupled to the AD9883A inputs through 47 nF capacitors.
REV. 0 AD9883A –9– GAIN 1.0 0.0 00h FFh INPUT RANGE – Volts 0.5 OFFSET = 00h OFFSET = 3Fh OFFSET = 7Fh OFFSET = 00h OFFSET = 7Fh OFFSET = 3Fh Figure 2. Gain and Offset Control Gain and Offset Control The AD9883A can accommodate input signals with inputs ranging from 0.
REV. 0 AD9883A –10– The PLL characteristics are determined by the loop filter design, by the PLL Ch arge Pump Current and by the VCO range setting. The loop filter design is illustrated in Figure 6. Recommended settings of VCO range and charge pump current for VESA standard display modes are listed in Table V.
REV. 0 AD9883A –11– Table V. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats Refresh Horizontal Standard Resolution Rate Frequency Pixel Rate VCORNGE Current VGA 640 × 480 60 Hz 31.5 kHz 25.175 MHz 00 101 72 Hz 37.
REV. 0 AD9883A –12– P0 P1 P2 P3 P4 P5 P6 P7 5-PIPE DELA Y D0 D1 D2 D3 D4 D5 D6 D7 RGB IN HSYNC PxCK HS ADCCK DA T AC K D OUT A HSOUT V ARIABLE DURA TION Figure 8. 4:4:4 Mode (For RGB and YUV) P0 P1 P2 P3 P4 P5 P6 P7 5-PIPE DELA Y Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 RGB IN HSYNC PxCK HS ADCCK DA T AC K G OUT A HSOUT U0 V1 U2 V3 U4 V5 U6 V7 R OUT A Figure 9.
REV. 0 AD9883A –13– 2-Wire Serial Register Map The AD9883A is initialized and controlled by a set of registers, which determine the operating modes. An external controller is employed to write and read the Control Registers through the 2-line serial interface port.
REV. 0 AD9883A –14– Table VI. Control Register Map (continued) Write and Hex Read or Default Register Address Read Only Bits Value Name Function 0FH R/ W 7:1 0 ******* Bit 7 – Clamp Function. Chooses between HSYNC for Clamp signal or another external signal to be used for clamping.
REV. 0 AD9883A –15– Table VI. Control Register Map (continued) Write and Hex Read or Default Register Address Read Only Bits Value Name Function 15H R/ W 7:0 Test Register Bits [7:2] Reserved for future use. Bit 1 – 4:2:2 Output Formatting Mode.
REV. 0 AD9883A –16– 04 7–3 Clock Phase Adjust A 5-bit value that adjusts the sampling phase in 32 steps across one pixel time. Each step represents an 11.25 ° shift in sampling phase. The power-up default value is 16. CLAMP TIMING 05 7–0 Clamp Placement An 8-bit register that sets the position of the internally generated clamp.
REV. 0 AD9883A –17– 0E 5 Hsync Output Polarity One bit that determines the polarity of the Hsync output and the SOG output. Table XI shows the effect of this option.
REV. 0 AD9883A –18– 0F 4 Coast Input Polarity Override This register is used to override the internal circuitry that determines the polarity of the coast signal going into the PLL.
REV. 0 AD9883A –19– 13 7-0 Post-Coast This register allows the coast signal to be applied follow- ing to the Vsync signal. This is necessary in cases where post-equalization pulses are present. The step size for this control is one Hsync period. The default is 0.
REV. 0 AD9883A –20– Table XXXIV. Detected Coast Input Polarity Status Hsync Polarity Status Result 0 Coast Polarity Negative 1 Coast Polarity Positive 15 7 4:2:2 Output Mode Select A bit that configures the output data in 4:2:2 mode.
REV. 0 AD9883A –21– Data is read from the control registers of the AD9883A in a simi la r manner. Reading requires two data transfer operations: The base address must be written with the R/ W bit of the slave address byte LOW to set up a sequential read operation.
REV. 0 AD9883A –22– Table XXXVIII. Control of the Sync Block Muxes via the Serial Register Control Mux Serial Bus Bit Nos. Control Bit State Result 1 and 2 0EH: Bit 3 0 Pass Hsync 1 Pass Sync-on-G.
REV. 0 AD9883A –23– It is also recommended to use a single ground plane for the entire board. Experience has repeatedly shown that the noise perfor- mance is the same or better with a single ground plane. Using multiple ground planes can be detrimental because each sepa rate ground plane is smaller, and long ground loops can result.
REV. 0 –24– C02561–1–10/01(0) PRINTED IN U.S.A. AD9883A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead LQFP (ST-80) 61 60 1 80 20 41 21 40 TOP VIEW (PINS DOWN) PIN 1 0.630 (16.00) BSC SQ 0.551 (14.00) BSC SQ SEATING PLANE 0.063 (1.
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