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SER VICE MANU AL SPECTRUM Series LCD Monitor LM-700/LM-700A P/N : 41A50-144.
1 THESE DOCUMENTS ARE FOR REPAI R SERVICE INFORMATION ONLY. EVERY REASONABLE EFFORT HAS BEEN MADE TO ENSURE THE ACCU RACY OF THIS MANUAL; WE CANNOT GUARANTEE THE ACCURACY OF THIS INFORMATION AFTER THE DATE OF PUBLICATION AND DI SCLAIMS RE LIABILITY FOR CHANGES, ERRORS OR OMISSIONS, MANUFACTURE DATA : JULY.
2 TABLE OF CONTENTS PAGE 1. SPECIFICATIONS .................................................................................................... 3 1-1 GENERAL SPECIFICATIONS ...................................................….............. 3 1-2 LCD MONITOR DESCRIPTION .
3 1. SPECIFICATIONS FOR LCD MONITOR 1-1 General specifications 1. LCD-PANEL : Active display area 17 inches diagonal Pixel pitch 0.264 mm x 0.264 mm Pixel format 1280 x 1024 RGB vertical stripe arrangem ent 2. Display Color : 8-bit, 16 .7 milli on colors 3.
4 1-2 LCD MONIT OR DESCRIP TION The LCD MONITOR will contain a n main board, an Inve rter m odule, keyboard and External Adapter which house the flat panel contr ol logic, bri ghtness cont rol logic, DDC and DC-DC conver sion The Inverter module will drive the backlight of panel .
5 2. PRECAUTIONS AND NOTICES 2-1 ASSEMBLY PRECAUTION (1) Please do not press or scratch LCD panel surface w ith anything hard. And do not s oil LCD panel surface by touching with ba re hands (Polarize.
6 3. OPERATING INSTRUCTIONS This pr ocedure gi ves you i nstructions f or install ing and usi ng the LM70 0 LCD m onitor displ ay. 1. Position the display on the desired operation and plug–i n the power cord into Extern al Adapter AC outlet.
7 4. ADJUSTMENT 4-1 ADJUSTMENT CONDITIONS A ND PRECAUTIONS Adjustm ents should be u ndertake n only on foll owing fun ction : cont rast, bright ness focus, cloc k, h-posi tion, v-position, red, green, blue since 6500 co lor & 7800 color.
8 9. adjust the GREEN on OSD, until chro ma 7120 indicator reached G=100 10. adjust the BLUE on OSD, until chroma 7120 indicator reach ed B=100 11. repeat a bove proced ure ( item 8,9,10) until chrom a 7120 RGB val ue meet the tolence =100 ±2 12. switch the chroma-7120 to xyY mod e W ith press “MODE” butto n 13.
9 2. Clock ad justment Set the Chroma at pattern 63 (cr oss -talk pattern) or WIN98/95 sh ut - do w n m ode (dot-pattern). Adjust until the vertical-Stripe-shadow as wide as possible or no visible. This functio n is adjust the PLL divider of ADC to generate an acc urate pixel cloc k Example : Hsyn = 31.
10 5. CIRCUIT-DESCRIPTION 5-1 SPECIAL FUNCTION with PRESS-KEY A) . press Menu button during 2 second s along with plug-in the DC Power cord : That operation will set the monitor into “Facto ry- m od.
11 5-3 SIMPLE-INT RODUCTION about LM700 chipse t 1. GMZAN1 ( all-in-one ch ip solution for AD C, OSD, scalar and interpolation) : USE for computer graphics images to co nvert analog RGB data to digita l data with interpolation process, zooming, ge nerated the OSD fo nt , perform overl ay function and gene rate drive-timing for LCD-PA NEL.
12 GMZAN1 (U200) LVDS chip (U601, U602) Panel-Power Control (U202) MCU ( U302 ) Data Digital RGB Panel Control Signal: Dhs, Dvs, Dclk Panel Power 5V Communi cation signal: Hclk,Hfs ,Hdata0 Input analo.
13 5-4 SOFTWARE FLOW CH A RT I. Power-On Subrotine CHART OK Check White-b alance data(650 0 & 7800) same with the backup data ? Check POC( ba cklight counter ) data same wit h the backup data ? IF not same, overwrite the data with backup value. Initial GMZAN1 Yes POWER-ON STAR T Initial MCU I/O, Interrupt vector & Ram Initial 1.
14 II. MAIN SUBROTINE LOOP ) Main loop start Process Power-saving status ( accord ing to below flow-chart result) Check GMZAN IFM status .i s change or not.
15 6. A). Interface-Board Trouble-Shooting chart *Use the PC Win 98 white pattern, with some ico n on it, and Change the Resolution to 640x4 80 60 Hz / 31 KHz **NOTICE : The free-running freq.
16 PANEL-POWER CIRC UIT I NVERTER Control Relative Circuit OSCILLATOR BLOCK U200-DATA OUTPUT OK,R225 have r esponse check R225 s hould have response fr om 12V to 0V When we s witch the power swit ch f.
17 II (a) THE SCREEN is Abnormal , stuck at white screen, OSD window can’t appear, but keyboard & LED was normal operation. At general, this symtom is cause by m issing pane l data or panel power, so we must check our wire-harness which connected to panel or the panel power controller (U202) II.
18 KEYBOARD BLOCK check OK Check U302 pin 38 (LED green) will have transition from hi to low or low to hi when we press th e power key? ? Press power key and check U302 pin 43 = low (0V) ? OK Replace .
19 POWER-BLOCK check * *Note : the Waveform of U304 pi n 2 can dete rmined th e power situati on 1. stable rectangle waveform with eq ual duty, freq around 150 K- 1 58 K Hz that means all power of this interface board is in normal operation ,and all status of 5V & 3.
20 III.ALL SCREEN HAS INTE RFERENCES OR NOISE, CA N’T BE FIXED BY AUTO KEY ** NOTE: There is s o many kind of i nterferences, 1). One is cause by some VGA-CARD that not m eet VESA spec or power grou nding too bad that infl uence our circuit 2).other is ca use by external interference s, move the m onitor far from electronic equi pment.
21 There is an interferences in DOS MODE NOTE :the criteria of doing AUTO-CONFIGU RATION : must be a full-size screen, if the screen not full , the auto- configuration will fail.
22 6 B). Inverter –MODULE Spec &Trouble Shooting Chart In LM700 model , we use CHI-MEI panel, and the INVERTER PROVIDER is SAMPO- CORPORATION SAMPO CORPORATION T R O U B L E S H O O T I N G O F C H I - M E I I N V E R T E R ( DIVTL0037-D42- -) 1.
23 SAMPO CORPORATION T R O U B L E S H O O T I N G O F C H I - M E I I N V E R T E R ( DIVTL0037-D42- -) 5.FUNCTION SPECIFICATIONS: The data test with the set of SAM PO, and the test circuit is as below. 6. FUNCTION LOAD CIRCUIT: ITEM SYMBOL MIN. TYP.
24 SAMPO CORPORATION T R O U B L E S H O O T I N G O F C H I - M E I I N V E R T E R ( DIVTL0037-D42- -) 7.CIRCUIT DIAGRAM: GD D D D S S S GD D D D S S S.
25 SAMPO CORPORATION T R O U B L E S H O O T I N G O F C H I - M E I I N V E R T E R ( DIVTL0037-D42- -) 8.PART LIST 8-1 COMPONENTS LIST: NO. REF. PART NAME PART NUMBER QTY DESCRIPTION SUPPLIER REMARK 1. CON1 CONNECTOR VCNCP0015-EJST A 1 S5B-PH-SM3-TB JST 2.
26 SAMPO CORPORATION T R O U B L E S H O O T I N G O F C H I - M E I I N V E R T E R ( DIVTL0037-D42- -) 8-2 COMPONENTS LIST: NO. REF. PART NAME PART NUMBER QTY DESCRIPTION SUPPLIER REMARK 26. C6 〃 VCLRCN1HB102K-A 1 SMD 0805 1000PF/50V TDK 27. C10,11 〃 VCLRCN1EB333K-A 2 SMD 0805 0.
27 SAMPO CORPORATION T R O U B L E S H O O T I N G O F C H I - M E I I N V E R T E R ( DIVTL0037-D42- -) 9. TROUBLE SHOOTING 9-1 NO POWER: . F A I L P A S S F A I L P A S S F A I L PASS CHECK ON FUSE F1 Vin=12 TO CHANGE F1= 4.
28 SAMPO CORPORATION T R O U B L E S H O O T I N G O F C H I - M E I I N V E R T E R ( DIVTL0037-D42- -) 9-2 HIGHT VOLTAGE PROTECTION: FAIL PASS 9-3 OUTPUT CURRENT ABNORMALITY: FAIL PASS 1.
29 SAMPO CORPORATION T R O U B L E S H O O T I N G O F C H I - M E I I N V E R T E R ( DIVTL0037-D42- -) 9-4. ENBALE ABNORMALITY: FAIL PASS 9-5 DIMMING CONTROL ABNORMALITY: F A I L PASS IF ENBALE ABNORMALITY 1.
30 - 9 - SAMPO CORPORATION T R O U B L E S H O O T I N G O F C H I - M E I I N V E R T E R ( DIVTL0037-D42- -) 9-6 TRANSFORMER ABNORMALITY: F A I L P A S S 10. INSTRUMENTS FOR TEST: 1. DC POWER SUPPLY GPS-3030D 2. AC VTVM VT:-181E 3. DIGITAL MULTIMERTER MODEL-34401 4.
31 6 C). ADAPTER-MODULE Tr ouble shooting chart The following spec & block-diagram is offer by CHI-SAM –COMPANY, for External Adapter part number : 80AL17-1-CH ( Bl ack), 80AL17-2-CH ( White) AC ADAPTER CH-1205 TROUBLE SHOOTING NO VOLTAGE O/ P CHECK BD101 AC VOLT.
32 I.) Adapter Schematic CH-1205 Please see the ADAPTER-SCHEMATIC in the end of this Document ( page 75).
33 IV. ADAPTER BOM LIST ( PART no. 80AL15-2-LI) Item Referen ce Part Quan tity Cat.NO. 1 BD101 DIODE BRIDGE KBL405G 600V/4A 1 PCS 15D7L405G6 2 CN101 AC POWER SOCKET 1 PCS 64P21-0001 3 BEAD1,BEAD2,BEAD3,BEAD4 BEAD 3.
34 41 PCB PCB FOR CH-1205 REV:D 1 PCS 11S43-0030 42 R117 RES 100 1/8W +-5% SMD(0805) 1 PCS 2242510000 43 J109,J110 RES 0 OHM 1/4W +-5% SMD(1206) 2 PCS 2243500000 44 R143 RES 1.
35 86 FOR FRONT HEATSINK 導熱墊片 TCR- 05 15*25-ASAHI 1 PCS 85011-0001 87 FOR FRONT HEATSINK 導熱墊片 TCR- 10 10*20-ASAHI 1 PCS 85100-0001 88 3M擋牆膠帶#44 1L 35*40mm 1 PCS 80400-0001 89 FRONT COVER 129.3*63.8*19.34mm 1 PCS 0810400020 90 BASE COVER 129.
36 6 D). AUDIO-MODULE Trouble shooting chart I.) NO VOICE OUTPUT ] Use OHM-METER m easure U1 pi n 2, 4 (channel-A ) is speaker well connected? Measure U1 pi n 10,12 ( channel B) is speak er well connected ? Plug-out the DC power , make sure the monitor is in OFF status .
37 II.) SOUND DISTORTION AUDIO BOM B i l l O f M a t e r i a l s S e p t e m b e r 7 , 2 0 0 1 1 8 : 0 9 : 1 4 P a g e 1 Item Quantity Referen ce Part _________________ ________________ _____________ 1 3 C1,C2,C4 1uF 2 1 C3 2200uF/25V 3 1 C5 10uF/50V 4 2 C6,C7 0.
38 GMZAN1 The gmZAN1device utilizes Genesis’ patented third-genera tion Adv anced Image Magnification technology as well as a proven integrated ADC/PLL to provide ex cellent imag e quality within a cost effective SVGA/XGA LCD monitor solution.
39 1.3 Pin Description Unless otherwise stated, unused inpu t pins must be tied to ground, and unused outpu t pins left open. Table 1 : Analog-to-Digital Converter PIN # Name I/O Description 77 ADC_VDD 2 Digital po wer for ADC e n coding logic. M ust be bypassed with 0.
40 Table 2 : Host Interface (HIF ) / External On-Screen Display PIN # Name I/O Description 98 HFS I Host Frame Sync. Fram es the p acket on the serial channel. 103 HCLK I Clock signal i nput for the 3-wire seri al communication. 99 HDATA I/O Data signal for the 3-wire serial comm unication.
41 Table 3 : Clock Recovery / Time Base Conversion PIN # Name I/O Description 125 DVDD Digital power for Destination DDS (direct digital synthesizer). Mu st be bypassed with a 0.1uF capacitor to digital gro und plane. 127 DAC_D GNDA Analog ground for Destin ation DDS DAC.
42 Table 4. TFT Panel Interface PIN # Name I/O Description 2pxl/clk 2pxl/clk 1pxl/clk 1pxl/clk 8 b i t 6 - b i t 8 - b i t 6 - b i t T F T 6 P D 4 7 O O B 1 - - - 7 P D 4 6 O O B 0 - - - 9 P D 4 5 O O.
43 PIN # Name I/O Description 2pxl/clk 2pxl/clk 1pxl/clk 1pxl/clk 8 b i t 6 - b i t 8 - b i t 6 - b i t T F T 6 3 P D 7 O E G 3 E G 1 G 3 G 1 6 4 P D 6 O E G 2 E G 0 G 2 G 0 6 6 P D 5 O E R 7 E G 5 R .
44 1.4 System-level Block Diagram Figure 2. Typical Stand-alone Configuration DVDDA Panel Interface SVDDA SGNDA OSC ADC RVDDA Host Interface DGNDA Clock Generator ADC_VDD gmZAN1 Core ADC_GND ADC RGNDA.
45 1.5 Operating Modes The Source Cl ock (also calle d SCLK in this document) and the Pa nel Clock are defined as follows: z The Source Cl ock is the sample cl ock regenerated from the input Hsy n c tim ing (called cloc k recovery) by SCLK DDS (direct digital synthesis) and the PLL.
46 1.5.4 Downscaling Panel Clock frequency < So urce Clock frequency Panel Hsync frequ en c y < Inpu t Hsync frequency Panel Vsync frequ en c y = Inpu t Vsync frequency This mode is used when the input resolu tion is greater than the panel reso lution, to provide enough of a display to enable the user to recover to a supported resolu tion.
47 2. FUNCTIONAL DESCRIPTION Figure 3 belo w shows the main fu nctional bl ocks inside the gmZAN1 2.1 Overall Architecture Figure 3. Bloc k Diagram for gmZ A N1 2.2 Clock Recovery Circuit The gmZAN1 has a built-in clock recovery circuit. This circuit consists of a digital clock synthesizer and an analog PLL.
48 The SCLK freque ncy (1/SCLK period) can be set to the range of 10-to-135 MHz. Usin g the DDS (direct digital synthesis) technol ogy the clock recovery ci rcuit can ge nerate any SCL K clock frequency within this range. The pixel cloc k (DCLK or desti nation clock) is used to drive a panel when the panel clock is different from SCLK (or SCLK/2).
49 The table below summ arizes the characteris tics of the clock rec overy circuit. Table 7. Clock Recovery Characteristics Minimum Typical Maximum SCLK Frequency 10MHz 135 MHz Sampling Pha se Adjustm ent 0.5 ns/step, 64 steps Patented digi tal clock synt hesis technology m akes the gmZAN1 clock circuit s very i mmune to temperature/v oltage drift.
50 2.3 Analog-to-Digital Converter 2.3.1 Pin Connection The RGB signals are to be connected to the gm Z AN1 chip as describe d in Table 8 and Ta ble 9.
51 2.3.2 Sync. Signal Support The gmZAN1 chip supports digital separate sync (Hsy nc/Vsync), digital com posite sync, and analog com posite sync (also known as sync-on -g reen). All sync types are supported without extern al syn c separation / extraction circuits.
52 The display start/end registers store th e first and the last pixels/lines of the last frame that have RGB data above a programm ed threshold. The reference point of the STM bloc k is the sam e as .
53 2.5.1 Scaling Filter The gmZAN1 scaling filter uses an advanced adaptive sca ling technique prop rietary to Genesis Microchip Inc. and provides high quality scaling of real time video and gra p hics images.
54 Table 13. gmZAN1 TFT Panel Interface Timing Signal Name Min Typical Max Unit Period t1 0 16.6 7 2048 - lines ms Frequency 60 - Hz Front porch t2 0 2048 lines Back porch t3 0 2048 lines Pulse width t4 0 2048 lines PdispE t5 0 Panel height 2048 lines Disp.
55 Figure 7. timing Diagr ams of the TFT Panel Inter face (One pixel per clock) (a) Vertical size in TFT (b) Vsync width and display position in T FT (c) Horizontal siz e in TFT (d) Hsync width in TFT.
56 Figure 8. Data latch timing of the TFT P anel Interface (a) Two pixel per clock mode in TFT (b) One pixel per clock mode in TFT 2.6.2 Power Manager LCD panels re quire logic power, panel bias power, and control si gnals to be seque n ced in a specific order, other w i se severe dam age may occur and disable t h e panel permanen tly.
57 2.6.2.1 State 0 (Power Off) The Pbias signal and Ppower signal are lo w (inactive ) . The pa nel controls and dat a are forced low. This is the final state in the power down sequence. PM is kept in state 0 until the panel is enabled. 2.6.2.2 State 1 (Power On) Intermediate step 1.
58 2.6.3 Panel Interface Drive Strength As mentioned previously, the gmZAN1 ha s programmable ou tput pads for the TFT pa nel interface. Three groups of panel interface pads (panel cl ock, data, and control) are i ndependently controllable and are pr ogrammed using API calls.
59 2.7.1 Serial Communication Protocol In the serial com munication bet w een the m icrocontrolle r and the gmZAN1, t h e microcontroller al ways acts as an initiator while the gmZAN1 is always the target. The following timing diagram describes the protocol of the serial channel of the gmZAN1 chip.
60 Table 15 summarizes the serial channel specification of the gmZAN 1. Refer to Figu re 10 for the timing param eter definition. Table 15. gmZAN1 Serial Channel Specificati on Parameter Min.
61 2.8.1 OSD Color Map Both the internal and external OSD di splay use a 16 location SRAM block for the color programming. Each color location is a twelve-bit value that defi nes the upper four bits o.
62 To improve the appearance and m ake it easy to find the OSD window on th e screen, the user may select optional shadowing (3D effect). The “Shadow” feat ure operates in the same manner as in th.
63 3. ELECTRICAL CHARACTERISTICS Table 20. Absolute Ratings Parameter Min. Typ. Max. Note PVDD 5.6 volts CVDD 5.6 volts Vin Vss-0.5 volt Vcc+0.5V Operating temperature 0 degree C 70 degree C Storage tem p erature -65 degree C 150 degree C Maxim um power c onsumpt ion ~2W Table 21.
64 7. MECHANICAL OF CABINET FRONT DIS-ASSEMBLY For temporary, this page still not available. Wait for mechanical drawing !.
65 PARTS LIST OF CABINET LOCATION T780KMGHBA A0A SPECIFICATION AUPC780A1 17” LCD AUDIO BOARD CBPC780GM 17” CONVERSION BOARD DCPC780A3 17” DC POWER BOARD KEPC780EK KE YBOARD 12A 381 1 RUBBER FOOT 15A 5684 1 MAIN FRAME 15A 5689 1 GND.CABLE CLAMP 15A 5689 2 GND.
66 PARTS LIST OF CABINET ( continue) LOCATION T780KMGHBA A0A SPECIFICATION Q1A 1030 10128 SCREW Q1A 1030 12128 SCREW 3X12mm Q1A 1030 12128 SCREW 3X12mm 750A LCD 170 3 LCD-PANEL M170E1-01 BY CHI-MEI.
67 PARTS LIST OF CONVERSION BOARD LOCATION CBPC780GM SPECIFICATION CN303 33A 3802- 5H WAFER 5P RIGHT ANELE PITCH 2.0 CN302 33A 3802- 9H WAFER 9P RIGHT ANELE PITCH 2.0 CN602 33A 3802- 10H WAFER 10P RIGHT ANELE PITCH CN601 33A 3802- 14H WAFER 14P RIGHT ANELE PITCH R319 33A 8009- 2 - 2 PIN MIN.
68 LOCATION AI780GM SPECIFICATION U601 56A 561- 5 NT7181 56L TSSOP U602 56A 561- 5 NT7181 56L TSSOP U200 56A 562- 8 gmZAN1 PQFP-160 GENESIS U304 56A 563- 1 CHIP LM2596S- 5.
69 LOCATION AI780GM SPECIFICATION C616 65A 0603- 103 - 32 CHIP 0.01UF 50V X7R C201 65A 0603- 104 - 12 CHIP 0.1UF 16V X7R C202 65A 0603- 104 - 12 CHIP 0.1UF 16V X7R C204 65A 0603- 104 - 12 CHIP 0.1UF 16V X7R C205 65A 0603- 104 - 12 CHIP 0.1UF 16V X7R C207 65A 0603- 104 - 12 CHIP 0.
70 LOCATION AI780GM SPECIFICATION C603 67A 312 101 3 1 SMD EC 100UF 16V 85C D C943 67A 312 101 3 1 SMD EC 100UF 16V 85C D C313 67A 312 220 3 1 SMD EC 22UF 16V 85C CSIZE C314 67A 312 220 3 1 SMD EC 22U.
71 PARTS LIST OF KEY PC BOARD LOCATION KEPC780EK Quantity SPECIFICATION TP101 9A 308 1 PIN TP102 9A 308 1 PIN J7 33A 3252 3 H WAFER 3P 3.96mm 90 40A 152 44 LABEL ( KEPC780EK) Q101 57A 419 PP T Q102 57.
72 PARTS LIST OF DC-POWER B OARD PARTS LIST OF AUDIO BOARD LOCATION DCPC780A3 Quan tity SPECIFICATION P4 33A 3278 2 1 2P PLUG B2B-XHA/JST B2B-XHA/JS P3-1 33A 3278 3 1 3P PLUG B3B-XHA/JST B3B-XHA/JS C71 67A 305 331 6 1 330uF+ － 20% 35V J2 88A 302 4 S 1 3.
73 9. POWER SYSTEM AND CONSUMPTION CURRENT ADAPTER MODULE Input AC 11 0V, 60Hz/240V, 50Hz Output DC 1 2 V 5A INVERTER MODULE Input DC 12V Output A C 1500V/30K-80KHz Current 14mA Main board power system LM2596S-5, 12V to 5V (5A SPEC) 5V To CPU, Ee prom, 24c21, cont rol-inverter -on.
74 10. PCB LAYOUT G mzan1 M CU LVDS Keyboard-connector In ve rt er - co nn ec t or M CU Panel- Power Control AIC1084 5V to 3.3v LVDS power ( LT1117) LM2596 convert 12V to 5V Input Connector DDC chi p .
75 11. SCHEMATIC DIAGRAM I). TOP -LEVEL FLOW PAGE 4 POWER +12V +5V +3.3V PAGE 3 ZAN1 TCLK1 +3.3V +5V +12V MFB2 MFB7 MFB8 MFB9 /VGA_CON RXD TXD HCLK HFS IRQ HDATA0 RST SDA SCL RST1 MFB1 MFB2 PDISPE PVS PHS PCLK OBLU OGRN ORED EBLU EGRN ERED PAGE 6 LVDS ERED EGRN EBLU OBLU OGRN ORED PCLK PHS PVS PDISPE 763-17.
ADC-AGND OGRN4 C227 0.1 uF ORED[4..7] OGRN5 EGRN1 C208 0.1 uF R229 0 R202 0 R316 NC OGRN5 C231 10 nF ERED3 ORED0 OGRN0 +P5V Connect two grounds at single point only. PCLKA VGA_SCL ORED6 EGRN3 ERED6 OGRN1 EGRN6 PPWR OBLU5 D209 5.6V U401D 74LVT14_ADC 9 8 R326 10 K ERED7 C214 100uF TXD OGRN[4.
AVDD_3.3 PD23 TX2+E TX0-E TX0-O PD22 PD10 AVDD_3.3 TXO6 TXCK+O TXE0 TXE4 PD14 TXCK-O + C605 10uF 16V TX1+O TX0+O TX2+E EGRN[0..7] TXO4 TXE3 PD20 TX0+O PD12 PD7 + 100uF C603 PD42 TXCK-E TX1+E TXE9 TX1-O TXCK+E PD36 C614 0.01UF TXO9 ODD PD8 PD31 PD47 C616 0.
2 C305 100uF RXD R328 10 K RST R402 1K(OP) U300 24LC04B 5 6 7 8 1 2 3 4 SI SCK WP VCC A0 A1 A2 VSS GND +5V GND GND C304 0.1 uF CP301 1000 pF 1 5 6 8 4 3 2 7 GND R340 0 GND HDATA0 KEY4(ENTER) KEY7(POWE.
3 +3.3V D300 B320 U305 AIC 1084 1 2 3 GND Vout Vin +A5V L905 CHOKE FB301 INDUCTOR +5V GND GND GND GND C307 330 uF/35V R905 0 +5V TP703 GND 1 C312 330 uF/35V T300 33 uH TP700 GND 1 715A820-1 B POWER AOC (Top Victory) Electronics Co.
4 R119 4.7K CN101 AC SOCKET B R106 3M 1/4W 4 Q102 2SC4505 R118 4.7K 4 T101 PQ2620 for CH-1205 3 C115 CY 2200P/250V C125 NC* HS101 HEATSINK D105 1N4148 1 K C123 0.1U U104A BA10358F R121 8.2K 1% R143 1.8K R123 150 1/4W C112 270P (NPO) VAR101 471KD07 R144 4.
5 J4 AUDIO IN 1 2 3 GND R2 10K R10 1(3W) GND R6 15K GND + C3 2200uF/25V + C5 10uF/50V GND + C1 1uF GND GND <Doc> <RevCode> A 11 Friday, April 27, 2001 Title Size Document Number Rev Date: .
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