Gebruiksaanwijzing /service van het product PD17062 van de fabrikant NEC
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The information in this document is subject to change without notice. DA T A SHEET MOS INTEGRA TED CIRCUIT µ PD17062 Document No. IC-3560 (O.D. No. IC-8937) Date Published January 1995 P Printed in Japan The µ PD17062 is a 4-bit CMOS microcontroller for digital tuning systems.
2 µ PD17062 ORDERING INFORMATION Part number Package µ PD17062CU- ××× 48-pin plastic shrink DIP (600 mil) µ PD17062GC- ××× 64-pin plastic QFP (14 × 14 mm) Remark ××× is the ROM code number.
3 µ PD17062 PIN CONFIGURATION (TOP VIEW) 48-pin plastic shrink DIP (600 mil) ADC 0 to ADC 5 : A/D converter input P0D 0 to P0D 3 : Port 0D BLANK : Blanking signal output P1A 0 to P1A 3 : Port 1A BLUE.
4 µ PD17062 64-pin plastic QFP (14 × 14 mm) 1 3 2 4 6 5 7 9 8 10 12 11 13 15 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 46 47 45 43 44 42 40 41 39 37 38 36 34 35 33 64 63 62 61 60 59 5.
5 µ PD17062 BLOCK DIAGRAM VCO PSC EO H SYNC V SYNC RED GREEN BLUE BLANK P0A 0 /SDA P0A 1 /SCL P0A 2 /SCK P0A 3 /SO P0B 0 /SI P0B 1 P0B 2 /TMIN P0B 3 /HSCNT P0D 0 /ADC 2 P0D 1 /ADC 3 P0D 2 /ADC 4 P0D .
6 µ PD17062 CONTENTS 1. PINS ............................................................................................................................................. 11 1.1 PIN FUNCTIONS ..........................................................
7 µ PD17062 8.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP) ...................... 57 8.6 GENERAL-PURPOSE REGISTER POINTER (RP) .......................................................................... 6 6 8.7 PROGRAM STATUS WORD (PSWORD) .
8 µ PD17062 11.5 RETURNING CONTROL FROM INTERRUPT PROCESSING ROUTINE ..................................... 11 6 11.6 INTERRUPT PROCESSING ROUTINE ........................................................................................... 11 7 11.7 EXTERNAL INTERRUPTS (INT NC PIN, V SYNC PIN) .
9 µ PD17062 17. D/A CONVERTER ....................................................................................................................... 2 17 17.1 PWM PINS .................................................................................
10 µ PD17062 23.5 PERIPHERAL HARDWARE REGISTER .......................................................................................... 28 6 23.6 OTHERS ...............................................................................................
11 µ PD17062 1. PINS 1.1 PIN FUNCTIONS Pin No. DIP QFP (GC) Symbol Description Output type At power-on reset P0C 3 | P0C 0 P0D 3 /ADC 5 | P0D 0 /ADC 2 PWM 3 | PWM 0 V DD V DD1 V DD0 VCO EO GND GND2 G.
12 µ PD17062 Pin No. DIP QFP (GC) Symbol Description Output type At power-on reset P1A 3 | P1A 0 P1B 3 | P1B 0 RED GREEN BLUE BLANK H SYNC V SYNC P1C 3 /ADC 1 P1C 2 P1C 1 ADC 0 P0B 3 /HSCNT P0B 2 /TM.
13 µ PD17062 Pin No. DIP QFP (GC) Symbol Description Output type At power-on reset INT NC NC 48 — 55 5 6 7 8 10 12 14 22 25 37 39 40 41 42 44 56 57 Interrupt input. Contains the noise canceler. An interrupt can be generated at either the rising or falling edge of the input signal.
14 µ PD17062 1.2 EQUIVALENT CIRCUITS OF THE PINS P0A (P0A 3 /SO, P0A 2 /SCK) P0B (P0B 1 , P0B 0 /SI) P1B (P1B 3 , P1B 2 , P1B 1 , P1B 0 ) P1C (P1C 3 /ADC 1 , P1C 2 , P1C 1 ) V DD V DD A/D converter (.
15 µ PD17062 P0C (P0C 3 , P0C 2 , P0C 1 , P0C 0 ) RED, GREEN, BLUE, BLANK, PSC (Output) PWM (PWM 3 , PWM 2 , PWM 1 , PWM 0 ) P1A (P1A 3 , P1A 2 , P1A 1 , P1A 0 ) (Output) P0D (P0D 3 /ADC 5 , P0D 2 /A.
16 µ PD17062 P0B 3 /HSCNT Port Horizontal synchronizing signal counter P-ch N-ch P0B 2 /TMIN Port Timer/counter P-ch N-ch.
17 µ PD17062 H SYNC , V SYNC , INT NC , CE (Hysteresis input) X OUT , X IN X IN X OUT EO VCO (Input).
18 µ PD17062 2. PROGRAM MEMORY (ROM) Program memory stores the program to be executed by the CPU, as well as predetermined constant data. 2.1 CONFIGURATION OF PROGRAM MEMORY Fig. 2-1 shows the configuration of program memory. As shown in Fig. 2-1, the capacity of the program memory is 8K bytes (3968 × 16 bits).
19 µ PD17062 2.2 FUNCTIONS OF PROGRAM MEMORY Program memory has two basic functions: (1) Program storage (2) Constant data storage A program is a set of instructions that control the CPU (Central Processing Unit: Device that actually controls the microcontroller).
20 µ PD17062 2.4 BRANCHING A PROGRAM A program is branched by execution of the branch instruction (BR). Fig. 2-2 illustrates the operation of the branch instruction. Branch instructions (BR) are divided into two types. Direct branch instructions (BR addr) transfer control to a program memory address (addr) directly specified in its operand.
21 µ PD17062 Fig. 2-2 Operation of Branch Instruction and Machine Code (a) Direct branch (BR addr) (b) Indirect branch (BR @AR) Address Program memory Label: Instruction (Machine code) Page 0 Page 1 .
22 µ PD17062 2.5 SUBROUTINE If a subroutine is executed, the specialized subroutine call instruction (CALL) and subroutine return instruction (RET, RETSK) are used. Fig. 2-3 illustrates the operation of subroutine call. Subroutine call instructions are divided into two types.
23 µ PD17062 Fig. 2-3 Operation of Subroutine Call Instruction (a) Direct subroutine call (CALL addr) (b) Indirect subroutine call (CALL @AR) Address Program memory Instruction CALL SUB1 Page 0 Page .
24 µ PD17062 2.6 TABLE REFERENCE The table reference instruction is used to reference the constant data in program memory. If the MOVT DBF, @AR instruction is executed, data at the program memory address specified in an address register is placed in a data buffer (DBF).
25 µ PD17062 3. PROGRAM COUNTER (PC) The program counter addresses program memory or a program. It is a 12-bit binary counter. Fig. 3-1 Program Counter PC 11 PC 9 PC 10 PC 8 PC 6 PC 7 PC 5 PC 3 PC 4 .
26 µ PD17062 4. STACK The stack is a register used to save an address returned by a program or the contents of the system register, described later, when a subroutine call occurs or an interrupt is accepted.
27 µ PD17062 4.3 ADDRESS STACK REGISTERS (ASRs) There are six address stack registers, each consisting of 13 bits. After a subroutine call instruction has been executed or an interrupt request accept.
28 µ PD17062 Fig. 4-3 Structure of Interrupt Stack Registers MSB LSB 0H 1H BANKSK0 BANKSK1 IXESK0 IXESK1 Fig. 4-4 Behavior of Interrupt Stack Registers Not defined B A Not defined A Not defined A Not defined Not defined Not defined RETI RETI Interrupt B Interrupt A V DD is applied.
29 µ PD17062 5. DATA MEMORY (RAM) Data memory is used to store data for operations and control. Simply by executing an appropriate instruction, data can be written to and read from data memory at any time. 5.1 STRUCTURE OF DATA MEMORY Fig. 5-1 shows the structure of data memory.
30 µ PD17062 Fig. 5-1 Data Memory Structure 0123456789 ABCD E F 0 1 2 3 4 5 6 7 DBF3 DBF2 DBF1 DBF0 P0A (4 bits) System register P0B (4 bits) P0C (4 bits) P0D (4 bits) BANK0 0123456789 ABCD E F 0 1 2.
31 µ PD17062 5.1.1 Structure of the System Register (SYSREG) The system register consists of 12 nibbles, located at addresses 74H to 7FH in data memory. The system register is allocated regardless of the bank. That is, the system register is always located at addresses 74H to 7FH, regardless of the bank.
32 µ PD17062 5.1.3 Structure of the General-Purpose Register (GR) The general-purpose register consists of 12 nibbles, specified with an arbitrary row address, in data memory. An arbitrary row address is specified using the general-purpose register pointer in the system register.
33 µ PD17062 5.1.4 Structure of Port Data Registers (port register) The port registers consist of 12 nibbles at addresses 70H to 73H of the banks of data memory. Fig. 5-5 shows the structure of the port registers. As shown in Fig. 5-5, the same port registers are allocated in BANK0 and BANK2.
34 µ PD17062 5.2 FUNCTIONS OF DATA MEMORY Data memory can be used to perform, with one instruction, a four-bit operation, comparison, decision, or transfer of the data in data memory and immediate data (arbitrary data) by executing one of the data memory manipulation instructions listed in Table 5-1.
35 µ PD17062 5.2.1 Function of System Register (SYSREG) The system register is used to control the CPU. For example, the bank register shown in Fig. 5-2 is used to specify a data memory bank, while the general- purpose register pointer specifies the row address of the general-purpose register.
36 µ PD17062 Table 5-1 Data Memory Manipulation Instructions Function Instruction ADD ADDC SUB SUBC AND OR XOR SKE SKGE SKLT SKNE MOV LD ST SKT SKF Addition Subtraction Logical operation Operation Co.
37 µ PD17062 Fig. 5-6 Correspondence Between Port Registers and Ports (Pins) 70H P0A 71H P0B 72H P0C 73H P0D 70H P1A 71H P1B 72H P1C 73H Fixed at 0 b 3 P0A3 b 2 P0A2 b 1 P0A1 b 0 P0A0 b 3 P0B3 b 2 P0.
38 µ PD17062 5.3 NOTES ON USING DATA MEMORY 5.3.1 Addressing Data Memory If the 17K series assembler is being used and a numeric representing a data memory address is specified directly in an operand of a data memory manipulation instruction, as shown in example 1, an error will occur.
39 µ PD17062 Example 2. 5.3.2 Notes on Using Unmounted Data Memory As shown in Fig. 5-6, nothing is actually assigned to bit 0 (LSB) of address 72H of BANK1 of the port registers.
40 µ PD17062 6. GENERAL-PURPOSE REGISTER (GR) The general-purpose register is allocated in data memory space, and is used to perform direct operations on the data in data memory and to transfer data to and from data memory. 6.1 STRUCTURE OF THE GENERAL-PURPOSE REGISTER Fig.
41 µ PD17062 Fig. 6-1 Structure of General-Purpose Register RPH RPL 7DH 7EH b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 00 0 0 b 2 b 1 b 0 B C D (RP) 01 23 45 6789A B C DE F 0 2 3 4 5 6 7 1 0 2 3 4 5 6 7 1 0 2 3 4 5 6 7 1 Column address Row addresses 0H to 7H of BANK0 can be freely specified using the general- purpose register pointer (RP).
42 µ PD17062 6.3 ADDRESS GENERATION FOR GENERAL-PURPOSE REGISTER AND DATA MEMORY IN INDIVIDUAL INSTRUCTIONS Table 6-1 lists the operation and transfer instructions that can be executed for the data in the general- purpose register and data memory.
43 µ PD17062 Example 1. When BANK0 is selected AND RPL, #0001B ; RP ← 0000000B; The general-purpose register is allocated in row ; address 0H in BANK0.
44 µ PD17062 Example 2. When BANK0 is selected and MPE = 0 is specified MOV 04H, #8 ; 04H ← 8 AND RPL, #0001B ; RP ← 0000000B; The general-purpose register is allocated in row ; address 0H in BANK0. MOV @04H, 52H Executing the above instruction transfers the contents of data memory address 52H to address 58H.
45 µ PD17062 Example 3 shows a program that transfers eight words of data from BANK2 to BANK0 data memory in units of four words, as shown in Fig. 6-4.
46 µ PD17062 6.4 NOTES ON USING THE GENERAL-PURPOSE REGISTER This section provides notes on using the general-purpose register, referring to the following example: Example AND RPL, #000B ; RP ← 000.
47 µ PD17062 Fig. 6-5 Execution of the Above Example Also, note the following when the general-purpose register is being used. No arithmetic/logical instructions are provided for the general-purpose register and immediate data.
48 µ PD17062 7. ARITHMETIC LOGIC UNIT (ALU) BLOCK 7.1 OVERVIEW Fig. 7-1 is an overview of the ALU block. As shown in Fig. 7-1, the ALU block consists of the ALU, temporary storage registers A and B, program status word, decimal conversion circuit, and data memory address controller.
49 µ PD17062 7.2 CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK 7.2.1 ALU In response to a programmed instruction, the ALU performs 4-bit arithmetic or logic processing, bit discrimination, comparative discrimination, rotation, or transfer.
50 µ PD17062 Table 7-1 ALU Operations ALU function Addition Subtraction Logic operation Discrimi- nation Comparison Transfer Rotation ADD ADDC SUB SUBC OR AND XOR SKT SKF SKE SKNE SKGE SKLT LD ST MOV.
51 µ PD17062 Table 7-2 Modification of the Data Memory Address and Indirect Transfer Address by the Index Register and Data Memory Row Address Pointer BANK : Bank register IX : Index register IXE : I.
52 µ PD17062 Table 7-3 Converted Decimal Data Remark Correct decimal conversion is not possible in the shaded area. Operation result Hexadecimal addi- tion 0 0 0000B 0 0000B 1 0 0001B 0 0001B 2 0 001.
53 µ PD17062 7.4 NOTES ON USING THE ALU 7.4.1 Notes on Using the Program Status Word for Operations After an arithmetic operation has been performed on the program status word, the operation result is held in the program status word.
54 µ PD17062 8. SYSTEM REGISTER (SYSREG) “System register” is the generic name for those registers directly related to CPU control. System registers are allocated at addresses 74H-7FH in data memory and can be referenced regardless of the bank specification.
55 µ PD17062 b 3 0 b 2 0 b 1 0 b 0 0 b 3 0 b 2 0 b 1 0 b 0 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 AR 15 (MSB) AR 0 (LSB) AR0 (77H) AR1 (76H) AR2 (75H) AR3 (74H) 8.1 ADDRESS REGISTER (AR) The address register specifies a program memory address. It is located at addresses 74H-77H.
56 µ PD17062 8.3 BANK REGISTER (BANK) The bank register specifies a data memory bank. The bank register contains BANK0 upon reset. The two high-order bits of address 79H are consistently set to 0. Data memory is classified into three banks by the bank register.
57 µ PD17062 8.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP) 8.5.1 Configuration of Index Register and Data Memory Row Address Pointer As shown in Fig. 8-1, the index register consists of 11 bits, including the three low-order bits, of 7AH (IXH) of the system register, 7BH, and 7CH (IXM, IXL).
58 µ PD17062 8.5.2 Functions of Index Register and Data Memory Row Address Pointer When a data memory manipulation instruction is executed with the index enable flag (IXE) set to 1, the index register ORs the data memory bank/address specified by the instruction and the contents of the index register.
59 µ PD17062 Table 8-2 Modification of Data Memory Address by Index Register and Data Memory Row Address Pointer M ; Data memory address BANK ; Bank register (M) ; Contents of data memory address (BA.
60 µ PD17062 8.5.3 For MPE = 0 and IXE = 0 (Data Memory Not Modified) As shown in Table 8-2, data memory addresses are not affected by the index register or data memory row address pointer.
61 µ PD17062 Fig. 8-3 Indirect Transfer of General-Purpose Register with MPE = 0 and IXE = 0 Address generation of example 2 R M 0 0 0 0 3 3 5 4 8 (@ r) @ r, m MOV 05H 34H 01 2 3 45 6 7 89 AB C D E F 8E 0 1 2 3 4 5 6 7 Column address Row address Example 1.
62 µ PD17062 8.5.4 For MPE = 1 and IXE = 0 (Diagonal Indirect Transfer) As shown in Table 8-2, the bank and row address of the data memory address in the indirect side specified by the general-purpose register are set to the value of the data memory row address pointer only when a general-purpose register indirect transfer instruction is executed.
63 µ PD17062 Fig. 8-4 Indirect Transfer of General-Purpose Register with MPE = 1 and IXE = 0 Address generation of example 1 R M 0 0 0 0 0 0 0 3 1 0 1 5 4 8 (@ r) @ r, m MOV 05H 34H 01 2 3 45 6 7 89 .
64 µ PD17062 8.5.5 For MPE = 0 and IXE = 1 (Index Modification) As shown in Table 8-2, when a data memory manipulation instruction is executed, the bank and row address of the data memory specified directly by the instruction are ORed with the index register.
65 µ PD17062 Fig. 8-5 Data Memory Address Modification with IXE = 1 01 2 3 45 6 R 0 1 2 3 4 M ADD r, m Column address Row address General- purpose register Specified by IX.
66 µ PD17062 8.6 GENERAL-PURPOSE REGISTER POINTER (RP) The general-purpose register pointer points to the bank and row address of the general-purpose register. However, since RPH of the µ PD17062 is fixed at 0, only RPL (3 bits) can be specified. This means that 0 to 7 can be specified as a register pointer.
67 µ PD17062 9. REGISTER FILE (RF) The register file is a group of registers that mainly control the CPU peripheral circuits. The register file has a capacity of 128 words × 4 bits.
68 µ PD17062 Fig. 9-1 Configuration of Control Register (1/2) Note The number in parenthesis is the address used when the assembler (AS17K) is used. Column Address Row Address Item 0 1 2 3 4 5 6 7 0 .
69 µ PD17062 Fig. 9-1 Configuration of Control Register (2/2) 89 A B C D E F S I O 0 C H S B S I O 0 M S S I O 0 T X B T M 0 C K 0 0 I N T V S Y N I N T N C R/W R/W 0 I E G V S Y N I E G N C B T M 0 .
70 µ PD17062 Table 9-1 Peripheral Hardware Control Functions of Control Registers (1/5) Remark *: Retains the previous state. Peripheral hardware Control register Peripheral hardware control function.
71 µ PD17062 Table 9-1 Peripheral Hardware Control Functions of Control Registers (2/5) Remark *: Retains the previous state. Peripheral hardware Control register Peripheral hardware control function.
72 µ PD17062 Table 9-1 Peripheral Hardware Control Functions of Control Registers (3/5) Remark *: Retains the previous state. **: Indefinite Peripheral hardware Control register Peripheral hardware c.
73 µ PD17062 Table 9-1 Peripheral Hardware Control Functions of Control Registers (4/5) Remark *: Retains the previous state. **: Indefinite Peripheral hardware Control register Peripheral hardware c.
74 µ PD17062 Table 9-1 Peripheral Hardware Control Functions of Control Registers (5/5) Peripheral hardware Control register Peripheral hardware control function At reset Register Ad- dress Read/ wri.
75 µ PD17062 b 3 b 2 b 1 b 0 0 IDCDMAEN 00 00H 0 1 DMA prohibited mode (instruction cycle = 2 s) DMA mode (instruction cycle = 12 s) µ µ 9.1 IDCDMAEN (00H, b 1 ) This flag must be set to enable the operation of IDC. When the IDCDMAEN flag is set, the mode changes to DMA mode and IDC is enabled.
76 µ PD17062 9.3 CE (07H, b 0 ) CE is a flag for reading the CE pin level. The flag indicates 1 when a high level signal is input to the CE pin, or 0 when a low level signal is input.
77 µ PD17062 b 3 b 2 b 1 b 0 BTM0ZX BTM0CK2 BTM0CK0 09H BTM0CK1 0 1 0 0 0 0 0 1 01 0 01 1 10 0 10 1 11 0 11 1 TIMER INT TIMER CARRY 5 ms 100 ms 20 ms 20 ms 5 ms 5/f TMR s 5 ms 6/f TMR s 100 ms 5 ms 1.
78 µ PD17062 9.7 INTNC (0FH, b 0 ) The INT NC flag is used for reading the INT NC pin state. The flag indicates 1 when a high level signal is input to the INT NC pin, and 0 when a low level signal is input to the INT NC pin.
79 µ PD17062 9.9 PLL REFERENCE MODE SELECTION REGISTER (13H) 9.10 SETTING OF INT NC PIN ACCEPTANCE PULSE WIDTH (15H) b 3 b 2 b 1 b 0 PLLRFCK3 PLLRFCK2 PLLRFCK0 13H PLLRFCK1 00 10 00 11 01 10 11 11 01 11 10 10 10 11 11 10 6.
80 µ PD17062 9.11 TIMER CARRY (17H) 9.12 SERIAL INTERFACE WAIT CONTROL (18H) 9.13 IEGNC (1FH) The IEGNC flag is used for selecting the interrupt detection edge of the INT NC pin and V SYNC pin. When the flag is set to 0, an interrupt occurs at a rising edge.
81 µ PD17062 b 3 b 2 b 1 b 0 ADCCH2 ADCCH1 ADCCMP 21H ADCCH0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 0 1 ADC 0 select ADC 1 select, shared with P1C 3 ADC 2 select, shared with P0D 0 ADC 3 select,.
82 µ PD17062 9.16 PORT1C I/O SETTING (27H) 9.17 SERIAL I/O0 STATUS REGISTER (28H) b 3 b 2 b 1 b 0 SIO0SF8 SIO0SF9 SBBSY 28H 0 1 SBSTT Busy condition detection 0 1 Start condition detection 0 1 9 cloc.
83 µ PD17062 9.18 INTERRUPT PERMISSION FLAG (2FH) This flag is used to enable interrupt for each interrupt cause. When the flag is set to 1, interrupt is enabled.
84 µ PD17062 9.20 IDCEN (31H) 9.21 PLL UNLOCK FLIP-FLOP DELAY CONTROL REGISTER (32H) b 3 b 2 b 1 b 0 0 0 IDCEN 31H 0 1 0 IDC operation prohibited (display off) IDC operation start (display on) b 3 b 2 b 1 b 0 PLULSEN3 32H 0 0 1 1 0 1 0 1 PLULSEN2 PLULSEN1 PLULSEN0 1.
85 µ PD17062 9.22 P1BBIOn (35H) P1BBIOn specifies the PORT1B I/O. When P1BBIOn is set to 0, PORT1B becomes an input port. When P1BBIOn is set to 1, PORT1B becomes an output port. 9.23 P0BBIOn (36H) P0BBIOn specifies the PORT0B I/O. When P0BBIOn is set to 0, PORT0B becomes an input port.
86 µ PD17062 9.24 P0ABIOn (37H) P0ABIOn specifies the PORT0A I/O. When P0ABIOn is set to 0, PORT0A becomes an input port. When P0ABIOn is set to 1, PORT0A becomes an output port.
87 µ PD17062 9.26 SHIFT CLOCK FREQUENCY SETTING (39H) 9.27 IRQNC (3FH) IRQNC is an interrupt request flag that indicates the interrupt request state. When an interrupt request is generated, the flag is set to 1. When the request is accepted (interrupt is made), the flag is reset to 0.
88 µ PD17062 10. DATA BUFFER (DBF) The data buffer is used to transfer data to and from peripheral hardware and to reference tables. 10.1 DATA BUFFER STRUCTURE 10.1.1 Mapping of Data Buffer to Data Memory Fig. 10-1 shows how the data buffer is mapped to data memory.
89 µ PD17062 10.1.2 Data Buffer Structure Fig. 10-2 shows the data buffer structure. As shown in Fig. 10-2, the data buffer consists of 16 bits. Bit b 0 of data memory address 0FH is the LSB, and bit b 3 of data memory address 0CH bit 3 is the MSB. Fig.
90 µ PD17062 10.2 FUNCTIONS OF DATA BUFFER The data buffer provides the following two functions: (1) Read constant data in program memory (to reference tables) (2) Transfer data to and from peripheral hardware Fig. 10-3 shows the relationship between the data buffer, peripheral hardware, and memory.
91 µ PD17062 10.3 DATA BUFFER AND TABLE REFERENCING 10.3.1 Table Referencing Tables are referenced by reading the constant data from program memory into the data buffer.
92 µ PD17062 10.3.2 Example Table Referencing Program This section shows an example table referencing program. Example P0A MEM 0.70H ; P0B MEM 0.71H ; P0C MEM 0.
93 µ PD17062 This program sequentially reads the constant data stored at program memory addresses 0001H to 000CH into the data buffer ( ) and outputs the data to Port0A, Port0B, and Port0C ( ). The constant data is left-shifted one bit. As a result, a high-level data is sequentially output to the Port0A, Port0B, and Port0C pins.
94 µ PD17062 Table 10-1 Peripheral Hardware and Data Buffer Functions Data buffer and data transfer Function peripheral register Peripheral hardware Name Symbol Peri- PUT Data Valid Explanation phera.
95 µ PD17062 10.4.2 Precautions When Transferring Data With Peripheral Registers Data is transferred between the data buffer and peripheral registers in 8-bit or 16-bit units. A PUT or GET instruction is executed for one instruction cycle (2 µ s) even if the data is 16 bits long.
96 µ PD17062 Example 2. GET instruction When the 8-bit data of a peripheral register is read, the value of the eight high-order bits (DBF3 and DBF2) of the data register does not change. Of the 8-bit data of the data register, each bit that is not a valid peripheral register bit becomes 0 or unpredictable.
97 µ PD17062 10.5 Data Buffer and Peripheral Registers Sections 10.5.1 to 10.5.7 describe the data buffer and the peripheral registers. 10.5.1 IDC Start Position Setting Register Fig. 10-4 shows the functions of the IDC start position setting register.
98 µ PD17062 10.5.2 A/D Converter Data Register Fig. 10-5 shows the functions of the A/D converter data register. The A/D converter data register sets the A/D converter comparison voltage. Because the A/D converter is a 4-bit converter, the four low-order bits of the A/D converter data register are valid.
99 µ PD17062 10.5.3 Presettable Shift Register Fig. 10.6 shows the functions of the presettable shift register. The presettable shift register writes the serial interface serial out data and reads the serial interface serial in data.
100 µ PD17062 10.5.4 HSYNC Counter Data Register Fig. 10.7 shows how the HSYNC counter data register functions . The HSYNC counter data register reads the horizontal synchronizing signal count. When the HSYNC counter data register reaches 3FH, it returns to 00H at the next input.
101 µ PD17062 10.5.5 PWM Data Register Fig. 10-8 shows how the PWM data register functions. The PWM data register sets the duty cycle of the 6-bit D/A converter (PWM output) output. The 6-bit D/A converter has four channels (pins PWM 3 , PWM 2 , PWM 1 , and PWM 0 ).
102 µ PD17062 10.5.6 Address Registers The address registers are mapped to addresses 74H to 77H in the system register (at data memory addresses 74H to 7FH). They are used for program memory address operations. See Chapter 8 . The address registers can be used to manipulate data directly with data memory operation instructions.
103 µ PD17062 10.5.7 PLL Data Register Fig. 10-10 shows how the PLL data register functions. The PLL data register sets the frequency division ratio of the PLL frequency synthesizer.
104 µ PD17062 10.6 PRECAUTIONS WHEN USING DATA BUFFERS 10.6.1 Write Only, Read Only, and Unused Address Data Buffer Precautions When the 17K series assembler and emulator are used for data transfer w.
105 µ PD17062 10.6.2 Peripheral Register Addresses and Reserved Words When a 17K series assembler is used, no error is generated when peripheral address “p” is specified directly (with a numerical value) in PUT p, DBF or GET DBF, p as shown in Example 1.
106 µ PD17062 11. INTERRUPT An interrupt temporarily stops the program being executed in response to a request from the peripheral hardware (INT NC pin, timer, V SYNC pin or serial interface). The interrupt then branches the program flow to a predetermined address (vector address).
107 µ PD17062 Fig. 11-1 Interrupt Block Configuration 3FH 2FH b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 I R Q S I O 0 I R Q V S Y N I R Q B T M 0 I R Q N C I P S I O 0 I R V S Y N I P B T M 0 I P N C 01H b 3 b.
108 µ PD17062 11.2 INTERRUPT FUNCTION The following peripheral hardware can use the interrupt function: the INT NC pin, timer, V SYNC pin, and serial interface.
109 µ PD17062 11.2.4 Interrupt Permission Flags (IP ××× ) The interrupt permission flags set interrupt permissions for various types of peripheral hardware. If these flags are set to 1 and the corresponding interrupt request flags are also set, the corresponding interrupt requests are output.
110 µ PD17062 11.2.6 Interrupt Enable Flip-Flop (INTE) The interrupt enable flip-flop sets the interrupt permissions of all four types of interrupts. If each interrupt request processing block outputs a 1 while this flip-flop is set to 1, a 1 is output from this flip-flop and an interrupt is accepted.
111 µ PD17062 11.3 INTERRUPT ACCEPTANCE 11.3.1 Interrupt Acceptance and Priority An interrupt is accepted as follows: (1) When the interrupt conditions are satisfied (e.g., a rising edge is input to the INT NC pin), each type of peripheral hardware outputs the interrupt request signal to the interrupt request blocks.
112 µ PD17062 Fig. 11-2 Interrupt Acceptance Flowchart START INT NC pin Timer V SYNC pin Serial interface IPNC=1? IPBTM0=1? IPVSYN=1? IPSIO0=1? No Yes No Yes No Yes No yes Yes No Yes No Yes No IRQNC=.
113 µ PD17062 11.3.2 Timing Chart at Interrupt Acceptance Fig. 11-3 shows the timing chart at interrupt acceptance. Fig. 11-3 (1) shows the timing chart of one interrupt. The timing chart when an interrupt request flag is set to 1 is shown in (a) of (1).
114 µ PD17062 Fig. 11-3 Interrupt Reception Timing Chart (1/2) (1) When one interrupt (e.g., rising edge at the INT NC pin) is used (a) When an interrupt mask time is not set by the interrupt permiss.
115 µ PD17062 Fig. 11-3 Interrupt Acceptance Timing Chart (2) When two or more interrupts (e.g., rising edge at the INT NC pin and falling edge at the V SYNC pin) are used (a) Hardware priorities (b).
116 µ PD17062 11.4 OPERATIONS AFTER INTERRUPT ACCEPTANCE When an interrupt is accepted, the following processing sequence is executed: (1) The interrupt enable flip-flop or interrupt request flag corresponding to the accepted interrupt is reset. In other words, a write protected state is set.
117 µ PD17062 11.6 INTERRUPT PROCESSING ROUTINE An interrupt is accepted in a program area that permits interrupts regardless of the program being executed. Therefore, to return control to the original program after interrupt processing, return the program to the state it is in when it is not processing an interrupt.
118 µ PD17062 11.6.3 Notes on Interrupt Processing Routine Note the following regarding the interrupt processing routine: (1) Data saved by hardware All bank registers and index enable flags are reset to 0 after being saved in the interrupt stack. (2) Data saved by software Data saved by software is not reset after being saved.
119 µ PD17062 Example Saving the status in an interrupt processing routine EI M046 M047 M048 M04D M04E M05F BTM0CK MEM MEM MEM MEM MEM MEM MEM 0.46H 0.47H 0.48H 0.4DH 0.4EH 0.5FH 0.89H POKE PEEK POKE MOV ST ST M048, WR, M04E, RPL, M046, M047, WR RPL WR #0EH AR1 AR0 .
120 µ PD17062 Fig. 11-4 Saving the System or Control Register Using the Window Register Numbers to correspond to the numbers in the program example. 0123456789ABCDEF 0 1 2 3 4 5 6 7 BANK0 POKE M048, .
121 µ PD17062 11.7 EXTERNAL INTERRUPTS (INT NC PIN, V SYNC PIN) There are two external interrupt sources: INT NC and V SYNC . An interrupt request is issued when a rising or falling edge is input to the INT NC or V SYNC pin. 11.7.1 Configuration Fig.
122 µ PD17062 11.7.2 Functions An interrupt can be issued when either a rising or falling edge is input to the INT NC or V SYNC pin. Use the IEGNC or IEGVSYN flag in the interrupt edge select register of the control register to select the rising or falling edge.
123 µ PD17062 IEGNC or IEGVSYN flag change INT NC or V SYNC pin Whether interrupt IRQNC flag request is issued 1 → 0 Low Not issued No change (Fall) (Rise) High Issued Set 1 → 0 Low Issued Set (Rise) (Fall) High Not issued No change Table 11-3 Interrupt Request Issuance by IEGNC Flag Change 11.
124 µ PD17062 11.9 MULTIPLE INTERRUPTS The multiple interrupt function is used to process interrupt C or D while another interrupt from source A or B is being processed as shown in Fig. 11-6. The interrupt depth at this time is called the interrupt level.
125 µ PD17062 11.9.1 Interrupt Source Priorities When using the multiple interrupt function, the priorities of interrupt sources must be determined. For example, if the interrupt sources are A, B, C, and D, the following priorities can be specified: A = B = C = D or A < B < C < D.
126 µ PD17062 For multiple interrupts of more than two levels, operations of the device and emulator differ as shown in Figs. 11-8 and 11-9. At interrupt stack, the device operation is the sweep-off type and the emulator operation is the rotation type.
127 µ PD17062 Fig. 11-7 Interrupt Stack Operation at Multiple Interrupts (a) Multiple level-2 interrupts (b) Multiple level-3 interrupts MAIN A MAIN B A MAIN RETI RETI A MAIN MAIN MAIN MAIN MAIN Inte.
128 µ PD17062 MAIN A MAIN B A C B A MAIN B A A A RETI RETI RET A A A A BANK0 CLR1 IXE DI BANK0 CLR1 IXE EI Undefined Undefined Main routine Interrupt A Interrupt B Interrupt C Undefined Fig. 11-8 Example of Using Multiple Level-3 Interrupts To interrupt A, be sure to set a lower priority than interrupts B and C.
129 µ PD17062 Fig. 11-9 Interrupt Stack Operation when 17K Series Emulator is Used If the RETI instruction is used on the emulator, the contents of the bank register and index enable flag of interrupt B are restored.
130 µ PD17062 11.9.3 Interrupt Level Restriction by Address Stack Register The return address at control return from interrupt processing is automatically saved in the address stack register. The address stack register can use the six levels from ASR0 to ASR5 as described in Chapter 4 .
131 µ PD17062 11.9.4 Saving the Contents of System and Control Registers The contents of system and control registers must be saved before using the multiple interrupt function. The contents of these registers change during interrupt processing. An area must be obtained for these contents for each interrupt source.
132 µ PD17062 In , specify the data memory bank containing the contents of the system register. Because the bank becomes BANK0 when an interrupt is accepted, if the data is saved in BANK0, this instruction is not necessary. In , save the contents of the window register in data memory M1.
133 µ PD17062 12. TIMER The timer functions are used to manage the time in creating programs. 12.1 TIMER CONFIGURATION Fig. 12-1 shows the configuration of the timer. The timer consists of two blocks, timer carry flip-flop (timer carry FF) block and timer interrupt block, as shown in Fig.
134 µ PD17062 12.2 TIMER FUNCTIONS There are two timer functions, timer carry FF check and timer interrupt. The timer carry FF check function performs time management by checking, by program, the state of the timer carry FF, which is set at constant intervals.
135 µ PD17062 Fig. 12-2 Relationship Between the Timer Mode Select Register and Timer Interval Set Pulse b 3 b 2 b 1 b 0 B T M 0 Z X B T M 0 C K 2 B T M 0 C K 1 B T M 0 C K 0 09H R/W Read/Write 000 0.
136 µ PD17062 12.3 TIMER CARRY FLIP-FLOP (TIMER CARRY FF) The timer carry FF is set to 1 by the positive-going edge of the timer carry FF set pulse specified by the timer mode select register.
137 µ PD17062 12.3.1 Example of Using the Timer Based on the BTM0CY Flag An example of a program follows. Example INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, NOT BTM0CK0 ; Built-in macro ; Specifies that the timer carry FF be set at intervals of 100 ms.
138 µ PD17062 12.3.2 Timer Error Caused by the BTM0CY Flag There are two types of timer error that can occur because of the BTM0CY flag. One type depends on the timing when the BTM0CY flag is checked, and the other type occurs when the timer carry FF setting interval is changed.
139 µ PD17062 (2) Timer error that occurs when the timer carry FF setting time interval is changed The timer carry FF setting time interval is specified by the BTM0CK2, BTM0CK1, and BTM0CK0 flags in the timer mode select register.
140 µ PD17062 As shown in Fig. 12-5, if the timer carry FF setting time interval is switched, the timer error that occurs before the BTM0CY flag is set for the first time is as follows: -t SET < e.
141 µ PD17062 12.4 CAUTIONS IN USING THE TIMER CARRY FF The timer carry FF is used not only as a timer function but also as a reset sync signal at a CE reset. A CE rest occurs when the timer carry FF set pulse rises after the CE pin goes from a low to a high.
142 µ PD17062 12.4.1 Timer Update Time and BTM0CY Flag Check Time Interval As described in Section 12.3.1 , the time interval t SET at which the BTM0CY flag is checked must be less than the time interval at which the timer carry FF is set.
143 µ PD17062 12.4.2 Correcting the Timer Carry FF at a CE reset This section describes an example of correcting the timer at a CE reset. If the timer carry FF is used both to check for power failure and as a timer, it is necessary to correct the timer at a CE reset, as explained in the following example.
144 µ PD17062 Fig. 12-6 Timing Chart As shown in Fig. 12-6, the positive-going edge of the internal 10 Hz pulse starts the program at 000H at a power-on reset. When the BTM0CY flag is checked at point A, it appears to be reset to 0, thus indicating a power-on reset, because it is just after the power is turned on.
145 µ PD17062 12.4.3 If the BTM0CY flag is checked at the same time with a CE reset As described in Section 12.4.2 , a CE reset occurs at the same time the BTM0CY flag is set to 1. If the BTM0CY flag read instruction happens to occur at the same time a CE reset occurs, the BTM0CY flag read instruction takes precedence.
146 µ PD17062 The program shown below is an example of a program that meets the above condition. Do not creates such a program. Example Process A INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, BTM0CK0 ; Built-in macro ; Specifies the timer carry FF set pulse as 5 ms.
147 µ PD17062 12.5 TIMER INTERRUPT The timer interrupt function issues an interrupt request at the negative-going edge of the timer interrupt pulse specified in the timer mode select register. The timer interrupt request corresponds to the IRQBTM0 flag in the interrupt request register on a one-to- one basis.
148 µ PD17062 12.5.1 Example of Using a Timer Based on a Timer Interrupt An example follows. Example BR AAA ; Branches to AAA. TIMER: ; Program address 0003H ADD M1, #0001B ; Add 1 to M1. SKT1 CY ; Tests the CY flag. BR BBB ; Returns if no carry is generated.
149 µ PD17062 12.5.2 Timer Interrupt Error As explained in Section 12.4 , an interrupt request is accepted each time the timer interrupt pulse goes low, provided that the interrupt is enabled. A timer error due to use of a timer interrupt occurs when: (1) An interrupt request is accepted for the first time after the timer interrupt is enabled.
150 µ PD17062 Fig. 12-9 Timer Interrupt Error (2/2) (b) When the timer interrupt pulse is switched EI EI EI EI IRQBTM0 IPBTM0 INTE FF EI DI Internal pulse A Internal pulse B Timer interrupt pulse Int.
151 µ PD17062 12.6 CAUTIONS IN USING THE TIMER INTERRUPT In a program using a timer that operates at constant intervals once a power-on reset occurs, it is necessary to have the timer interrupt handling routine finish within that constant interval. This is explained using an example.
152 µ PD17062 In reality, however, to avoid skipping the timer process in the above example, a delay is provided between the negative-going edge of the timer carry FF set pulse and the negative-going edge of the timer interrupt pulse, as shown in Fig.
153 µ PD17062 13. STANDBY The standby function is intended to reduce the current drain of the device at backup. 13.1 STANDBY BLOCK CONFIGURATION Fig. 13-1 shows the configuration of the standby block. As shown in Fig. 13-1, the standby block is further divided into halt control and clock stop control blocks.
154 µ PD17062 13.2 STANDBY FUNCTION The standby function stops the whole or part of the operation of the device to reduce its current drain. The standby function is divided into halt and clock stop functions. The halt function uses a dedicated instruction (HALT h instruction) to stop the CPU in order to reduce the required current drain.
155 µ PD17062 13.3 DEVICE OPERATION MODE SPECIFIED AT THE CE PIN The CE pin controls the following items according to the level and positive-going edge of its input signal. (1) Whether to enable or disable the clock stop instruction (2) Whether to reset the device Sections 13.
156 µ PD17062 13.4 HALT FUNCTION The halt function stops the operation of the CPU clock by executing the HALT h instruction. When the HALT h instruction is executed, the program stops at this instruction and rests there until the halt state is released.
157 µ PD17062 13.4.2 Halt Release Conditions Fig. 13-3 summarizes the release conditions. As shown in Fig. 13-3, the halt release condition is 4-bit data specified in the operand h of the HALT h instruction. The halt state is released when a condition specified as 1 in the operand h is satisfied.
158 µ PD17062 13.4.3 Halt Release by Key Entry The HALT 0001B instruction specifies a key entry as a halt release condition. If this condition is specified, the halt state is released when a high level is applied to one of the P0D 0 /ADC 2 to P0D 3 /ADC 5 pins.
159 µ PD17062 (2) Cautions in using the P0D 0 /ADC 2 to P0D 3 /ADC 5 pins for an A/D converter P0D 3 /ADC 5 P0D 2 /ADC 4 P0D 1 /ADC 3 P0D 0 /ADC 2 A/D input A/D input Latch General-purpose port If on.
160 µ PD17062 (3) Alternative method to release the halt state P0D 3 /ADC 5 P0D 2 /ADC 4 P0D 1 /ADC 3 P0D 0 /ADC 2 Output port Latch Microprocessor or the like General-purpose output port The P0D 0 /ADC 2 to P0D 3 /ADC 5 pins can be used a general-purpose input port with a built-in pull-down resistor.
161 µ PD17062 13.4.4 Releasing the Halt State by the Timer Carry FF The HALT 0010B instruction specifies the timer carry FF as a halt release condition. If it is specified that the halt state is to be released according to the timer carry FF, the halt state is released immediately when the timer carry FF is set to 1.
162 µ PD17062 13.4.5 Releasing the Halt State by an Interrupt The HALT 1000B instruction specifies an interrupt as halt release condition. If it is specified that the halt state is to be released according to an interrupt, the halt state is released immediately when an interrupt request is accepted.
163 µ PD17062 Example HLTINT DAT 1000B ; Defines a symbol. START: ; Address 0000H BR MAIN ; NOP INTTM: ; Timer interrupt vector address (0003H) BR INTTIMER ; Branches to INTTIMER (interrupt handling).
164 µ PD17062 13.5 CLOCK STOP FUNCTION The clock stop function stops the operation of the 8 MHz crystal oscillator by executing the STOP s instruction. The clock stop function can reduce the current drain of the µ PD17062 by 10 µ A (maximum). The operand s of the STOP s instruction is 0000B.
165 µ PD17062 Fig. 13-4 Releasing the Clock Stop State by a CE Reset Fig. 13-5 Releasing the Clock Stop State by a Power-on Reset 5 V 0 V V DD CE pin Crystal oscillation (X OUT pin) STOP 0 instruction Approx.
166 µ PD17062 13.5.3 Cautions in Using the Clock Stop Instruction The clock stop instruction (STOP s) is effective only when the CE pin is at a low level. To enable the clock stop state to be released, the program must therefore have a provision to handle when the CE pin happens to be at a high.
167 µ PD17062 13.6 OPERATION OF THE DEVICE AT A HALT OR CLOCK STOP 13.6.1 State of Each Pin at a Halt and Clock Stop Table 13-1 summarizes how the CPU and peripheral hardware behave during the halt or clock stop state.
168 µ PD17062 Stops at the address of the HALT instruction. Holds the previous state. Holds the previous state. Holds the previous state. Operates normally. Operates normally. Operates normally. Stops operating. Operates normally. Operates normally. Operates normally.
169 µ PD17062 13.6.2 Cautions in Processing of Each Pin During Halt or Clock Stop State The halt function is intended to reduce the required current drain, for example, by allowing only the clock to operate.
170 µ PD17062 Table 13-2 State of Each Pin During the Halt or Clock Stop State and Cautions to Be Taken (2/2) INT NC RED GREEN BLUE BLANK H SYNC V SYNC PWM 3 PWM 2 PWM 1 PWM 0 ADC 0 X IN X OUT Clock .
171 µ PD17062 14. RESET The reset function is used to initialize device operation. 14.1 RESET BLOCK CONFIGURATION Fig. 14-1 shows the configuration of the reset block. Device reset is divided into reset by turning on V DD (power-on reset or V DD reset), and reset by CE pin (CE reset).
172 µ PD17062 14.2 RESET FUNCTION Power-on reset is applied when V DD rises from a certain voltage, CE reset is applied when the CE pin rises from low level to high level. Power-on reset initializes the program counter, stack, system register and control registers, and executes the program from address 0000H.
173 µ PD17062 14.3 CE RESET CE reset is executed by raising the CE pin from low level to high level. When the CE pin rises to high level, the RESET signal is output and the device is reset in synchronization with the rising edge of the pulse used for the next setting of the timer carry FF.
174 µ PD17062 14.3.2 CE Reset When Clock-Stop (STOP Instruction) Used Fig. 14-3 shows the reset operation. When clock-stop is used, the IRES, RES and RESET signals are output at the time the STOP instruction is executed.
175 µ PD17062 14.3.3 Cautions at CE Reset When CE reset is used, careful attention must be given to points (1) and (2) below regardless of the instruction being executed.
176 µ PD17062 Example 2. ; SKT1 FLG1 ; If FLG1 is set to 1, BR LCTUNE ST M1, R1 ; data is rewritten to M1 and M2 again. ST M2, R2 CLR1 FLG1 ; LCTUNE : Initial reception ; The last channel is received. The channel indicated by the contents of M1 and M2 is received.
177 µ PD17062 14.4 POWER-ON RESET Power-on reset is executed by raising V DD from a certain voltage (called the power-on clear voltage) or less. When V DD is less than the power-on clear voltage, the power-on clear signal (POC) is output from the voltage detection circuit shown in Fig.
178 µ PD17062 14.4.1 Power-on Reset at Normal Operation Fig. 14-5 (a) shows power-on reset at normal operation. As shown in Fig. 14-5 (a), when the V DD drops below 3.5 V, the power-on clear signal is output and operation of the device stops regardless of the input level of the CE pin.
179 µ PD17062 Fig. 14-5 Power-on Reset and V DD (a) During normal operation (including halt state) (b) At clock-stop (c) When V DD rises from 0 V 5 V 0 V “H” Normal operation Device operation sto.
180 µ PD17062 14.5 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET When supply voltage is first turned on, power-on reset and CE reset may be applied simultaneously. Sections 14.5.1 through 14.5.3 describe this reset operation. Section 14.5.4 describes the cautions when supply voltage rises.
181 µ PD17062 Fig. 14-6 Relationship Between Power-on Reset and CE Reset (a) When V DD and CE pin raised simultaneously (b) When CE pin raised in halt state (c) When CE pin raised after power-on reset 5 V 0 V Opera- tion stopped V DD CE Power-on reset Program start Power-on clear voltage 3.
182 µ PD17062 14.5.4 Cautions When Supply Voltage Raised When supply voltage is raised, careful attention must be given to points (1) and (2) below. (1) When V DD raised from power-on clear voltage When V DD is raised, it must be raised to 3.5 V or greater, once.
183 µ PD17062 (2) At return from clock-stop state When returning from the back-up state when clock-stop is used to back-up supply voltage at 2.2 V, V DD must be raised to 3.5 V or greater within 50 ms after the CE pin becomes high level. As shown in Fig.
184 µ PD17062 14.6 POWER FAILURE DETECTION Power failure detection is used to judge whether the device is reset by turning on V DD or by the CE pin, as shown in Fig. 14-9. Since the contents of the data memory, output ports, etc. become “undefined” when V DD is turned on, they are initialized by power failure detection.
185 µ PD17062 Fig. 14-10 BTM0CY Flag State Transition V DD = L → 3.5 V CE = L CE = H CE = H → L STOP 0 BTM0CY = 0 CE = L → H CE = L → H CE = H → L CE = L → H CE = L → H STOP 0 BTM0CY = 1 CE = low CE = optional CE = high V DD = low Operation stopped Clock oscillation start Forced halt (approx.
186 µ PD17062 Fig. 14-11 BTM0CY Flag Operation (a) When BTM0CY flag not detected even once (neither SKT1 BTM0CY nor SKF1 BTM0CY executed) (b) When power failure detected with BTM0CY flag 5 V 0 V V DD CE Timer carry FF set pulse BTM0CY Fig.
187 µ PD17062 14.6.2 Cautions at Power Failure Detection with BTM0CY Flag When clock counting, etc. is performed with the BTM0CY flag, careful attention must be given to the following points. (1) Clock updating When writing a clock program by using the timer carry FF, the clock must be updated after a power failure.
188 µ PD17062 Example Sample program START: ; Program address 0000H ; Reset processing ; ; SKT1 BTM0CY ; Power failure detection BR INITIAL BACKUP: ; Clock updating BR MAIN INITIAL: ; Initialization ; INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, BTM0CK0 ; Built-in macro ; Sets timer carry FF set time to 5 ms.
189 µ PD17062 15. GENERAL-PURPOSE PORT A general-purpose port outputs a high level, low level, or floating signal to an external circuit and reads a high level or low level signal from an external circuit. 15.1 CONFIGURATION AND CLASSIFICATION OF GENERAL-PURPOSE PORT Fig.
190 µ PD17062 Table 15-1 Classification of General-Purpose Ports General-purpose ports Classification of general-purpose ports Target ports Data setting method I/O shared port Bit I/O Port0A Port reg.
191 µ PD17062 b 3 b 2 b 1 b 0 m n P P P P 3 2 1 0 Weight of port register bit Port register address (Examples: 70H = A, 71H = B, 72H = C, 73H = D) Port register bank "P" of port Port register Bank Address Bit 15.
192 µ PD17062 15.2.2 General-Purpose I/O Ports (P0A, P0B, P1B, P1C) The I/O of P0A is switched by the P0A bit I/O selection register (RF address 37H). The I/O of P0B is switched by the P0B bit I/O selection register (RF address 36H). The I/O of P1B is switched by the P1B bit I/O selection register (RF address 35H).
193 µ PD17062 Table 15-2 Relationship between Each Port (Pin) and Port Register Note Nothing is mapped to b 0 of 72H. When b 0 is read, 0 is always read.
194 µ PD17062 15.3 GENERAL-PURPOSE I/O PORTS (P0A, P0B, P1B, P1C) 15.3.1 Configuration of I/O Ports In the following, (1) to (3) explain the configuration of the I/O ports. (1) P0A (P0A 3 , P0A 2 pins) P0B (P0B 3 , P0B 2 , P0B 1 , P0B 0 pins) P1B (P1B 3 , P1B 2 , P1B 1 , P1B 0 pins) P1C (P1C 3 , P1C 2 , P1C 1 pins) (2) P0A (P0A 1 , P0A 0 pins) 15.
195 µ PD17062 15.3.3 Port0A Bit I/O Selection Register (P0ABIO) Port0B Bit I/O Selection Register (P0BBIO) Port1B Bit I/O Selection Register (P1BBIO) Port1C Group I/O Selection Register (P1CGPIO) The Port0A bit I/O selection register sets I/O for each pin of P0A.
196 µ PD17062 15.3.4 To Use an I/O Port (P0A, P0B, P1B, P1C) as an Input Port Select the pin to be used as an input port by using the I/O selection register of each port. P1C can be set to I/O in 3-bit (3-pin) units only. The pin specified as an input port enters floating (Hi-Z) status and waits for the input of an external signal.
197 µ PD17062 15.3.6 Notes on Using I/O Ports (P0A 1 and P0A 0 ) As shown in the example below, when pins P0A 1 and P0A 0 pins are used as output pins, the contents of the output latch may be overwritten.
198 µ PD17062 15.4 GENERAL-PURPOSE INPUT PORT (P0D) 15.4.1 Configuration The following explains the configuration of the input port. (1) P0D (P0D 3 , P0D 2 , P0D 1 , P0D 0 pins) 15.
199 µ PD17062 15.5 GENERAL-PURPOSE OUTPUT PORTS (P0C, P1A) 15.5.1 Configuration of Output Ports (P0C, P1A) (1) and (2), below, show the configuration of the output ports.
200 µ PD17062 15.5.2 Example of Using Output Ports (P0C, P1A) The output ports output the contents of the output latch from each pin. Output data can be set by executing an instruction, such as the MOV instruction, to write the contents of the port register for each pin.
201 µ PD17062 16. SERIAL INTERFACE The µ PD17062 has two sets of serial interface pins, channel 0 (CH0) and channel 1 (CH1), for exchanging data with an external unit.
202 µ PD17062 Table 16-2 CH0 Operation Modes Remark × : Don’t care Serial interface Port 0A I/O SDA pin SCL pin Operation mode mode register specification SB SIO0MS SIO0TX P0ABIO0 P0ABIO1 0 0 0 0 .
203 µ PD17062 Table 16-3 CH1 Operation Modes Remark × : Don’t care Serial interface Port 0A I/O SI pin SCK pin SO pin Operation mode mode register specification SB SIO0MS SIO0TX P0ABIO2 P0ABIO3 P0.
204 µ PD17062 16.1.1 SIO0CH The SIO0CH flag is used to select the channel of the serial interface. When the SIO0CH flag is set to 0, the serial interface hardware is connected to CH0. When the SIO0CH flag is set to 1, the serial interface hardware is connected to CH1.
205 µ PD17062 16.1.3 SIO0MS The SIO0MS flag specifies the serial interface clock to be used. When the SIO0MS flag is set to 0, the external clock is selected. When the SIO0MS flag is set to 1, the internal clock is selected. When the internal clock is selected, its frequency is set by the shift clock frequency register (RF: 39H).
206 µ PD17062 16.2 CLOCK COUNTER The clock counter is a wrap around counter that counts the clock of the shift clock pin (P0A 1 /SCL pin for CH0, P0A 2 /SCK pin for CH1) of the currently selected serial interface. The clock counter counts the shift clock from 1 to 9 repeatedly.
207 µ PD17062 16.3 STATUS REGISTER The status register is a four-bit read-only register that retains the start and stop states in two-wire bus mode and the contents of the current clock counter.
208 µ PD17062 16.3.4 SIO0SF8 (Serial I/O Shift 8 Clock) Flag The SIO0SF8 flag, mapped to b 3 of the status register, is set to 1 when the contents of the clock counter become 8. When the contents of the clock counter become 0 or 1, the SIO0SF8 flag is reset to 0.
209 µ PD17062 16.4 WAIT REGISTER The µ PD17062 can set a state in which the serial interface hardware does not operate, even if a shift clock is input.
210 µ PD17062 Table 16-8 Wait Timings (1) Slave operation wait in two-wire bus mode When the timing specified by SIO0WRQ1 and SIO0WRQ0 is set, the SCL pin is switched to output mode and a low level signal is output. If no-wait (SIO0WRQ1 = SIO0WRQ0 = 0) is specified, this operation is not performed.
211 µ PD17062 (2) Master operation wait in two-wire bus mode Master operation wait in two-wire bus mode incurs the interruption of transmission. In this mode, when the timing specified by SIO0WRQ1 and SIO0WRQ0 is set, the shift clock is fixed to the low level.
212 µ PD17062 16.4.2 SIO0NWT (Serial I/O No-Wait) Flag Writing appropriate data into the SIO0NWT flag can both release wait and execute forced wait. (1) Writing 0 into SIO0NWT In this case, forced wait is executed. In other words, the clock being supplied to the clock counter and presettable shift register is disabled.
213 µ PD17062 (2) For transmission in two-wire bus mode (SIO0TX = 1) In this case, the contents of an acknowledgement received from the receiver side are set in the SBACK flag. This means that the acknowledge state of the receiver side can be determined simply by reading the contents of the SBACK flag.
214 µ PD17062 16.5 PRESETTABLE SHIFT REGISTER (PSR) The presettable shift register is an 8-bit register. It outputs the contents of the most significant bit of the PSR to the serial data output pin (.
215 µ PD17062 16.6 SERIAL INTERFACE INTERRUPT SOURCE REGISTER (SIO0IMD) The interrupt source register (SIO0IMD) is a four-bit register that specifies when an interrupt is generated in the CPU during serial interface communication. The SIO0IMD register is mapped to address 38H of the register file.
216 µ PD17062 Bit position b 3 b 2 b 1 b 0 Flag name SIO0CK3 SIO0CK2 SIO0CK1 SIO0CK0 (0) (0) SIO0CK1 SIO0CK0 Internal clock frequency 0 0 100 kHz 0 1 200 kHz 1 0 500 kHz 1 1 1 MHz 16.
217 µ PD17062 Peripheral equipment Peripheral address Corresponding pin PWM0 05H PWM 0 PWM1 06H PWM 1 PWM2 07H PWM 2 PWM3 08H PWM 3 17. D/A CONVERTER 17.1 PWM PINS The µ PD17062 has 4 output pins for 6-bit PWM, which enables varying the duty cycle of the 15.
218 µ PD17062 Fig. 17-1 PWMR Structure and the Corresponding DBF Bits Fig. 17-2 Waveform Output from the PWM Pin b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 PWMR DBF1 (0EH) DBF0 (0FH) The PWM pin is used as a D/A converter. The PWM pin is used as a one-bit output port (through mode), which outputs the content of b 5 .
219 µ PD17062 18. PLL FREQUENCY SYNTHESIZER 18.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION Fig. 18-1 is a block diagram of the PLL frequency synthesizer. As shown in Fig. 18-1, the PLL frequency synthesizer consists of a programmable divider (PD), phase comparator ( φ -DET), reference frequency generator (RFG), and charge pump.
220 µ PD17062 18.2 OVERVIEW OF EACH PLL FREQUENCY SYNTHESIZER BLOCK The PLL frequency synthesizer receives an input signal at the VCO pin, divides its frequency in the programmable divider, and outputs the difference in phase between the divider output and the reference frequency from the EO pin.
221 µ PD17062 18.3 PROGRAMMABLE DIVIDER (PD) AND PLL MODE SELECT REGISTER 18.3.1 Programmable Divider Configuration Fig. 18-2 shows the configuration of the programmable divider (PD). As shown in Fig. 18-2, the programmable divider consists of a swallow counter and programmable counter.
222 µ PD17062 18.3.2 Programmable Divider (PD) and Data Buffer (DBF) The programmable divider divides the frequency of an input signal at the VCO pin by the values specified in the swallow counter and programmable counter. The swallow and programmable counters consist of a 4- and 12-bit binary downcounter, respectively.
223 µ PD17062 18.4 REFERENCE FREQUENCY GENERATOR (RFG) 18.4.1 Reference Frequency Generator (RFG) Configuration and Functions Fig. 18-3 shows the configuration of the reference frequency generator.
224 µ PD17062 18.4.2 PLL Reference Mode Select Register Configuration and Functions Fig. 18-4 shows the configuration and functions of the PLL reference mode select register. When the PLL reference mode select register selects the PLL disable mode, the VCO pin is pulled down internally, and the EO pin floats.
225 µ PD17062 18.5 PHASE COMPARATOR ( φ -DET), CHARGE PUMP, AND UNLOCK DETECTION BLOCK 18.5.1 Configuration of the Phase Comparator ( φ -DET), Charge Pump, and Unlock Detection Block Fig. 18-5 shows the configuration of the phase comparator ( φ -DET), charge pump, and unlock detection block.
226 µ PD17062 18.5.2 Functions of the Phase Comparator ( φ -DET) As shown in Fig. 18-5, the phase comparator compares the phase of the output frequency “f N ” of the programmable divider (PD) and the phase of the reference frequency “f r ”, and outputs the up request signal (UP) or down request signal (DW).
227 µ PD17062 Fig. 18-6 Relationship among f r , f N , UP, and DW Signals (1) When f N is lagging behind f r (2) When f N is leading f r (3) When f N is in phase with f r (4) When f N is lower than f.
228 µ PD17062 18.5.3 Charge Pump As shown in Fig. 18-5, the charge pump directs the up request signal (UP) or down request signal (DW) from the phase comparator ( φ -DET) to the error output pin (EO) pin.
229 µ PD17062 (1) PLL unlock FF judge register (PLLULJDG) This register is a read-only register. It is reset when its content is read into a window register (WR) with a PEEK instruction.
230 µ PD17062 (2) PLL unlock FF delay control register (PLULSEN) When the unlock FF disable mode is selected, the unlock FF remains set. So, note that if the PLL unlock FF judge register checks the unlock FF in the unlock FF disable mode, it always appears to be unlocked (PLLUL flag = 1).
231 µ PD17062 18.6 PLL DISABLE MODE The PLL frequency synthesizer is disabled when the CE pin is at a low level. It is also disabled when the PLL reference mode select register (PLRFMODE, at address 13H) selects the PLL disable mode. Table 18-1 summarizes how each block operates during the PLL disable mode.
232 µ PD17062 PLLR 0000 0110 1100 1111 06 C F PLRFMODE 0010 6.25 kHz 18.7 SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER The following data is necessary to control the PLL frequency synthesizer. (1) Reference frequency : f r (2) Division value : N The following paragraphs explain how to set the PLL data.
233 µ PD17062 19. A/D CONVERTER The µ PD17062 contains a 4-bit program-controlled A/D converter that operates with a successive compari- son method. 19.1 PRINCIPLE OF OPERATION The A/D converter in the µ PD17062 consists of a 4-bit resistor string-based D/A converter and comparator.
234 µ PD17062 19.2 D/A CONVERTER CONFIGURATION The D/A converter used in the A/D converter of the µ PD17062 is a resistor string D/A converter consisting of 16 resistors connected in series between the V DD and GND pins in which a voltage at each resistor connection point is selected.
235 µ PD17062 19.3 REFERENCE VOLTAGE SETTING REGISTER (ADCR) The ADCR is a 4-bit register to specify a reference voltage for the A/D converter. It is mapped at peripheral address 02H. Data is written to and read from the ADCR register through the data buffer using the “PUT” and “GET” instructions respectively.
236 µ PD17062 b 3 b 2 b 1 #0 (MSB) (LSB) (RF : 21H) ADCCMP ADCCH2 ADCCH1 ADCCH0 Selected pin 0 0 0 ADC 0 0 0 1 P1C 3 /ADC 1 0 1 0 P0D 0 /ADC 2 0 1 1 P0D 1 /ADC 3 1 0 0 P0D 2 /ADC 4 1 0 1 P0D 3 /ADC 5 11 0 No corresponding pin (do not set) 11 1 19.5 ADC PIN SELECT REGISTER (ADCCHn) The ADCCHn register selects an A/D converter input pin.
237 µ PD17062 19.6 EXAMPLE OF A/D CONVERSION PROGRAM The following example shows an A/D conversion program based on the successive comparison method. The result of conversion is held in the DBF0. Sample program DBF0B3 FLG 0.0FH.3 DBF0B2 FLG 0.0FH.2 DBF0B1 FLG 0.
238 µ PD17062 Flowchart START DBF ← 1000B ADCR ← DBF ADCCMP DBF0B3 ← 0 DBF0B2 ← 1 ADCR ← DBF ADCCMP 1 0 1 0 DBF0B2 ← 0 DBF0B1 ← 1 1 Sets DBF data. Begins AD conversion. Judges comparison result. DBF0B3 ← 0 DBF0B2 ← 1 Judges comparison result.
239 µ PD17062 END ADCR ← DBF ADCCMP DBF0B1 ← 0 DBF0B0 ← 1 ADCR ← DBF ADCCMP 1 0 1 0 DBF0B0 ← 0 DBF0B0 ← 0 DBF0B1 ← 0 DBF0B0 ← 1 1 Sets reference voltage.
240 µ PD17062 TV screen 19 characters 14 rows 20. IMAGE DISPLAY CONTROLLER The image display controller (IDC) function indicates a channel number, volume of sound, time, and other information on a TV screen. The pattern of a display is user-programmable, and the display pattern definition is stored in the CROM area.
241 µ PD17062 (4) Rounding, rimming, and reverse video can be specified for individual characters. (5) Number of fonts: 120 (user-programmable) The number of fonts that can be displayed on one screen simultaneously is limited to within 64.
242 µ PD17062 (6) Up to 4 different character sizes, both vertical and horizontal, are available. The same vertical character size is specified for all characters in a row, while the horizontal character size is specified for individual characters (according to the control data Note 1 ).
243 µ PD17062 20.2 DIRECT MEMORY ACCESS The direct memory access (DMA) function transfers memory contents directly to peripheral equipment, without using the CPU. In the µ PD17062, the DMA mode is used to run the IDC. The instruction cycle of the µ PD17062 is 2 µ s, but its apparent instruction cycle becomes 12 µ s during the DMA mode.
244 µ PD17062 Sample program Remark The “SET1” or “CLR1” is not included in the µ PD17062 instruction set. They are a built-in macro instruction of the 17K series assembler. They set or reset a one-bit flag. If they are written in a source program as shown at *1, they are expanded during assembly as shown at *2.
245 µ PD17062 b 3 b 2 b 1 b 0 0 0 IDCEN 0 1 0 Turns off the display. Turns on the display. (RF 31H) ------ ------ 20.3 IDC ENABLE FLAG The IDCEN (IDC enable) flag is manipulated to start IDC operations (turn on the display). The flag is mapped at the lowest bit (#0) of the register file at 31H.
246 µ PD17062 20.4 VRAM VRAM is the memory that holds data used to select a picture pattern that the IDC displays on a screen such as a TV screen. In the µ PD17062, the VRAM data is allocated at BANK1 and BANK2 in data memory. One VRAM data item (8 bits) is held at two adjoining addresses (even and odd address).
247 µ PD17062 Fig. 20-2 VRAM Data Configuration 20.4.1 ID Field The ID field indicates the type of data in the data field. The data field can hold the following three types of data. (1) Character pattern select data (2) Carriage return data (3) Control data select data Table 20-3 ID Field 20.
248 µ PD17062 Table 20-4 VRAM Data (Character Pattern Select Data) versus CROM Addresses VRAM data CROM address VRAM data CROM address (8 bits) BANK0 BANK1 (8 bits) BANK0 BANK1 00H 0800H-080EH 0C00H-.
249 µ PD17062 Sample program If the CROM data and VRAM data are specified as shown above, the display on the screen varies depending on the CROM bank. The CROM bank is specified by CROMBNK (b 0 at 30H). The following description applies to the above example.
250 µ PD17062 20.4.3 Carriage Return Data The term carriage return data refers to the data pointing to the address of the VRAM data that specifies the first character in a row on the screen. The carriage return data specifies the end of a display row.
251 µ PD17062 Fig. 20-4 Carriage Return Data (8 Bits Including the ID Field) 0 123 4 567 8 9A B C D EF 40 41 42 43 44 45 46 47 0 48 49 4A 4B 4C 4D 4E 4F 1 50 51 52 53 54 55 56 57 2 58 59 5A 5B 5C 5D .
252 µ PD17062 20.4.4 Control Data Select Data The term control data refers to the data that specifies the character size, display position, and color of a character pattern on the screen. This data is held in CROM (at ××× FH). The control data select data is held in VRAM and selects control data in CROM.
253 µ PD17062 Table 20-5 VRAM Data (Control Data Select Data) versus CROM Addresses VRAM data CROM address VRAM data CROM address (8 bits) BANK0 BANK1 (8 bits) BANK0 BANK1 80H 080FH 0C0FH A0H 0A0FH 0.
254 µ PD17062 20.4.5 Cautions in Specifying VRAM Data (1) Reset the IDCEN flag to 0 before specifying VRAM data. (2) The VRAM data must begin at 00H in BANK1. (3) Do not set VRAM data at 7 × H in BANK1 or BANK2. (4) Always set control data at the beginning of a screen.
255 µ PD17062 20.5 CHARACTER ROM The CROM (character ROM) consists of the IDC pattern data and control data. The CROM data shares the program memory with programs. The CROM area has a capacity of 2 Ksteps (1920 × 16 bits). An area not used as CROM is used as an ordinary program area.
256 µ PD17062 Fig. 20-6 Character Pattern Data Configuration (a) Data for a character with no rimming (b) Data for a character with rimming If 2 is to be displayed, the character pattern is set as shown in Fig. 20-7. 0 and 1 in the pattern data correspond to ■ ■ and ■ , respectively.
257 µ PD17062 Fig. 20-8 Example of the Pattern of a Character with Rimming ×××× 0H ×××× 1H ×××× 2H ×××× 3H ×××× 4H ×××× 5H ×××× 6H ×××× 7H ×××× 8H ×××× 9H ××.
258 µ PD17062 20.5.2 Control Data The control data specifies the display position, size, and color of a character pattern. It is stored at ××× FH in the CROM area. One control data item consists of 16 bits. The highest bit is always 0. Fig. 20-9 shows the configuration of the control data.
259 µ PD17062 (2) Vertical size data (b 12 and b 11 of the control data) The vertical size data determines the vertical size of each image of a character. Up to four sizes can be specified on each row. Table 20-8 lists details of the vertical size data.
260 µ PD17062 (4) Vertical position data (b 6 to b 3 of the control data) The vertical position data specifies which of the 12 rows (vertical positions) shown in Fig.
261 µ PD17062 (5) Color data (b 2 to b 0 of the control data) The color data specifies the color of a display character. It is output from a specified output pin (R, G, or B pin). Table 20-9 lists the correspondence between the color data and the output pins.
262 µ PD17062 20.5.3 Defining Display Patterns with an Assembler With the 17K series assembler, the DCP pseudo instruction can be used to define display patterns easily.
263 µ PD17062 20.6 BLANK, R, G, AND B PINS All these pins are CMOS push-pull output pins. They output an active-high signal. The BLANK pin outputs a signal to turn off a broadcasting picture.
264 µ PD17062 20.7 SPECIFYING THE DISPLAY START POSITION IDC display start positions (upper left of the screen) can be specified by setting data in the IDC start position setting register. Up to 16 horizontal and vertical positions can be specified. In other words, the display position of the entire screen can be shifted.
265 µ PD17062 20.7.1 Horizontal Start Position Setting Register If the horizontal start position setting register contains 0H, the horizontal start position is set 4.
266 µ PD17062 20.7.2 Vertical Start Position Setting Register If the vertical start position setting register contains 0H, the vertical start position is set 17 H (interlace) after the trailing edge of the vertical sync signal.
267 µ PD17062 The vertical start position of the display character is determined by the vertical start position register. At this point, the vertical start position (number of horizontal scan lines) depends on the state of the V SYNC and H SYNC signals supplied to the µ PD17062, as shown in Fig.
268 µ PD17062 20.8 SAMPLE PROGRAMS The following sample program generates a display shown below. The RAM names of VRAM are defined as follows (tentative): NEC CH 02 .
269 µ PD17062 The sample program follows: Program start ; Performs initialization such as clearing RAM. Initialization SET1 IDCDMAEN ; Selects the DMA mode. CLR1 IDCEN ; Turns off the display. ; ; ** Channel display routine ** ; CLR1 CROMBNK ; Sets the CROM bank to 0.
270 µ PD17062 At point , the contents of VRAM (BANK2) are as follows: For this example, the contents of CROM are as follows: 0 8 1 0 2 0 3 C 4 0 5 D 6 8 7 1 8 0 9 0 A 0 B 2 C 4 D 0 E 4 F 0 0 1 CROM D.
271 µ PD17062 ; ******** ; ******** ; ******** 1 0810 0000 0811 0006 0812 000E 0813 001E 0814 0076 0815 00C6 0816 0186 0817 0006 0818 0006 0819 0006 081A 0006 081B 0006 081C 0006 081D 0006 081E 0006 .
272 µ PD17062 ; ******** ; ******** ; ******** 3 0830 0000 0831 007C 0832 00FE 0833 01C7 0834 0183 0835 0003 DCP 0, ' DCP 0, ' DCP 0, ' DCP 0, ' DCP 0, ' DCP 0, ' ; “3.
273 µ PD17062 ; ******** ; ******** ; ******** H 08D0 0000 08D1 0183 08D2 0183 08D3 0183 08D4 0183 08D5 0183 08D6 0183 08D7 01FF 08D8 01FF 08D9 0183 08DA 0183 08DB 0183 08DC 0183 08DD 0183 08DE 0183 .
274 µ PD17062 21. HORIZONTAL SYNC SIGNAL COUNTER 21.1 HORIZONTAL SYNC SIGNAL COUNTER CONFIGURATION The horizontal sync signal counter counts the frequency of a horizontal sync signal for TV or similar equipment. When a TV broadcasting signal is received, a prescribed horizontal sync signal is output.
275 µ PD17062 21.2 GATE CONTROL REGISTER (HSCGT) The gate control register is a 2-bit register consisting of the HSCGT1 and HSCGT0 flags used to control the gate.
276 µ PD17062 21.3 HSYNC COUNTER (HSC) The HSYNC counter is mapped at peripheral address 04H. It is a 6-bit read-only binary counter. It can be read-accessed through the data buffer using the GET instruction. When it overflows, the 6-bit HSYNC counter goes back to 00H.
277 µ PD17062 22. INSTRUCTION SETS 22.1 OUTLINE OF INSTRUCTION SETS b 15 b 14 -b 11 0 1 BIN HEX 0000 0 ADD r, m ADD m, #n4 0001 1 SUB r, m SUB m, #n4 0 0 1 0 2 ADDC r, m ADDC m, #n4 0011 3 SUBC r, m .
278 µ PD17062 22.2 INSTRUCTIONS Legend AR : Address register ASR : Address stack register pointed to by the stack pointer addr : Program memory address (11 low-order bits) BANK : Bank register CMP : .
279 µ PD17062 22.3 LIST OF INSTRUCTION SETS Instruction set Add Subtract Logical operation Test Compare Rotation Transfer Mne- monic ADD ADDC INC SUB SUBC OR AND XOR SKT SKF SKE SKNE SKGE SKLT RORC L.
280 µ PD17062 Instruction code Mne- monic PUSH POP PEEK POKE GET PUT BR CALL RET RETSK RETI EI DI STOP HALT NOP Operand AR AR WR, rf rf, WR DBF, p p, DBF addr @AR addr @AR s h Instruction set Transfe.
281 µ PD17062 22.4 BUILT-IN MACRO INSTRUCTIONS The following macro instructions are built in the 17K series assembler (AS17K). For details, refer to the assembler user’s guide. Legend flag n : FLG-type symbol < > : An operand enclosed in < > is optional.
282 µ PD17062 23. RESERVED SYMBOLS FOR ASSEMBLER The reserved µ PD17062 symbols for the assembler are listed below. 23.1 SYSTEM REGISTER MEM MEM MEM MEM MEM MEM MEM MEM FLG MEM MEM MEM MEM MEM MEM FLG FLG FLG FLG FLG 0.74H 0.75H 0.76H 0.77H 0.78H 0.
283 µ PD17062 23.3 PORT REGISTER Symbol Attribute Value Read/ Description write P0A3 FLG 0.70H.3 R/W Bit 3 of port 0A P0A2 FLG 0.70H.2 R/W Bit 2 of port 0A P0A1 FLG 0.70H.1 R/W Bit 1 of port 0A P0A0 FLG 0.70H.0 R/W Bit 0 of port 0A P0B3 FLG 0.71H.3 R/W Bit 3 of port 0B P0B2 FLG 0.
284 µ PD17062 Symbol Attribute Value Read/ Description write IDCDMAEN FLG 0.80H.1 R/W DMA enable flag SP MEM 0.81H R/W Stack pointer CE FLG 0.87H.0 R CE pin status flag SIO0CH FLG 0.88H.3 R/W SIO0 channel selection flag SB FLG 0.88H.2 R/W SIO0 mode selection flag SIO0MS FLG 0.
285 µ PD17062 Symbol Attribute Value Read/ Description write SIO0SF8 FLG 0.0A8H.3 R SIO0 shift 8 clock flag SIO0SF9 FLG 0.0A8H.2 R SIO0 shift 9 clock flag SBSTT FLG 0.0A8H.1 R Serial bus start test flag SBBSY FLG 0.0A8H.0 R Serial bus busy flag IPSIO0 FLG 0.
286 µ PD17062 23.5 PERIPHERAL HARDWARE REGISTER Symbol Attribute Value Read/ Description write IDCORG DAT 01H R/W IDC start position setting register ADCR DAT 02H R/W A/D-converter reference-voltage .
287 µ PD17062 24. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (T a = 25 ± 2 ° C) Parameter Symbol Rated value Unit Supply voltage V DD –0.
288 µ PD17062 AC CHARACTERISTICS (T a = –40 to +85 ° C, V DD = 5 V ± 10 %, RH ≤ 70 %) Parameter Symbol Conditions Min. Typ. Max. Unit Operating frequency f in1 VCO Sine wave input V in = 0.7 V P-P 0.7 20 MHz f in2 TMIN 45 65 Hz f in3 HSCNT 10 20 kHz IDC jitter IDC G 4.
289 µ PD17062 25. PACKAGE DRAWINGS 48PIN PLASTIC SHRINK DIP (600 mil) ITEM MILLIMETERS INCHES NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. N 0.17 0.007 A 44.46 MAX. 1.
290 µ PD17062 64 PIN PLASTIC QFP ( 14) ITEM MILLIMETERS INCHES F G K N J 1.0 1.6±0.2 0.10 0.8 (T.P.) 1.0 Q 0.039 0.039 0.063±0.008 0.004 0.031 (T.P.) S64GC-80-3BE-1 A C NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.
291 µ PD17062 26. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the µ PD17062. For details of the recommended soldering conditions, refer to our document SMD Surface Mount Technology Manual (IEI-1207) .
292 µ PD17062 Name Description APPENDIX DEVELOPMENT TOOLS The following support tools are available for developing programs for the µ PD17062. Hardware The IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators applicable to the 17K series.
293 µ PD17062 17K series assembler (AS17K) Device file (AS17062) Support software (SIMPLEHOST) µ S5A10AS17K µ S5A13AS17K µ S7B10AS17K µ S7B13AS17K µ S5A10AS17062 µ S5A13AS17062 µ S7B10AS17062 µ S7B13AS17062 µ S5A10IE17K µ S5A13IE17K µ S7B10IE17K µ S7B13IE17K AS17K is an assembler applicable to the 17K series.
294 µ PD17062 [MEMO].
295 µ PD17062 Cautions on CMOS Devices Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates.
296 µ PD17062 SIMPLEHOST is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. Caution This product contains an I 2 C bus interface circuit. When using the I 2 C bus interface, notify its use to NEC when ordering custom code.
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In een situatie waarin je al een beziter van NEC PD17062 bent, maar toch heb je de instructies niet gelezen, moet je het doen voor de hierboven beschreven redenen. Je zult dan weten of je goed de alle beschikbare functies heb gebruikt, en of je fouten heb gemaakt die het leven van de NEC PD17062 kunnen verkorten.
Maar de belangrijkste taak van de handleiding is om de gebruiker bij het oplossen van problemen te helpen met NEC PD17062 . Bijna altijd, zal je daar het vinden Troubleshooting met de meest voorkomende storingen en defecten #MANUAl# samen met de instructies over hun opplosinge. Zelfs als je zelf niet kan om het probleem op te lossen, zal de instructie je de weg wijzen naar verdere andere procedure, bijv. door contact met de klantenservice of het dichtstbijzijnde servicecentrum.
