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© 1997,1999 DATA SHEET © 1997 MIPS Technologies Inc. MOS INTEGRA TED CIRCUIT µ PD30500, 30500A, 30500B Document No. U12031EJ3V0DS00 (3rd edition) Date Published August 1999 N CP(K) Printed in Japan.
µ PD30500, 30500A, 30500B 2 Data Sheet U12031EJ3V0DS00 APPLICATIONS • High-performance embedded systems • Multimedia systems • Entry-class computers • Image processing systems ORDERING INFORM.
µ PD30500, 30500A, 30500B 3 Data Sheet U12031EJ3V0DS00 PIN CONFIGURATION • 223-pin ceramic PGA (48 × 48 mm) µ PD30500RJ-150 µ PD30500RJ-180 µ PD30500RJ-200 18 17 16 15 14 13 12 11 10 9 8 7 6 5 .
µ PD30500, 30500A, 30500B 4 Data Sheet U12031EJ3V0DS00 No. Name No. Name No. Name No. Name No. Name No. Name A2 V DD A3 GND A4 V DD A5 GND A6 GND A7 V DD A8 GND A9 V DD A10 GND A11 V DD A12 GND A13 V.
µ PD30500, 30500A, 30500B 5 Data Sheet U12031EJ3V0DS00 • 272-pin plastic BGA (29 × 29 mm) µ PD30500S2-150 µ PD30500S2-180 µ PD30500S2-200 µ PD30500AS2-200 Note µ PD30500AS2-250 Note µ PD3050.
µ PD30500, 30500A, 30500B 6 Data Sheet U12031EJ3V0DS00 (1) µ PD30500 No. Name No. Name No. Name No. Name No. Name No. Name A1 GND A2 V DD A3 GND A4 SysAD32 A5 GND A6 ScCWE1 A7 GND A8 V DD Ok A9 GND .
µ PD30500, 30500A, 30500B 7 Data Sheet U12031EJ3V0DS00 A1 GND A2 V DD IO A3 GND A4 SysAD32 A5 GND A6 ScCWE1 A7 GND A8 V DD Ok A9 GND A10 SysClock A11 GND A12 ScLine15 A13 GND A14 ScLine12 A15 GND A16.
µ PD30500, 30500A, 30500B 8 Data Sheet U12031EJ3V0DS00 PIN NAMES BigEndian : Endian Mode Select ColdReset : Cold Reset ExtRqst : External Request GND : Ground GNDP : Quiet GND for PLL Int (0:5) : Int.
µ PD30500, 30500A, 30500B 9 Data Sheet U12031EJ3V0DS00 INTERNAL BLOCK DIAGRAM Data, address System interface Control Clock generator SysClock Instruction cache Data cache Instruction address Pipeline.
µ PD30500, 30500A, 30500B 10 Data Sheet U12031EJ3V0DS00 PIN FUNCTIONS Pin Name I/O Function SysAD (0:63) I/O System address/data bus. 64-bit bus for communication between processor, secondary cache and external agent. SysADC (0:7) I/O System address/data check bus.
µ PD30500, 30500A, 30500B 11 Data Sheet U12031EJ3V0DS00 Pin Name I/O Function Int (0:5) Input Interrupt. General-purpose processor interrupt requests whose input statuses can be confirmed by bits 15 through 10 of cause register. NMI Input Non-maskable interrupt.
µ PD30500, 30500A, 30500B 12 Data Sheet U12031EJ3V0DS00 ELECTRICAL SPECIFICATIONS (1) µ PD30500 Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Supply voltage V DD –0.5 to +4.0 V Input voltage Note V I –0.5 to V DD + 0.3 V Pulse of less than 10 ns –1.
µ PD30500, 30500A, 30500B 13 Data Sheet U12031EJ3V0DS00 Capacitance Parameter Symbol Condition MIN. MAX. Unit Input capacitance C In 5p F Output capacitance C out 7p F AC Characteristics (T C = 0 to +70 ° C (PGA Package), T C = 0 to +85 ° C (BGA Package), V DD = 3.
µ PD30500, 30500A, 30500B 14 Data Sheet U12031EJ3V0DS00 System Interface Parameter Parameter Symbol Condition MIN. MAX. Unit Data output hold time t DM Modebit (14 : 13) = 10 1.0 ns Modebit (14 : 13) = 11 1.1 ns Modebit (14 : 13) = 00 1.3 ns Modebit (14 : 13) = 01 1.
µ PD30500, 30500A, 30500B 15 Data Sheet U12031EJ3V0DS00 (2) µ PD30500A (Preliminary) Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Supply voltage V DD IO –0.5 to +4.0 V V DD –0.3 to +3.3 V Input voltage Note V I –0.5 to V DD IO + 0.
µ PD30500, 30500A, 30500B 16 Data Sheet U12031EJ3V0DS00 Capacitance Parameter Symbol Condition MIN. MAX. Unit Input capacitance C In 5p F Output capacitance C out 7p F AC Characteristics (T C = 0 to +85 ° C, V DD IO = 3.3 V ± 5 %, V DD = 2.5 V ± 5 %) Clock parameter Parameter Symbol Condition MIN.
µ PD30500, 30500A, 30500B 17 Data Sheet U12031EJ3V0DS00 System Interface Parameter Parameter Symbol Condition MIN. MAX. Unit Data output hold time t DM Modebit (14 : 13) = 10 1.3 ns Modebit (14 : 13) = 11 1.4 ns Modebit (14 : 13) = 00 1.5 ns Modebit (14 : 13) = 01 1.
µ PD30500, 30500A, 30500B 18 Data Sheet U12031EJ3V0DS00 (3) µ PD30500B (Preliminary) Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Supply voltage V DD IO –0.5 to +4.0 V V DD –0.3 to +2.5 V Input voltage Note V I –0.5 to V DD IO + 0.
µ PD30500, 30500A, 30500B 19 Data Sheet U12031EJ3V0DS00 Capacitance Parameter Symbol Condition MIN. MAX. Unit Input capacitance C In 5p F Output capacitance C out 7p F AC Characteristics (T C = 0 to +85 ° C, V DD IO = 3.3 V ± 5 %, V DD = 1.8 V ± 0.
µ PD30500, 30500A, 30500B 20 Data Sheet U12031EJ3V0DS00 System Interface Parameter Parameter Symbol Condition MIN. MAX. Unit Data output hold time t DM Modebit (14 : 13) = 10 1.3 ns Modebit (14 : 13) = 11 1.4 ns Modebit (14 : 13) = 00 1.5 ns Modebit (14 : 13) = 01 1.
µ PD30500, 30500A, 30500B 21 Data Sheet U12031EJ3V0DS00 Test Condition t DO 50 % 50 % SysClock All output pins t DM Test Load All output pins DUT C L = 50 pF Timing Chart Clock timing t CP t CH t CL .
µ PD30500, 30500A, 30500B 22 Data Sheet U12031EJ3V0DS00 Clock jitter t ji 50 % t ji SysClock System interface edge timing t DO t DH t DH Output Output Output Output Input Input t DO t DM t DM t DS t .
µ PD30500, 30500A, 30500B 23 Data Sheet U12031EJ3V0DS00 Clocking relations 12 34 Cycle SysClock (input) PClock (output) SysAD Driven (output) SysAD Received (input) t DS t DH Data Data Data Data Data Data Data t DM t DO Data Power application sequence (V R 5000A, V R 5000B only) t DP t DP 0.
µ PD30500, 30500A, 30500B 24 Data Sheet U12031EJ3V0DS00 Reset Timing Power-on reset timing V DD I/O Note 2 ≥ 64 K SysClock SysClock V DD Ok ModeClock ModeIn t MDS ≥ 100 ms 256 SysClock Undefined bit0 bit1 bit255 t MDH ColdReset Reset t DS ≥ 64 SysClock t DS V DD Note 1 3.
µ PD30500, 30500A, 30500B 25 Data Sheet U12031EJ3V0DS00 Warm reset timing H V DD IO Note ≥ 64 SysClock SysClock V DD Ok ColdReset Reset t DS t DS H V DD H H Note V R 5000A, V R 5000B only.
µ PD30500, 30500A, 30500B 26 Data Sheet U12031EJ3V0DS00 PACKAGE DRAWING F φ M M L H G J E Index Mark X223RJ-100A-1 ITEM MILLIMETERS INCHES A D E F G H 47.24 ± 0.25 2.03 2.54(T.P.) J 3.98 MAX. 0.50 MIN. 3.30 ± 0.2 K 1.860 ± 0.010 0.080 0.100(T.P.) 0.
µ PD30500, 30500A, 30500B 27 Data Sheet U12031EJ3V0DS00 Each ball centerline is located within 0.30 mm of its true position (T.P.) at maximum material condition. Each ball centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
µ PD30500, 30500A, 30500B 28 Data Sheet U12031EJ3V0DS00 RECOMMENDED SOLDERING CONDITIONS Soldering this product under the following soldering conditions is recommended. For the details of the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E) .
µ PD30500, 30500A, 30500B 29 Data Sheet U12031EJ3V0DS00 DIFFERENCES BETWEEN THE V R 5000 AND V R 4310 TM Item V R 5000 V R 4310 Operating frequency Internal 200 MHz MAX.
µ PD30500, 30500A, 30500B 30 Data Sheet U12031EJ3V0DS00 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation.
µ PD30500, 30500A, 30500B 31 Data Sheet U12031EJ3V0DS00 NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd.
µ PD30500, 30500A, 30500B • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation.
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