Gebruiksaanwijzing /service van het product PD75P308 van de fabrikant NEC
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NEC Corporation 1989 Document No. IC-2472B (O. D. No. IC-7208C) Date Published November 1993 P Printed in Japan DA T A SHEET MOS INTEGRA TED CIRCUIT µ PD75P308 The mark ★ shows major revised points.
µ PD75P308 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 S31/BP7 COM0 COM1 C.
µ PD75P308 3 BLOCK DIAGRAM P00-P03 P10-P13 P20-P23 P30-P33 /MD0-MD3 P40-P43 P50-P53 P60-P63 P70-P73 4 4 4 4 4 4 4 4 PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 S0-S23 S24/BP0 -S31/BP7 COM0-COM3 V -V LCO LC2 BIAS LCDCL/P30 SYNC/P30 24 8 4 3 LCD CONTROLLER /DRIVER f LCD RESET SP(8) BANK GENERAL REG.
µ PD75P308 4 CONTENTS 1. PIN FUNCTIONS ................................................................................................................................. 5 1.1 PORT PINS .................................................................
µ PD75P308 5 E-B P00 Input INT4 P01 Input/Output SCK P02 Input/Output SO/SB0 P03 Input/Output SI/SBI P10 INT0 P11 INT1 P12 INT2 P13 TI0 P20 PTO0 P21 — P22 PCL P23 BUZ P30* 2 P31* 2 P32* 2 MD2 P33* .
µ PD75P308 6 Timer/event counter external event pulse input Timer/event counter output Clock output Fixed frequency output (for buzzer or for trimming the system clock) Serial clock input/output Seri.
µ PD75P308 7 1.3 PIN INPUT/OUTPUT CIRCUITS The following shows a simplified input/output circuit diagram for each pin of the µ PD75P308. TYPE A (for TYPE E–B) TYPE D (for TYPE E– B, F-A) TYPE B .
µ PD75P308 8 P-ch TYPE F– A TYPE G – C TYPE G–A TYPE G–B V DD V LC0 V LC0 V LC1 V LC2 SEG data/Bit Port data P-ch N-ch OUT N-ch V LC1 V LC2 P-ch P-ch N-ch OUT N-ch V LC0 V LC1 V LC2 P-ch N-ch SEG data COM data OUT P-ch N-ch N-ch P-ch data output disable Type D Type B P.
µ PD75P308 9 TYPE M-C data output disable P.U.R. enable V DD P.U.R. IN/OUT P–ch N-ch P.U.R. : Pull–Up Resistor 1.4 NOTES ON USING P00/INT4 AND RESET PINS In addition to the functions shown in sections 1.
µ PD75P308 10 Item µ PD75P308K µ PD75P308GF µ PD75308GF • EPROM • PROM (one-time model) • Mask ROM • 0000H-1F7FH • 0000H-1F7FH • 0000H-1F7FH • 8064 x 8 bits • 8064 x 8 bits • 806.
µ PD75P308 11 Pin Name Function V PP Applies voltage when program memory is written/verified (normally, at V DD potential) These pins input clock that updates address when program memory is written/verified. To X2 pin, input signal 180º out of phase in respect to signal to X1 pin.
µ PD75P308 12 3.2 PROGRAM MEMORY WRITE PROCEDURE The program memory write procedure is as follows. High-speed program memory write is possible. (1) Ground the unused pins through pull-down resistors. The X1 pin must be low. (2) Supply 5 V to the V DD and V PP pins.
µ PD75P308 13 3.3 PROGRAM MEMORY READ PROCEDURE The contents of the program memory can be read in the following procedure. (1) Ground the unused pins through pull-down resistors. The X1 pin must be low. (2) Supply 5 V to the V DD and V PP pins. (3) Wait for 10 microseconds.
µ PD75P308 14 3.4 ERASURE ( µ PD75P308K ONLY) The contents of the data programmed to the µ PD75P308 can be erased by exposing the window of the program memory to ultraviolet rays. The wavelength of the ultraviolet rays used to erase the contents is about 250 nm, and the quantity of the ultraviolet rays necessary for complete erasure is 15 W.
µ PD75P308 15 4. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (T a = 25 ° C) Parameter Symbol Conditions Rating Unit Supply Voltage V DD -0.3 to +7.0 V Supply Voltage V PP -0.3 to +13.5 V V I1 Other than ports 4 or 5 -0.3 to V DD +0.3 V V I2 *1 Ports 4 and 5 Open-drain -0.
µ PD75P308 16 Ceramic *3 Oscillation frequency (f XX ) *1 Oscillation stabilization After V DD came to MIN. time *2 of oscillation voltage range Crystal Oscilaltion frequency (f XX ) *1 Oscillation s.
µ PD75P308 17 32 32.768 35 kHz 1.0 2 s 32 100 kHz 51 5 µ s Crystal Oscillation frequency (f XT ) Oscillation stabilization time * External Clock XT1 input frequency (f XT ) XT1 input high-, low-level widths (t XTH , t XTL ) SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (T a = -10 to +70 ° C, V DD = 5 V ± 5%) Oscillator Item Conditions MIN.
µ PD75P308 18 Ports 2, 3 Ports 0, 1, 6, 7, RESET Ports 4, 5 Open-drain X1, X2, XT1 Ports 2, 3, 4, 5 Ports 0, 1, 6, 7, RESET X1, X2, XT1 Ports 0, 2, 3, I OH = -1mA 6, 7 BIAS BP0-7 I OH = -100 µ A* 1 Ports 0, 2, 3, Ports 3, 4, 5 6, 7 I OL = 15mA I OL = 1.
µ PD75P308 19 AC CHARACTERISTICS (T a = -10 to + 70 ° C, V DD = 5V ± 5%) Operation Other Than Serial Transfer Parameter Symbol Conditions MIN. TYP. MAX.
µ PD75P308 20 SERIAL TRANSFER OPERATION TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit 1600 ns t KCY1 /2-50 ns 150 ns 400 ns 250 ns Output Output R L = 1k Ω , C L = 100pF* t KCY1 t KH1, t KL1 t SIK1 t KSI1 t KSO1 SCK Cycle Time SCK High-, Low-Level Widths SI Set-Up Time (vs.
µ PD75P308 21 1600 ns t KCY /2 -50 150 ns t KCY /2 ns 0 250 ns t KCY ns t KCY ns t KCY ns t KCY ns SCK Cycle Time SCK High-, Low-Level Widths SB0, 1 Set-Up Time (vs.
µ PD75P308 22 AC TIMING TEST POINT (excluding X1 and XT1 inputs) Test points 0.8 V DD 0.2 V DD 0.8 V DD 0.2 V DD CLOCK TIMING X1 input V DD –0.5V 0.
µ PD75P308 23 SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE: SCK t KL1 t KH1 t KCY1 Output data t SIK1 t KSI1 t KSO1 Input data SI SO TWO-LINE SERIAL I/O MODE: SCK t KL t KH t KCY t SIK t KSI SB0.
µ PD75P308 24 SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER RESET INPUT TIMING INT0, 1, 2, 4 KR0-7 t INTL t INTH INTERRUPT INPUT TIMING SCK t KL3,4 t KCY3,4 t SIK3,4 t KSI3,4 t KSO3,4 SB0,1 t KH.
µ PD75P308 25 Released by RESET Released by interrupt LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (T a = -10 to +70 ° C) 0 µ s 2 17 /f X ms * 3 ms Parameter Symbol Conditions MIN.
µ PD75P308 26 *1 : These symbols are the corresponding µ PD27C256 symbols. 2 : The internal address signal is incremented by 1 at the fourth rising edge of X1 input. The internal address is not connected to any pin. Parameter Symbol * 1 Conditions MIN.
µ PD75P308 27 V PP V DD V DD +1 V DD MD0 MD1 MD2 MD3 V PP V DD Data input Data output Data input Data input t VPS t VDS t t DS t DH tt DV t DF t DS t AH t AS t OPW t t M1R t PW t PCR t M1S t M1H t M3.
µ PD75P308 28 5. PACKAGE DRAWINGS N A M F B 64 65 40 K L 80 PIN PLASTIC QFP (14 × 20) 80 1 25 24 41 G D C P detail of lead end S Q 5°±5° M I H J P80GF-80-3B9-2 ITEM MILLIMETERS INCHES A B C D F G H I J K L 23.
µ PD75P308 29 X80KW-80A-1 ITEM MILLIMETERS INCHES NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. A B C D E F G H I J K Q R S T U W 20.
µ PD75P308 30 6. RECOMMENDED SOLDERING CONDITIONS It is recommended that µ PD75P308 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616).
µ PD75P308 31 Hardare IE-75000-R *1 In-circuit emulator for 75K series IE-75001-R IE-75000-R-EM *2 Emulation board for IE-75000-R and IE-75001-R EP-75308GF-R Emulation prove for µ PD75P308GF, provided with 80-pin conversion socket, EV-9200G-80. PG-1500 PROM programmer PA-75P308GF PROM programmer adapter solely used for µ PD75P308GF.
µ PD75P308 32 APPENDIX B. RELATED DOCUMENTS ★.
µ PD75P308 33 GENERAL NOTES ON CMOS DEVICES 1 STATIC ELECTRICITY (ALL MOS DEVICES) Exercise care so that MOS devices are not adversely influenced by static electricity while being handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge.
µ PD75P308 34 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation.
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