Gebruiksaanwijzing /service van het product 16-bit single-chip microcomputer van de fabrikant Renesas
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RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C F AMIL Y / M16C/60 SERIES 16 Rev. 1.02 Revision date: Jul. 01, 2005 Hardware Manual www.renesas.com Before using this material, please visit our website to verify that this is the most updated document available.
Keep safety first in your circuit designs! Notes regarding these materials • Renesas T echnology Corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them.
How to Use This Manual 1. Introduction This hardware manual provides detailed information on the M16C/6N Group (M16C/6NL, M16C/6NN) of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.
3. M16C Family Documents The following documents were prepared for the M16C family (1) . Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Har.
A-1 T able of Contents SFR Page Reference ............................................................................................................ B -1 1. Overview ...................................................................................
A-2 7.2 CPU Clock and Peripheral Function Clock .................................................................................... ............ 43 7.2.1 CPU Clock and BCLK .............................................................................
A-3 1 1. DMAC ....................................................................................................................... ......... 78 1 1.1 Transfer Cycle ...................................................................................
A-4 18. CAN Module ................................................................................................................. ... 198 18.1 CAN Module-Related Registers ............................................................................
A-5 20.4 Standard Serial I/O Mode .................................................................................................. .................... 256 20.4.1 ID Code Check Function ...............................................................
A-6 22.18 Flash Memory V ersion ..................................................................................................... .................... 308 22.18.1 Functions to Prevent Flash Memory from Rewriting ...................................
B-1 SFR Page Reference PM0 PM1 CM0 CM1 AIER PRCR CM2 WDTS WDC RMAD0 RMAD1 PLC0 PM2 SAR0 DAR0 TCR0 DM0CON SAR1 DAR1 TCR1 DM1CON Address Register Symbol Page The blank areas are reserved.
B-2 Address Register Symbol Page CAN0 Message Box 2: Identifier / DLC CAN0 Message Box 2: Data Field CAN0 Message Box 2: Time Stamp CAN0 Message Box 3: Identifier / DLC CAN0 Message Box 3: Data Field .
B-3 Address Register Symbol Page The blank areas are reserved. 200 201 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 01 10h 0 111 h 01 12h 01 13h 01 1.
B-4 FMR1 FMR0 RMAD2 AIER2 RMAD3 The blank areas are reserved. Address Register Symbol Page 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0.
B-5 C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL1 1 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 C0CTLR C0STR C0SSTR C0ICR C0IDR C0CONR C0RECR C0TECR C0TSR C1CTLR Address Register Symbol Page The blank areas are reserved.
B-6 T ABSR CPSRF ONSF TRGSR UDF TA 0 TA 1 TA 2 TA 3 TA 4 TB0 TB1 TB2 T A0MR T A1MR T A2MR T A3MR T A4MR TB0MR TB1MR TB2MR TB2SC U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON DM0SL DM1SL CRCD CRCIN Address Register Symbol Page The blank areas are reserved.
Rev.1.02 Jul 01, 2005 page 1 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev .1.02 Jul 01, 2005 Under development This document is under development and its contents are subject to change 1.
Rev.1.02 Jul 01, 2005 page 2 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change. 1.2 Performance Outline Tables 1.1 and 1.2 list a performance outline of M16C/6N Group (M16C/6NL, M16C/6NN).
Rev.1.02 Jul 01, 2005 page 3 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 4 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change. 1.3 Block Diagram Figure 1.1 shows a block diagram of M16C/6N Group (M16C/6NL, M16C/6NN).
Rev.1.02 Jul 01, 2005 page 5 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change. 1.4 Product List Table 1.3 lists the M16C/6N Group (M16C/6NL, M16C/6NN) products and Figure 1.
Rev.1.02 Jul 01, 2005 page 6 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change. PIN CONFIGURATION (top view) Figure 1.3 Pin Configuration (Top View) (1) 1.
Rev.1.02 Jul 01, 2005 page 7 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 8 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change. 1.6 Pin Description Tables 1.4 and 1.5 list the pin descriptions.
Rev.1.02 Jul 01, 2005 page 9 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1. Overview Under development This document is under development and its contents are subject to change. Table 1.5 Pin Description (100-pin and 128-pin Versions) (2) Applies the reference voltage for the A/D converter and D/A converter.
Rev.1.02 Jul 01, 2005 page 10 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 2. Central Processing Unit (CPU) Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 11 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 2. Central Processing Unit (CPU) Under development This document is under development and its contents are subject to change. 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing.
Rev.1.02 Jul 01, 2005 page 12 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 3. Memory Under development This document is under development and its contents are subject to change. 3. Memory Figure 3.1 shows a memory map of the M16C/6N Group (M16C/6NL, M16C/6NN).
Rev.1.02 Jul 01, 2005 page 13 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. 4. Special Function Register (SFR) SFR (Special Function Register) is the control register of peripheral functions.
Rev.1.02 Jul 01, 2005 page 14 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 15 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 16 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 17 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 18 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.6 SFR Information (6) X: Undefined NOTE: 1.
Rev.1.02 Jul 01, 2005 page 19 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. Table 4.7 SFR Information (7) X: Undefined NOTES: 1.
Rev.1.02 Jul 01, 2005 page 20 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 21 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. X: Undefined NOTE: 1. The blank areas are reserved and cannot be accessed by users.
Rev.1.02 Jul 01, 2005 page 22 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. X: Undefined NOTE: 1. The blank areas are reserved and cannot be accessed by users.
Rev.1.02 Jul 01, 2005 page 23 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. X: Undefined NOTES: 1. The TA2P to TA4P bits in the UDF register are set to "0" after reset.
Rev.1.02 Jul 01, 2005 page 24 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 4. Special Function Register (SFR) Under development This document is under development and its contents are subject to change. X: Undefined NOTES: 1. These registers exist only in the128-pin version.
Rev.1.02 Jul 01, 2005 page 25 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 5. Reset Under development This document is under development and its contents are subject to change. 5. Reset Hardware reset, software reset, watchdog timer reset and oscillation stop detection reset are available to reset the microcomputer.
Rev.1.02 Jul 01, 2005 page 26 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 5. Reset Under development This document is under development and its contents are subject to change. Figure 5.2 Reset Sequence Figure 5.1 Example Reset Circuit RESET VCC R E S E T VCC 0 V 0 V Supply a clock with td(P-R) +20 or more cycles to the XIN pin 0.
Rev.1.02 Jul 01, 2005 page 27 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 5. Reset Under development This document is under development and its contents are subject to change. P0, P1, P2, P3, P4, P5, P6, P7, Input port P8_0 to P8_4, P8_6, P8_7, P9, P10, P11, P12, P13, P14_0, P14_1 (2) ____________ Table 5.
Rev.1.02 Jul 01, 2005 page 28 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 6. Processor Mode Under development This document is under development and its contents are subject to change. 6. Processor Mode Three processor mode is available single-chip mode only.
Rev.1.02 Jul 01, 2005 page 29 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 6. Processor Mode Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 30 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 6. Processor Mode Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 31 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 32 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 33 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 7.2 CM0 Register System Clock Control Register 0 (1) NOTES: 1.
Rev.1.02 Jul 01, 2005 page 34 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 35 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 36 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 7.5 PCLKR Register NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
Rev.1.02 Jul 01, 2005 page 37 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 38 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 39 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. NOTE: 1 . Place a damping resistor if required.
Rev.1.02 Jul 01, 2005 page 40 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 7.10 Examples of Sub Clock Connection Circuit 7.
Rev.1.02 Jul 01, 2005 page 41 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7.1.3 On-chip Oscillator Clock This clock, approximately 1 MHz, is supplied by a on-chip oscillator.
Rev.1.02 Jul 01, 2005 page 42 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. Figure 7.11 Procedure to Use PLL Clock as CPU Clock Source Set the PLC02 to PLC00 bits (multiplying factor).
Rev.1.02 Jul 01, 2005 page 43 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 44 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7.4 Power Control Normal operation mode, wait mode and stop mode are provided as the power consumption control.
Rev.1.02 Jul 01, 2005 page 45 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7.4.1.6 On-chip Oscillator Mode The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock.
Rev.1.02 Jul 01, 2005 page 46 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7.4.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer.
Rev.1.02 Jul 01, 2005 page 47 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 48 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
Rev.1.02 Jul 01, 2005 page 49 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change. 7.4.3.3 Exiting Stop Mode _______ Stop mode is exited by a hardware reset, NMI interrupt or peripheral function interrupt.
Rev.1.02 Jul 01, 2005 page 50 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 51 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 52 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 53 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 54 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 55 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 8. Protection Under development This document is under development and its contents are subject to change. 8. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily.
Rev.1.02 Jul 01, 2005 page 56 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 57 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. 9.2 Software Interrupts A software interrupt occurs when executing certain instructions.
Rev.1.02 Jul 01, 2005 page 58 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. 9.3 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.
Rev.1.02 Jul 01, 2005 page 59 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. Figure 9.2 Interrupt Vector 9.4.1 Fixed Vector Tables The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh.
Rev.1.02 Jul 01, 2005 page 60 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 61 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. 9.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted.
Rev.1.02 Jul 01, 2005 page 62 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 63 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. 9.5.1 I Flag The I flag enables or disables the maskable interrupt.
Rev.1.02 Jul 01, 2005 page 64 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 65 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 66 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. 9.5.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack.
Rev.1.02 Jul 01, 2005 page 67 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 68 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 69 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. ______ 9.6 INT Interrupt _______ INTi interrupt (i = 0 to 8) (1) is triggered by the edges of external inputs.
Rev.1.02 Jul 01, 2005 page 70 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 71 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 72 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 73 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change. ______ 9.7 NMI Interrupt _______ _______ ______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low.
Rev.1.02 Jul 01, 2005 page 74 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 75 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 76 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 10. W atchdog T imer Under development This document is under development and its contents are subject to change. 10. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control.
Rev.1.02 Jul 01, 2005 page 77 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 10. W atchdog T imer Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 78 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change. 11. DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Rev.1.02 Jul 01, 2005 page 79 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 80 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 81 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 82 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 83 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change. 11.1 Transfer Cycle The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle.
Rev.1.02 Jul 01, 2005 page 84 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change. Figure 11.5 Transfer Cycles for Source Read NOTE: 1. The same timing changes occur with the respective conditions at the destination as at the source.
Rev.1.02 Jul 01, 2005 page 85 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change. 11.2 DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible.
Rev.1.02 Jul 01, 2005 page 86 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 87 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 1 1. DMAC Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 88 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 89 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 90 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. 12.1 Timer A Figure 12.3 shows a block diagram of the timer A.
Rev.1.02 Jul 01, 2005 page 91 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 92 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 93 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 94 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 95 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 96 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 97 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 98 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 99 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 100 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 101 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 102 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. 12.1.4 Pulse Width Modulation (PWM) Mode In pulse width modulation mode, the timer outputs pulses of a given width in succession.
Rev.1.02 Jul 01, 2005 page 103 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 104 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 105 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. 12.2 Timer B Figure 12.15 shows a block diagram of the timer B.
Rev.1.02 Jul 01, 2005 page 106 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 107 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 108 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 109 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 110 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 111 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 112 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 12. T imers Under development This document is under development and its contents are subject to change. Figure 12.22 Operation Timing When Measuring Pulse Width Figure 12.
Rev.1.02 Jul 01, 2005 page 113 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 114 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 115 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change. Figure 13.2 INVC0 Register NOTES: 1.
Rev.1.02 Jul 01, 2005 page 116 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 117 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 118 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 119 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 120 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 121 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 122 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 123 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 13. Three-Phase Motor Control T imer Function Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 124 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14. Serial I/O Serial I/O is configured with 7 channels: UART0 to UART2 and SI/O3 to SI/O6 (1) .
Rev.1.02 Jul 01, 2005 page 125 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 126 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 127 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 128 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.5 U0TB to U2TB Registers, U0RB to U2RB Registers, and U0 BRG to U2BRG Registers Nothing is assigned When write, set to "0".
Rev.1.02 Jul 01, 2005 page 129 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 130 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 131 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 132 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 133 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 134 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data.
Rev.1.02 Jul 01, 2005 page 135 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 136 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Table 14.3 lists the functions of the input/output pins during clock synchronous serial I/O mode.
Rev.1.02 Jul 01, 2005 page 137 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 138 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 139 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.1.3 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format.
Rev.1.02 Jul 01, 2005 page 140 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 141 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 142 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 143 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 144 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Table 14.7 lists the functions of the input/output pins during UART mode.
Rev.1.02 Jul 01, 2005 page 145 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 146 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 147 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 148 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 149 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 150 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.3 Special Mode 1 (I 2 C Mode) I 2 C mode is provided for use as a simplified I 2 C interface compatible mode.
Rev.1.02 Jul 01, 2005 page 151 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 152 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 153 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 154 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.24 Transfer to UiRB Register and Interrupt Timing i = 0 to 2 This diagram applies to the case where the following condition is met.
Rev.1.02 Jul 01, 2005 page 155 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined.
Rev.1.02 Jul 01, 2005 page 156 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Table 14.13 STSPSEL Bit Functions Figure 14.26 STSPSEL Bit Functions 14.
Rev.1.02 Jul 01, 2005 page 157 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 14.
Rev.1.02 Jul 01, 2005 page 158 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 159 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.4 Special Mode 2 Multiple slaves can be serially communicated from one master.
Rev.1.02 Jul 01, 2005 page 160 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 161 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 162 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 163 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.29 Transmission and Reception Timing (CKPH = 0) in Slave Mode (External Clock) Figure 14.
Rev.1.02 Jul 01, 2005 page 164 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.1.5 Special Mode 3 (IE Mode) In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Rev.1.02 Jul 01, 2005 page 165 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 166 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 167 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 168 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.32 Transmit and Receive Timing in SIM Mode The above timing diagram applies to the case where data is received in the direct format.
Rev.1.02 Jul 01, 2005 page 169 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. Figure 14.33 shows the example of connecting the SIM interface.
Rev.1.02 Jul 01, 2005 page 170 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 171 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.2 SI/Oi (i = 3 to 6) (1) SI/Oi is exclusive clock-synchronous serial I/Os.
Rev.1.02 Jul 01, 2005 page 172 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 173 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 174 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 175 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change. 14.2.1 SI/Oi Operation Timing Figure 14.39 shows the SI/Oi operation timing.
Rev.1.02 Jul 01, 2005 page 176 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 177 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 178 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 179 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 180 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. Figure 15.3 ADCON2 Register, and AD0 to AD7 Registers NOTES: 1.
Rev.1.02 Jul 01, 2005 page 181 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 182 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 183 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. 15.1.2 Repeat Mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code.
Rev.1.02 Jul 01, 2005 page 184 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 185 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. 15.1.3 Single Sweep Mode In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code.
Rev.1.02 Jul 01, 2005 page 186 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 187 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. 15.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code.
Rev.1.02 Jul 01, 2005 page 188 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 189 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 190 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 191 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change. 15.2 Function 15.2.1 Resolution Select Function The desired resolution can be selected using the BITS bit in the ADCON1 register.
Rev.1.02 Jul 01, 2005 page 192 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 193 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 15. A/D Converter Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 194 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 16. D/A Converter Under development This document is under development and its contents are subject to change. 16. D/A Converter This is an 8-bit, R-2R type D/A converter.
Rev.1.02 Jul 01, 2005 page 195 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 16. D/A Converter Under development This document is under development and its contents are subject to change. Figure 16.2 DACON Register, DA0 and DA1 Registers Figure 16.
Rev.1.02 Jul 01, 2005 page 196 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 17. CRC Calculation Under development This document is under development and its contents are subject to change. 17. CRC Calculation The Cyclic Redundancy Check (CRC) operation detects an error in data blocks.
Rev.1.02 Jul 01, 2005 page 197 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 17. CRC Calculation Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 198 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 199 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.1 CAN Module-Related Registers The CAN0 module has the following registers.
Rev.1.02 Jul 01, 2005 page 200 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.2 CAN0 Message Box Table 18.1 shows the memory mapping of the CAN0 message box.
Rev.1.02 Jul 01, 2005 page 201 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. Figures 18.2 and 18.3 show the bit mapping in each slot in byte access and word access.
Rev.1.02 Jul 01, 2005 page 202 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. Figure 18.4 Bit Mapping of Mask Registers in Byte Access 18.
Rev.1.02 Jul 01, 2005 page 203 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.4 CAN SFR Registers Figures 18.6 to 18.12 show the CAN SFR registers.
Rev.1.02 Jul 01, 2005 page 204 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 205 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. - (b4-b0) - (b5) - (b6) - (b7) CAN1 Control Reg ister (1) C1CTLR X0000001b 0230h b7 b6 b5 b4 b3 b2 b1 b0 NOTE: 1.
Rev.1.02 Jul 01, 2005 page 206 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 207 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 208 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 209 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 210 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.5 Operational Modes The CAN module has the following four operational modes.
Rev.1.02 Jul 01, 2005 page 211 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.5.2 CAN Operation Mode The CAN operation mode is activated by setting the Reset bit in the C0CTLR register to “ 0 ” .
Rev.1.02 Jul 01, 2005 page 212 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.5.5 Bus Off State The bus off state is entered according to the fault confinement rules of the CAN specification.
Rev.1.02 Jul 01, 2005 page 213 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.6 Configuration CAN Module System Clock The M16C/6N Group (M16C/6NL, M16C/6NN) has a CAN module system clock select circuit.
Rev.1.02 Jul 01, 2005 page 214 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 215 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. Figure 18.17 Correspondence of Mask Registers to Slots Figure 18.
Rev.1.02 Jul 01, 2005 page 216 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 217 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 218 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 219 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.15 Reception and Transmission Table 18.3 shows configuration of CAN reception and transmission mode.
Rev.1.02 Jul 01, 2005 page 220 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 221 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.15.2 Transmission Figure 18.22 shows the timing of the transmit sequence.
Rev.1.02 Jul 01, 2005 page 222 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module Under development This document is under development and its contents are subject to change. 18.16 CAN Interrupt The CAN module provides the following CAN interrupts.
Rev.1.02 Jul 01, 2005 page 223 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 224 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. 19.1 PDi Register (100-pin Version: i = 0 to 10, 128-pin Version: i = 0 to 13) Figure19.
Rev.1.02 Jul 01, 2005 page 225 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure19.1 I/O Ports (1) NOTES: 1. Symbolizes a parasitic diode.
Rev.1.02 Jul 01, 2005 page 226 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 227 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 228 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 229 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 230 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Figure19.7 PD0 to PD13 Registers Nothing is assigned.
Rev.1.02 Jul 01, 2005 page 231 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 232 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change. Pull-up Control Register 0 Bit Name Bit Symbol RW b7 b6 b5 b4 b3 b2 b1 b0 PUR0 03FCh 00h Symbol Address After Reset NOTE: 1.
Rev.1.02 Jul 01, 2005 page 233 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 234 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 19. Programmable I/O Ports Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 235 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 236 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.1 Memory Map The flash memory contains the user ROM area and a boot ROM area.
Rev.1.02 Jul 01, 2005 page 237 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 238 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 239 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 240 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 241 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 242 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.3.3.1 FMR00 Bit This bit indicates the flash memory operating status.
Rev.1.02 Jul 01, 2005 page 243 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 20.6 Setting and Resetting of EW1 Mode Figure 20.
Rev.1.02 Jul 01, 2005 page 244 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 245 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.3.4 Precautions on CPU Rewrite Mode 20.3.
Rev.1.02 Jul 01, 2005 page 246 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.3.4.9 Writing Command and Data Write commands and data to even addresses in the user ROM area.
Rev.1.02 Jul 01, 2005 page 247 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.3.5 Software Commands Software commands are described below.
Rev.1.02 Jul 01, 2005 page 248 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 20.8 Program Command 20.3.5.4 Program Command (40h) The program command writes 2-byte data to the flash memory.
Rev.1.02 Jul 01, 2005 page 249 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Figure 20.9 Block Erase Command 20.3.5.5 Block Erase Command The block erase command erases each block.
Rev.1.02 Jul 01, 2005 page 250 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.3.5.6 Erase All Unlocked Block The erase all unlocked block command erases all blocks except the block A.
Rev.1.02 Jul 01, 2005 page 251 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.3.5.8 Read Lock Bit Status Command (71h) The read lock bit status command reads the lock bit state of a specified block.
Rev.1.02 Jul 01, 2005 page 252 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.3.6 Data Protect Function Each block in the flash memory has a nonvolatile lock bit.
Rev.1.02 Jul 01, 2005 page 253 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 254 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 255 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 256 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 257 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. Table 20.7 Pin Functions for Standard Serial I/O Mode NOTES: 1.
Rev.1.02 Jul 01, 2005 page 258 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 259 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 260 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.4.2 Example of Circuit Application in Standard Serial I/O Mode Figures 20.
Rev.1.02 Jul 01, 2005 page 261 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 262 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 263 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 264 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 265 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory V ersion Under development This document is under development and its contents are subject to change. 20.6.2 Example of Circuit Application in CAN I/O Mode Figure 20.
Rev.1.02 Jul 01, 2005 page 266 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change. 21. Electrical Characteristics Table 21.
Rev.1.02 Jul 01, 2005 page 267 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 268 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change. Table 21.3 Recommended Operating Conditions (2) (1) Main Clock Input Oscillation No W a i t Mask ROM Version VCC = 3.
Rev.1.02 Jul 01, 2005 page 269 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change. Table 21.4 Electrical Characteristics (1) (1) V CC -2.
Rev.1.02 Jul 01, 2005 page 270 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 271 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 272 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 273 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 274 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 275 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 21. Electric Characteristics Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 276 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22. Usage Precaution 22.1 SFR There is the SFR which can not be read (containg bits that will result in unknown data when read).
Rev.1.02 Jul 01, 2005 page 277 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.2 External Clock Do not stop the external clock when it is connected to the XIN pin and the main clock is selected as the CPU clock.
Rev.1.02 Jul 01, 2005 page 278 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.3 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met.
Rev.1.02 Jul 01, 2005 page 279 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.4 Power Control ____________ When exiting stop mode by hardware reset, set RESET pin to “ L ” until a main clock oscillation is stabilized.
Rev.1.02 Jul 01, 2005 page 280 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. Suggestions to reduce power consumption. Ports The processor retains the state of each I/O port even when it goes to wait mode or to stop mode.
Rev.1.02 Jul 01, 2005 page 281 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 282 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 283 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.7 Interrupt 22.7.1 Reading Address 00000h Do not read the address 00000h in a program.
Rev.1.02 Jul 01, 2005 page 284 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 285 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 286 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.8 DMAC 22.8.1 Write to DMAE Bit in DMiCON Register (i = 0, 1) When both of the conditions below are met, follow the steps below.
Rev.1.02 Jul 01, 2005 page 287 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.9 Timers 22.9.1 Timer A 22.9.1.1 Timer A (Timer Mode) The timer remains idle after reset.
Rev.1.02 Jul 01, 2005 page 288 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.9.1.2 Timer A (Event Counter Mode) The timer remains idle after reset.
Rev.1.02 Jul 01, 2005 page 289 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.9.1.3 Timer A (One-shot Timer Mode) The timer remains idle after reset.
Rev.1.02 Jul 01, 2005 page 290 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.9.1.4 Timer A (Pulse Width Modulation Mode) The timer remains idle after reset.
Rev.1.02 Jul 01, 2005 page 291 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.9.2 Timer B 22.9.2.1 Timer B (Timer Mode) The timer remains idle after reset.
Rev.1.02 Jul 01, 2005 page 292 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.9.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) The timer remains idle after reset.
Rev.1.02 Jul 01, 2005 page 293 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 294 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.11 Serial I/O 22.11.1 Clock Synchronous Serial I/O Mode 22.
Rev.1.02 Jul 01, 2005 page 295 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 296 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 297 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.12 A/D Converter Set the ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a trigger occurs).
Rev.1.02 Jul 01, 2005 page 298 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 299 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 300 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 301 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 302 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 303 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 304 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 305 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.15 Dedicated Input Pin When dedicated input pin voltage is larger than VCC pin voltage, latch up occurs.
Rev.1.02 Jul 01, 2005 page 306 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 307 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.17 Mask ROM Version When using the masked ROM version, write nothing to internal ROM area.
Rev.1.02 Jul 01, 2005 page 308 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 309 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 310 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change.
Rev.1.02 Jul 01, 2005 page 311 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution Under development This document is under development and its contents are subject to change. 22.20 Noise Connect a bypass capacitor (approximately 0.
Rev.1.02 Jul 01, 2005 page 312 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) Appendix 1. Package Dimensions Under development This document is under development and its contents are subject to change. Appendix 1. Package Dimensions Terminal cross section b 1 c 1 b p c 2.
Rev.1.02 Jul 01, 2005 page 313 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) Register Index Under development This document is under development and its contents are subject to change. Register Index A AD0 to AD7 ..........................
Rev.1.02 Jul 01, 2005 page 314 of 314 REJ09B0126-0102 M16C/6N Group (M16C/6NL, M16C/6NN) Register Index Under development This document is under development and its contents are subject to change. U0C1 to U2C1 ............................... 130 U0MR to U2MR .
REVISION HISTORY M16C/6N Group ( M16C/6NL, M16C/6NN) Hardware Manual Rev . Date Description Page Summary C-1 1.00 Sep. 30, 2004 1.01 Nov. 01, 2004 1.02 Jul. 01, 2005 – First edition issued – Revised edition issued * Revised parts and revised contents are as follows (except for expressional change).
REVISION HISTORY M16C/6N Group ( M16C/6NL, M16C/6NN) Hardware Manual Rev . Date Description Page Summary C-2 229 Figure 19.6 I/O Pins: NOTE 1 is deleted. 269 Table 21.4 Electrical Characteristics (1) • Measuring Condition of V OL is revised from “L OL = –200µA ” to “L OL = 200µA ”.
M16C/6N Group (M16C/6NL, M16C/6NN) Hardware Manual Publication Data : Rev.1.00 Sep 30, 2004 Rev.1.02 Jul 01, 2005 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
M16C/6N Group (M16C/6NL, M16C/6NN) Hardware Manual 2- 6 -2, Ote-machi, Chiyoda-ku, Tokyo, 1 00-0004, Japan.
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