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RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R-FPU 32 Rev. 1.01 Revision date: Oct 31, 2003 Software Manual www.renesas.com Before using this material, please visit our website to confirm that this is the most current document available.
Keep safety first in your circuit designs! Notes regarding these materials • Renesas T echnology Corporation puts the maximum ef fort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them.
REVISION HISTORY Rev . Date Description Page Summary M32R-FPU Software Manual 1.00 Jan 08, 2003 First edition issued – 1.01 Oct 31, 2003 Hexadecimal Instruction Code Table corrected (BTST instruction) APPENDICES-3 Appendix Figure 3.1.1 corrected Incorrect) *The E1 stage of the FDIV instruction requires 13 cycles.
M32R-FPU Software Manual (Rev.1.01) (1) T able of contents CHAPTER 1 CPU PROGRAMMING MODEL 1.1 CPU register .......................................................................................................... 1-2 1.2 General-purpose registers ..
M32R-FPU Software Manual (Rev.1.01) CHAPTER 3 INSTRUCTIONS 3.1 Conventions for instruction description ................................................................... 3-2 3.2 Instruction description ................................................
M32R-FPU Software Manual (Rev.1.01) This page left blank intentionally..
CHAPTER 1 CPU PROGRAMMIING MODEL 1.1 CPU Register 1.2 General-purpose Registers 1.3 Control Registers 1.4 Accumulator 1.5 Program Counter 1.6 Data Format 1.
1 1-2 M32R-FPU Software Manual (Rev.1.01) b0 b0 CPU PROGRAMMING MODEL 1.1 CPU Register 1.1 CPU Register The M32R family CPU, with a built-in FPU (herein referred to as M32R-FPU) has 16 general-purpose registers, 6 control registers, an accumulator and a program counter.
1 1-3 M32R-FPU Software Manual (Rev.1.01) CRn b31 b0 CPU PROGRAMMING MODEL 1.3 Control Registers 1.3 Control Registers There are 6 control registers which are the Processor Status Word Register (PSW),.
1 1-4 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.3 Control Registers The Processor Status Word Register (PSW) indicates the M32R-FPU status. It consists of the current PSW field which is regularly used, and the BPSW field where a copy of the PSW field is saved when EIT occurs.
1 1-5 M32R-FPU Software Manual (Rev.1.01) b0 CPU PROGRAMMING MODEL 1.3 Control Registers 1.3.2 Condition Bit Register: CBR (CR1) The Condition Bit Register (CBR) is derived from the PSW register by extracting its Condition (C) bit. The value written to the PSW register's C bit is reflected in this register.
1 1-6 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.3 Control Registers <At reset release: H0000 0100> b Bit Name Function R W 0 FS Reflects the logical sum of FU, FZ, FO and FV.
1 1-7 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.3 Control Registers 21 EV 0: Mask EIT processing to be executed when an R W Invalid Operation Exception invalid operation exception occurs Enable Bit 1: Execute EIT processing when an invalid operation exception occurs 22 No function assigned.
1 1-8 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.3 Control Registers 1.3.6 Floating-point Exceptions (FPE) Floating-point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions specified in the IEEE754 standard (OVF/UDF/IXCT/ DIV0/IVLD) is detected.
1 1-9 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.3 Control Registers (3) Inexact Exception (IXCT) The exception occurs when the operation result differs from a result led out with an infinite range of precision. The following table shows the operation results and the respective conditions in which each IXCT occurs.
1 1-10 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.3 Control Registers (5) Invalid Operation Exception (IVLD) The exception occurs when an invalid operation is executed. The following table shows the operation results and the respective conditions in which each IVLD occurs.
1 1-11 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.4 Accumulator 1.4 Accumulator The Accumulator (ACC) is a 56-bit register used for DSP function instructions. The accumulator is handled as a 64-bit register when accessed for read or write.
1 1-12 M32R-FPU Software Manual (Rev.1.01) 1.6 Data Format 1.6.1 Data Type The data types that can be handled by the M32R-FPU instruction set are signed or unsigned 8, 16, and 32-bit integers and single-precision floating-point numbers. The signed integers are represented by 2's complements.
1 1-13 M32R-FPU Software Manual (Rev.1.01) 1.6.2 Data Format (1) Data format in a register The data sizes in the M32R-FPU registers are always words (32 bits).
1 1-14 M32R-FPU Software Manual (Rev.1.01) (2) Data format in memory The data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits).
1 1-15 M32R-FPU Software Manual (Rev.1.01) 1.7 Addressing Mode M32R-FPU supports the following addressing modes. (1) Register direct [R or CR] The general-purpose register or the control register to be processed is specified. (2) Register indirect [@R] The contents of the register specify the address of the memory.
1 1-16 M32R-FPU Software Manual (Rev.1.01) CPU PROGRAMMING MODEL 1.7 Addressing Mode This page left blank intentionally..
CHAPTER 2 INSTRUCTION SET 2.1 Instruction set overview 2.2 Instruction format.
2 2-2 M32R-FPU Software Manual (Rev.1.01) 2.1 Instruction set overview The M32R-FPU has a total of 100 instructions. The M32R-FPU has a RISC architecture. Memory is accessed by using the load/store instructions and other operations are executed by using register-to-register operation instructions.
2 2-3 M32R-FPU Software Manual (Rev.1.01) INSTRUCTION SET 2.1 Instruction set overview Three types of addressing modes can be specified for load/store instructions. (1) Register indirect The contents of the register specify the address. This mode can be used by all load/ store instructions.
2 2-4 M32R-FPU Software Manual (Rev.1.01) 2.1.2 Transfer instructions The transfer instructions carry out data transfers between registers or a register and an immediate value. LD24 Load 24-bit immediate LDI Load immediate MV Move register MVFC Move from control register MVTC Move to control register SETH Set high-order 16-bit 2.
2 2-5 M32R-FPU Software Manual (Rev.1.01) • logic operation instructions AND AND AND3 AND 3-operand NOT Logical NOT OR OR OR3 OR 3-operand XOR Exclusive OR XOR3 Exclusive OR 3-operand • multiply/d.
2 2-6 M32R-FPU Software Manual (Rev.1.01) 2.1.4 Branch instructions The branch instructions are used to change the program flow. BC Branch on C-bit BEQ Branch on equal to BEQZ Branch on equal to zero .
2 2-7 M32R-FPU Software Manual (Rev.1.01) The addressing mode of the BRA , BL , BC and BNC instructions can specify an 8-bit or 24-bit immediate value. The addressing mode of the BEQ , BNE , BEQZ , BNEZ , BLTZ , BGEZ , BLEZ , and BGTZ instructions can specify a 16-bit immediate value.
2 2-8 M32R-FPU Software Manual (Rev.1.01) 2.1.5 EIT-related instructions The EIT-related instructions carry out the EIT events (Exception, Interrupt and Trap). Trap initiation and return from EIT are EIT-related instructions. TRAP Trap RTE Return from EIT 2.
2 2-9 M32R-FPU Software Manual (Rev.1.01) Fig. 2.1.2 DSP function instruction operation 1 (multiply, multiply and accumulate) Rsrc1 01 5 1 6 3 1 H ACC 06 3 L 01 5 1 6 3 1 H L x x MULLO instruction MUL.
2 2-10 M32R-FPU Software Manual (Rev.1.01) ACC 06 3 sign 0 RAC instruction ACC 06 3 sign 0 RACH instruction < word size round off > < halfword size round off > data data 06 3 06 3 Note: The actual operation is processed in two steps. Refer to Chapter 3 for details .
2 2-11 M32R-FPU Software Manual (Rev.1.01) INSTRUCTION SET 2.1 Instruction set overview 2.1.7 Floating-point Instructions The following instructions execute floating-point operations.
2 2-12 M32R-FPU Software Manual (Rev.1.01) 2.2 Instruction format There are two major instruction formats: two 16-bit instructions packed together within a word boundary, and a single 32-bit instruction (see Figure 2.2.1 ). Figure 2.2.2 shows the instruction format of M32R CPU.
2 2-13 M32R-FPU Software Manual (Rev.1.01) The MSB (Most Significant Bit) of a 32-bit instruction is always "1". The MSB of a 16-bit instruction in the high-order halfword is always "0" (instruction A in Figure 2.2.3), however the processing of the following 16-bit instruction depends on the MSB of the instruction.
2 2-14 M32R-FPU Software Manual (Rev.1.01) This page left blank intentionally. INSTRUCTION SET 2.2 Instruction format.
CHAPTER 3 INSTRUCTIONS 3.1 Conventions for instruction description 3.2 Instruction description.
3 3-2 M32R-FPU Software Manual (Rev.1.01) 3.1 Conventions for instruction description Conventions for instruction description are summarized below. [Mnemonic] Shows the mnemonic and possible operands (operation target) using assembly language notation.
3 3-3 M32R-FPU Software Manual (Rev.1.01) Table 3.1.3 Operation expression (operator) (cont.) operator meaning - sign invert (monomial operator) = substitute right side into left side (substitute oper.
3 3-4 M32R-FPU Software Manual (Rev.1.01) [Description] Describes the operation performed by the instruction and any condition bit change. [EIT occurrence] Shows possible EIT events (Exception, Interrupt, Trap) which may occur as the result of the instruction's execution.
3 3-5 M32R-FPU Software Manual (Rev.1.01) 3.2 Instruction description This section lists M32R-FPU instructions in alphabetical order. Each page is laid out as shown below.
3 3-6 M32R-FPU Software Manual (Rev.1.01) ADD dest 0000 ADD Rdest,Rsrc ADD 1010 arithmetic/logic operation Add src [Mnemonic] ADD Rdest,Rsrc [Function] Add Rdest = Rdest + Rsrc; [Description] ADD adds Rsrc to Rdest and puts the result in Rdest. The condition bit (C) is unchanged.
3 3-7 M32R-FPU Software Manual (Rev.1.01) ADD3 [Mnemonic] ADD3 Rdest,Rsrc,#imm16 [Function] Add Rdest = Rsrc + ( signed short ) imm16; [Description] ADD3 adds the 16-bit immediate value to Rsrc and puts the result in Rdest. The immediate value is sign-extended to 32 bits before the operation.
3 3-8 M32R-FPU Software Manual (Rev.1.01) ADDI [Mnemonic] ADDI Rdest,#imm8 [Function] Add Rdest = Rdest + ( signed char ) imm8; [Description] ADDI adds the 8-bit immediate value to Rdest and puts the result in Rdest. The immediate value is sign-extended to 32 bits before the operation.
3 3-9 M32R-FPU Software Manual (Rev.1.01) ADDV [Mnemonic] ADDV Rdest,Rsrc [Function] Add Rdest = ( signed ) Rdest + ( signed ) Rsrc; C = overflow ? 1 : 0; [Description] ADDV adds Rsrc to Rdest and puts the result in Rdest. The condition bit (C) is set when the addition results in overflow; otherwise it is cleared.
3 3-10 M32R-FPU Software Manual (Rev.1.01) ADDV3 [Mnemonic] ADDV3 Rdest,Rsrc,#imm16 [Function] Add Rdest = ( signed ) Rsrc + ( signed ) ( ( signed short ) imm16 ); C = overflow ? 1 : 0; [Description] ADDV3 adds the 16-bit immediate value to Rsrc and puts the result in Rdest.
3 3-11 M32R-FPU Software Manual (Rev.1.01) ADDX [Mnemonic] ADDX Rdest,Rsrc [Function] Add Rdest = ( unsigned ) Rdest + ( unsigned ) Rsrc + C; C = carry_out ? 1 : 0; [Description] ADDX adds Rsrc and C to Rdest, and puts the result in Rdest.
3 3-12 M32R-FPU Software Manual (Rev.1.01) AND AND 1100 0000 AND Rdest,Rsrc logic operation instruction AND src dest [Mnemonic] AND Rdest,Rsrc [Function] Logical AND Rdest = Rdest & Rsrc; [Description] AND computes the logical AND of the corresponding bits of Rdest and Rsrc and puts the result in Rdest.
3 3-13 M32R-FPU Software Manual (Rev.1.01) AND3 [Mnemonic] AND3 Rdest,Rsrc,#imm16 [Function] Logical AND Rdest = Rsrc & ( unsigned short ) imm16; [Description] AND3 computes the logical AND of the corresponding bits of Rsrc and the 16-bit immediate value, which is zero-extended to 32 bits, and puts the result in Rdest.
3 3-14 M32R-FPU Software Manual (Rev.1.01) BC BC [Mnemonic] (1) BC pcdisp8 (2) BC pcdisp24 [Function] Branch (1) if ( C==1 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed char ) pcdisp8 ) << 2 ); .
3 3-15 M32R-FPU Software Manual (Rev.1.01) bit operation Bit clear [M32R-FPU Extended Instruction] INSTRUCTIONS 3.2 Instruction description BCLR BCLR [Mnemonic] BCLR #bitpos,@(disp16,Rsrc) [Function] Bit operation for memory contents Set 0 to specified bit.
3 3-16 M32R-FPU Software Manual (Rev.1.01) BEQ BEQ branch instruction Branch on equal to [Mnemonic] BEQ Rsrc1,Rsrc2,pcdisp16 [Function] Branch if ( Rsrc1 == Rsrc2 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed short ) pcdisp16 ) << 2); [Description] BEQ causes a branch to the specified label when Rsrc1 is equal to Rsrc2.
3 3-17 M32R-FPU Software Manual (Rev.1.01) BEQZ BEQZ branch instruction Branch on equal to zero [Mnemonic] BEQZ Rsrc,pcdisp16 [Function] Branch if ( Rsrc == 0 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed short ) pcdisp16 ) << 2); [Description] BEQZ causes a branch to the specified label when Rsrc is equal to zero.
3 3-18 M32R-FPU Software Manual (Rev.1.01) BGEZ BGEZ branch instruction Branch on greater than or equal to zero [Mnemonic] BGEZ Rsrc,pcdisp16 [Function] Branch if ( (signed) Rsrc >= 0 ) PC = ( PC &.
3 3-19 M32R-FPU Software Manual (Rev.1.01) BGTZ BGTZ branch instruction Branch on greater than zero [Mnemonic] BGTZ Rsrc,pcdisp16 [Function] Branch if ((signed) Rsrc > 0) PC = (PC & 0xfffffffc).
3 3-20 M32R-FPU Software Manual (Rev.1.01) BL BL branch instruction Branch and link [Mnemonic] (1) BL pcdisp8 (2) BL pcdisp24 [Function] Subroutine call (PC relative) (1) R14 = ( PC & 0xfffffffc ).
3 3-21 M32R-FPU Software Manual (Rev.1.01) BLEZ BLEZ branch instruction Branch on less than or equal to zero [Mnemonic] BLEZ Rsrc,pcdisp16 [Function] Branch if ((signed) Rsrc <= 0) PC = (PC & 0.
3 3-22 M32R-FPU Software Manual (Rev.1.01) BLTZ BLTZ branch instruction Branch on less than zero [Mnemonic] BLTZ Rsrc,pcdisp16 [Function] Branch if ((signed) Rsrc < 0) PC = (PC & 0xfffffffc) + .
3 3-23 M32R-FPU Software Manual (Rev.1.01) BNC BNC branch instruction Branch on not C-bit [Mnemonic] (1) BNC pcdisp8 (2) BNC pcdisp24 [Function] Branch (1) if (C==0) PC = ( PC & 0xfffffffc ) + ( (.
3 3-24 M32R-FPU Software Manual (Rev.1.01) BNE BNE branch instruction Branch on not equal to [Mnemonic] BNE Rsrc1,Rsrc2,pcdisp16 [Function] Branch if ( Rsrc1 != Rsrc2 ) PC = ( PC & 0xfffffffc ) + ((( signed short ) pcdisp16) << 2); [Description] BNE causes a branch to the specified label when Rsrc1 is not equal to Rsrc2.
3 3-25 M32R-FPU Software Manual (Rev.1.01) BNEZ BNEZ branch instruction Branch on not equal to zero [Mnemonic] BNEZ Rsrc,pcdisp16 [Function] Branch if ( Rsrc != 0 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed short ) pcdisp16 ) << 2); [Description] BNEZ causes a branch to the specified label when Rsrc is not equal to zero.
3 3-26 M32R-FPU Software Manual (Rev.1.01) BRA BRA branch instruction Branch [Mnemonic] (1) BRA pcdisp8 (2) BRA pcdisp24 [Function] Branch (1) PC = ( PC & 0xfffffffc ) + ( ( ( signed char ) pcdisp.
3 3-27 M32R-FPU Software Manual (Rev.1.01) BSET BSET INSTRUCTIONS 3.2 Instruction description bit operation Instructions Bit set [M32R-FPU Extended Instruction] [Mnemonic] BSET #bitpos,@(disp16,Rsrc) [Function] Bit operation for memory contents Set 0 to specified bit.
3 3-28 M32R-FPU Software Manual (Rev.1.01) BTST BTST INSTRUCTIONS 3.2 Instruction description bit operation Instructions Bit test [M32R-FPU Extended Instruction] [Mnemonic] BTST #bitpos,Rsrc [Function] Remove the bit specified by the register.
3 3-29 M32R-FPU Software Manual (Rev.1.01) CLRPSW CLRPSW INSTRUCTIONS 3.2 Instruction description bit operation Instructions Clear PSW [M32R-FPU Extended Instruction] [Mnemonic] CLRPSW #imm8 [Function] Set the undefined SM, IE, and C bits of PSW to 0.
3 3-30 M32R-FPU Software Manual (Rev.1.01) CMP [Mnemonic] CMP Rsrc1,Rsrc2 [Function] Compare C = ( ( signed ) Rsrc1 < ( signed ) Rsrc2 ) ? 1:0; [Description] The condition bit (C) is set to 1 when Rsrc1 is less than Rsrc2. The operands are treated as signed 32-bit values.
3 3-31 M32R-FPU Software Manual (Rev.1.01) CMPI [Mnemonic] CMPI Rsrc,#imm16 [Function] Compare C = ( ( signed ) Rsrc < ( signed short ) imm16 ) ? 1:0; [Description] The condition bit (C) is set when Rsrc is less than 16-bit immediate value. The operands are treated as signed 32-bit values.
3 3-32 M32R-FPU Software Manual (Rev.1.01) CMPU [Mnemonic] CMPU Rsrc1,Rsrc2 [Function] Compare C = ( ( unsigned ) Rsrc1 < ( unsigned ) Rsrc2 ) ? 1:0; [Description] The condition bit (C) is set when Rsrc1 is less than Rsrc2. The operands are treated as un- signed 32-bit values.
3 3-33 M32R-FPU Software Manual (Rev.1.01) CMPUI [Mnemonic] CMPUI Rsrc,#imm16 [Function] Compare C = ( ( unsigned ) Rsrc < ( unsigned ) ( ( signed short ) imm16 ) ) ? 1:0; [Description] The condition bit (C) is set when Rsrc is less than the 16-bit immediate value.
3 3-34 M32R-FPU Software Manual (Rev.1.01) dest 1001 src 0000 0000 0000 0000 0000 DIV Rdest,Rsrc DIV [Mnemonic] DIV Rdest,Rsrc [Function] Signed division Rdest = ( signed ) Rdest / ( signed ) Rsrc; [Description] DIV divides Rdest by Rsrc and puts the quotient in Rdest.
3 3-35 M32R-FPU Software Manual (Rev.1.01) DIVU [Mnemonic] DIVU Rdest,Rsrc [Function] Unsigned division Rdest = ( unsigned ) Rdest / ( unsigned ) Rsrc; [Description] DIVU divides Rdest by Rsrc and puts the quotient in Rdest. The operands are treated as unsigned 32-bit values and the result is rounded toward zero.
3 3-36 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FADD FADD [Mnemonic] FADD Rdest,Rsrc1,Rsrc2 [Function] Floating-point add Rdest = Rsrc1 + Rsrc2 ; [Description] Add the floating-point single precision values stored in Rsrc1 and Rsrc2 and store the result in Rdest.
3 3-37 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and DN = 1.
3 3-38 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FCMP FCMP src1 1101 src2 0000 dest 0000 0000 1100 FCMP Rdest,Rsrc1,Rsrc2 [Mnemonic] FCMP Rdest,Rsrc1,Rsrc2 [Function.
3 3-39 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and DN = 1.
3 3-40 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FCMPE FCMPE src1 1101 src2 0000 dest 0000 0000 1101 FCMPE Rdest,Rsrc1,Rsrc2 [Mnemonic] FCMPE Rdest,Rsrc1,Rsrc2 [Func.
3 3-41 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and DN = 1.
3 3-42 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FDIV FDIV [Mnemonic] FDIV Rdest,Rsrc1,Rsrc2 [Function] Floating-point divide Rdest = Rsrc1 / Rsrc2 ; [Description] D.
3 3-43 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and DN = 1.
3 3-44 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FMADD FMADD [Mnemonic] FMADD Rdest,Rsrc1,Rsrc2 [Function] Floating-point multiply and add Rdest = Rdest + Rsrc1 * Rsrc2 ; [Description] This instruction is executed in the following 2 steps.
3 3-45 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The following shows the values of Rsrc1, Rsrc2 and Rdest and the operation results when DN = 0 and DN = 1.
3 3-46 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description DN=1 Value after Multiplication Operation Value after Addition Operation IVLD: Invalid Operation Exception UIPL: Uni.
3 3-47 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FMSUB FMSUB [Mnemonic] FMSUB Rdest,Rsrc1,Rsrc2 [Function] Floating-point multiply and subtract Rdest = Rdest - Rsrc1 * Rsrc2 ; [Description] This instruction is executed in the following 2 steps.
3 3-48 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The following shows the values of Rsrc1, Rsrc2 and Rdest and the operation results when DN = 0 and DN = 1.
3 3-49 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description DN=1 Value after Multiplication Operation Value after Subtraction Operation IVLD: Invalid Operation Exception UIPL: .
3 3-50 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FMUL FMUL [Mnemonic] FMUL Rdest,Rsrc1,Rsrc2 [Function] Floating-point multiply Rdest = Rsrc1 * Rsrc2 ; [Description].
3 3-51 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and DN = 1.
3 3-52 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FSUB FSUB [Mnemonic] FSUB Rdest,Rsrc1,Rsrc2 [Function] Floating-point subtract Rdest = Rsrc1 - Rsrc2 ; [Description].
3 3-53 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description Rsrc2 Subtraction UIPL QNaN QNaN SNaN QNaN SNaN +0 +0 +0 (Note) (Note) +Infinity +Infinity IVLD IVLD IVLD -Infinity .
3 3-54 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FTOI FTOI [Mnemonic] FTOI Rdest,Rsrc [Function] Convert the floating-point single precision value to 32-bit integer.
3 3-55 M32R-FPU Software Manual (Rev.1.01) [Supplemental Operation Description] The results of the FTOI instruction executed based on the Rsrc value, both when DN = 0 and DN = 1, are shown in below.
3 3-56 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description FTOS FTOS [Mnemonic] FTOS Rdest,Rsrc [Function] Convert the floating-point single precision value to 16-bit integer.
3 3-57 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description [Supplemental Operation Description] The results of the FTOS instruction executed based on the Rsrc value, both when DN = 0 and DN = 1, are shown in below.
3 3-58 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description ITOF ITOF [Mnemonic] ITOF Rdest,Rsrc [Function] Convert the integer to a floating-point single precision value. Rdes = (float) Rsrc ; [Description] Converts the 32-bit integer stored in Rsrc to a floating-point single precision value and stores the result in Rdest.
3 3-59 M32R-FPU Software Manual (Rev.1.01) JL JL branch instruction Jump and link [Mnemonic] JL Rsrc [Function] Subroutine call (register direct) R14 = ( PC & 0xfffffffc ) + 4; PC = Rsrc & 0xfffffffc; [Description] JL causes an unconditional jump to the address specified by Rsrc and puts the return address in R14.
3 3-60 M32R-FPU Software Manual (Rev.1.01) JMP JMP branch instruction Jump [Mnemonic] JMP Rsrc [Function] Jump PC = Rsrc & 0xfffffffc; [Description] JMP causes an unconditional jump to the address specified by Rsrc. The condition bit (C) is unchanged.
3 3-61 M32R-FPU Software Manual (Rev.1.01) LD LD load/store instruction Load [Mnemonic] (1) LD Rdest,@Rsrc (2) LD Rdest,@Rsrc+ (3) LD Rdest,@(disp16,Rsrc) [Function] Load to register from the contents of the memory.
3 3-62 M32R-FPU Software Manual (Rev.1.01) LD24 LD24 load/store instruction Load 24-bit immediate [Mnemonic] LD24 Rdest,#imm24 [Function] Load the 24-bit immediate value into register. Rdest = imm24 & 0x00ffffff; [Description] LD24 loads the 24-bit immediate value into Rdest.
3 3-63 M32R-FPU Software Manual (Rev.1.01) LDB LDB load/store instruction Load byte [Mnemonic] (1) LDB Rdest,@Rsrc (2) LDB Rdest,@(disp16,Rsrc) [Function] Load to register from the contents of the memory.
3 3-64 M32R-FPU Software Manual (Rev.1.01) LDH LDH load/store instruction Load halfword [Mnemonic] (1) LDH Rdest,@Rsrc (2) LDH Rdest,@(disp16,Rsrc) [Function] Load to register from the contents of the memory.
3 3-65 M32R-FPU Software Manual (Rev.1.01) LDI LDI transfer instruction Load immediate [Mnemonic] (1) LDI Rdest,#imm8 (2) LDI Rdest,#imm16 [Function] Load the immediate value into register. (1) Rdest = ( signed char ) imm8; (2) Rdest = ( signed short ) imm16; [Description] (1) LDI loads the 8-bit immediate value into Rdest.
3 3-66 M32R-FPU Software Manual (Rev.1.01) LDUB LDUB load/store instruction Load unsigned byte [Mnemonic] (1) LDUB Rdest,@Rsrc (2) LDUB Rdest,@(disp16,Rsrc) [Function] Load to register from the contents of the memory.
3 3-67 M32R-FPU Software Manual (Rev.1.01) LDUH LDUH load/store instruction Load unsigned halfword [Mnemonic] (1) LDUH Rdest,@Rsrc (2) LDUH Rdest,@(disp16,Rsrc) [Function] Load to register from the contents of the memory.
3 3-68 M32R-FPU Software Manual (Rev.1.01) LOCK LOCK load/store instruction Load locked [Mnemonic] LOCK Rdest,@Rsrc [Function] Load locked LOCK = 1, Rdest = *( int *) Rsrc; [Description] The contents of the word at the memory location specified by Rsrc are loaded into Rdest.
3 3-69 M32R-FPU Software Manual (Rev.1.01) MACHI MACHI DSP function instruction Multiply-accumulate high-order halfwords [Mnemonic] MACHI Rsrc1,Rsrc2 [Function] Multiply and add accumulator += (( sign.
3 3-70 M32R-FPU Software Manual (Rev.1.01) MACLO MACLO DSP function instruction Multiply-accumulate low-order halfwords [Mnemonic] MACLO Rsrc1,Rsrc2 [Function] Multiply and add accumulator += ( ( sign.
3 3-71 M32R-FPU Software Manual (Rev.1.01) MACWHI MACWHI DSP function instruction Multiply-accumulate word and high-order halfword [Mnemonic] MACWHI Rsrc1,Rsrc2 [Function] Multiply and add accumulator.
3 3-72 M32R-FPU Software Manual (Rev.1.01) MACWLO MACWLO DSP function instruction Multiply-accumulate word and low-order halfword [Mnemonic] MACWLO Rsrc1,Rsrc2 [Function] Multiply and add accumulator .
3 3-73 M32R-FPU Software Manual (Rev.1.01) MUL MUL multiply and divide instruction Multiply [Mnemonic] MUL Rdest,Rsrc [Function] Multiply { signed64bit tmp; tmp = ( signed64bit ) Rdest * ( signed64bit ) Rsrc; Rdest = ( int ) tmp;} [Description] MUL multiplies Rdest by Rsrc and puts the result in Rdest.
3 3-74 M32R-FPU Software Manual (Rev.1.01) MULHI MULHI DSP function instruction Multiply high-order halfwords [Mnemonic] MULHI Rsrc1,Rsrc2 [Function] Multiply accumulator = (( signed) (Rsrc1 & 0xf.
3 3-75 M32R-FPU Software Manual (Rev.1.01) MULLO MULLO DSP function instruction Multiply low-order halfwords [Mnemonic] MULLO Rsrc1,Rsrc2 [Function] Multiply accumulator = ( ( signed ) ( Rsrc1 <<.
3 3-76 M32R-FPU Software Manual (Rev.1.01) MULWHI MULWHI DSP function instruction Multiply word and high-order halfword [Mnemonic] MULWHI Rsrc1,Rsrc2 [Function] Multiply accumulator = ( ( signed ) Rsr.
3 3-77 M32R-FPU Software Manual (Rev.1.01) MULWLO MULWLO DSP fucntion instruction Multiply word and low-order halfword [Mnemonic] MULWLO Rsrc1,Rsrc2 [Function] Multiply accumulator = ( ( signed ) Rsrc.
3 3-78 M32R-FPU Software Manual (Rev.1.01) MV MV transfer instruction Move register [Mnemonic] MV Rdest,Rsrc [Function] Transfer Rdest = Rsrc; [Description] MV moves Rsrc to Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] dest 0001 M V Rdest,Rsrc src 1000 INSTRUCTIONS 3.
3 3-79 M32R-FPU Software Manual (Rev.1.01) MVFACHI MVFACHI DSP function instruction Move high-order word from accumulator [Mnemonic] MVFACHI Rdest [Function] Transfer from accumulator to register Rdest = ( int ) ( accumulator >> 32 ) ; [Description] MVFACHI moves the high-order 32 bits of the accumulator to Rdest.
3 3-80 M32R-FPU Software Manual (Rev.1.01) MVFACLO MVFACLO DSP function instruction Move low-order word from accumulator [Mnemonic] MVFACLO Rdest [Function] Transfer from accumulator to register Rdest = ( int ) accumulator [Description] MVFACLO moves the low-order 32 bits of the accumulator to Rdest.
3 3-81 M32R-FPU Software Manual (Rev.1.01) MVFACMI MVFACMI DSP function instruction Move middle-order word from accumulator [Mnemonic] MVFACMI Rdest [Function] Transfer from accumulator to register Rdest = ( int ) ( accumulator >> 16 ) ; [Description] MVFACMI moves bits16 through 47 of the accumulator to Rdest.
3 3-82 M32R-FPU Software Manual (Rev.1.01) MVFC MVFC transfer instruction Move from control register [Mnemonic] MVFC Rdest,CRsrc [Function] Transfer from control register to register Rdest = CRsrc ; [Description] MVFC moves CRsrc to Rdest. The condition bit (C) is unchanged.
3 3-83 M32R-FPU Software Manual (Rev.1.01) MVTACHI MVTACHI DSP function instruction Move high-order word to accumulator [Mnemonic] MVTACHI Rsrc [Function] Transfer from register to accumulator accumulator [ 0 : 31 ] = Rsrc ; [Description] MVTACHI moves Rsrc to the high-order 32 bits of the accumulator.
3 3-84 M32R-FPU Software Manual (Rev.1.01) MVTACLO MVTACLO DSP function instruction Move low-order word to accumulator [Mnemonic] MVTACLO Rsrc [Function] Transfer from register to accumulator accumulator [ 32 : 63 ] = Rsrc ; [Description] MVTACLO moves Rsrc to the low-order 32 bits of the accumulator.
3 3-85 M32R-FPU Software Manual (Rev.1.01) MVTC MVTC transfer instruction Move to control register [Mnemonic] MVTC Rsrc,CRdest [Function] Transfer from register to control register CRdest = Rsrc ; [Description] MVTC moves Rsrc to CRdest. If PSW(CR0) is specified as CRdest, the condition bit (C) is changed; otherwise it is un- changed.
3 3-86 M32R-FPU Software Manual (Rev.1.01) NEG NEG arithmetic operation instruction Negate [Mnemonic] NEG Rdest,Rsrc [Function] Negate Rdest = 0 – Rsrc ; [Description] NEG negates (changes the sign of) Rsrc treated as a signed 32-bit value, and puts the result in Rdest.
3 3-87 M32R-FPU Software Manual (Rev.1.01) NOP NOP branch instruction No operation [Mnemonic] NOP [Function] No operation /* */ [Description] NOP performs no operation. The subsequent instruction then processed. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] NOP 0000 0111 0000 0000 INSTRUCTIONS 3.
3 3-88 M32R-FPU Software Manual (Rev.1.01) NOT NOT logic operation instruction Logical NOT [Mnemonic] NOT Rdest,Rsrc [Function] Logical NOT Rdest = ~ Rsrc ; [Description] NOT inverts each of the bits of Rsrc and puts the result in Rdest. The condition bit (C) is unchanged.
3 3-89 M32R-FPU Software Manual (Rev.1.01) OR OR logic operation instruction OR [Mnemonic] OR Rdest,Rsrc [Function] Logical OR Rdest = Rdest | Rsrc ; [Description] OR computes the logical OR of the corresponding bits of Rdest and Rsrc, and puts the result in Rdest.
3 3-90 M32R-FPU Software Manual (Rev.1.01) OR3 OR3 logic operation instruction OR 3-operand [Mnemonic] OR3 Rdest,Rsrc,#imm16 [Function] Logical OR Rdest = Rsrc | ( unsigned short ) imm16 ; [Descriptio.
3 3-91 M32R-FPU Software Manual (Rev.1.01) RAC RAC DSP function instruction Round accumulator [Mnemonic] RAC [Function] Saturation Process { signed64bit tmp; tmp = ( signed64bit ) accumulator <<.
3 3-92 M32R-FPU Software Manual (Rev.1.01) [Supplement] This instruction is executed in two steps as shown below: <step 1> <step 2> The value in the accumulator is altered depending on the supposed bit 80 through 7 after left-shift operation and bit 8 through bit 63 after shift operation.
3 3-93 M32R-FPU Software Manual (Rev.1.01) RACH RACH DSP function instruction Round accumulator halfword [Mnemonic] RACH [Function] Saturation Process { signed64bit tmp; tmp = ( signed64bit ) accumula.
3 3-94 M32R-FPU Software Manual (Rev.1.01) [Supplement] This instruction is executed in two steps, as shown below. <proccess 1> <proccess 2> The value in the accumulator is altered depending on the supposed bit 80 through 7 after left-shift operation and bit 8 through bit 63 after shift operation.
3 3-95 M32R-FPU Software Manual (Rev.1.01) REM REM multiply and divide instruction Remainder [Mnemonic] REM Rdest,Rsrc [Function] Signed remainder Rdest = ( signed ) Rdest % ( signed ) Rsrc ; [Description] REM divides Rdest by Rsrc and puts the quotient in Rdest.
3 3-96 M32R-FPU Software Manual (Rev.1.01) REMU REMU multiply and divide instruction Remainder unsigned [Mnemonic] REMU Rdest,Rsrc [Function] Unsigned remainder Rdest = ( unsigned ) Rdest % ( unsigned ) Rsrc ; [Description] REMU divides Rdest by Rsrc and puts the quotient in Rdest.
3 3-97 M32R-FPU Software Manual (Rev.1.01) RTE RTE EIT-related instruction Return from EIT [Mnemonic] RTE [Function] Return from EIT SM = BSM ; IE = BIE ; C = BC ; PC = BPC & 0xfffffffc ; [Description] RTE restores the SM, IE and C bits of the PSW from the BSM, BIE and BC bits, and jumps to the address specified by BPC.
3 3-98 M32R-FPU Software Manual (Rev.1.01) SETH SETH Transfer instructions Set high-order 16-bit [Mnemonic] SETH Rdest,#imm16 [Function] Transfer instructions Rdest = ( signed short ) imm16 << 16 ; [Description] SETH load the immediate value into the 16 most significant bits of Rdest.
3 3-99 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description SETPSW SETPSW Bit Operation Instructions Set PSW [M32R-FPU Extended Instruction] [Mnemonic] SETPSW #imm8 [Function] Set the undefined SM, IE, anc C bits of PSW to 1.
3 3-100 M32R-FPU Software Manual (Rev.1.01) SLL SLL shift instruction Shift left logical [Mnemonic] SLL Rdest,Rsrc [Function] Logical left shift Rdest = Rdest << ( Rsrc & 31 ) ; [Description] SLL left logical-shifts the contents of Rdest by the number specified by Rsrc, shifting zeroes into the least significant bits.
3 3-101 M32R-FPU Software Manual (Rev.1.01) SLL3 SLL3 shift instruction Shift left logical 3-operand [Mnemonic] SLL3 Rdest,Rsrc,#imm16 [Function] Logical left shift Rdest = Rsrc << ( imm16 &.
3 3-102 M32R-FPU Software Manual (Rev.1.01) SLLI SLLI shift instruction Shift left logical immediate [Mnemonic] SLLI Rdest,#imm5 [Function] Logical left shift Rdest = Rdest << imm5 ; [Descriptio.
3 3-103 M32R-FPU Software Manual (Rev.1.01) SRA SRA shift instruction Shift right arithmetic [Mnemonic] SRA Rdest,Rsrc [Function] Arithmetic right shift Rdest = ( signed ) Rdest >> ( Rsrc & .
3 3-104 M32R-FPU Software Manual (Rev.1.01) SRA3 SRA3 shift instruction Shift right arithmetic 3-operand [Mnemonic] SRA3 Rdest,Rsrc,#imm16 [Function] Arithmetic right shift Rdest = ( signed ) Rsrc >.
3 3-105 M32R-FPU Software Manual (Rev.1.01) SRAI SRAI shift instruction Shift right arithmetic immediate [Mnemonic] SRAI Rdest,#imm5 [Function] Arithmetic right shift Rdest = ( signed ) Rdest >>.
3 3-106 M32R-FPU Software Manual (Rev.1.01) SRL SRL shift instruction Shift right logical [Mnemonic] SRL Rdest,Rsrc [Function] Logical right shift Rdest = ( unsigned ) Rdest >> ( Rsrc & 31 ).
3 3-107 M32R-FPU Software Manual (Rev.1.01) SRL3 SRL3 shift instruction Shift right logical 3-operand [Mnemonic] SRL3 Rdest,Rsrc,#imm16 [Function] Logical right shift Rdest = ( unsigned ) Rsrc >>.
3 3-108 M32R-FPU Software Manual (Rev.1.01) SRLI SRLI shift instruction Shift right logical immediate [Mnemonic] SRLI Rdest,#imm5 [Function] Logical right shift Rdest = ( unsigned ) Rdest >> ( i.
3 3-109 M32R-FPU Software Manual (Rev.1.01) ST ST load/store instruction Store [Mnemonic] (1) ST Rsrc1,@Rsrc2 (2) ST Rsrc1,@+Rsrc2 (3) ST Rsrc1,@-Rsrc2 (4) ST Rsrc1,@(disp16,Rsrc2) [Function] Store (1.
3 3-110 M32R-FPU Software Manual (Rev.1.01) [Encoding] src1 1010 src1 0010 0111 src2 0100 src2 disp16 src1 0010 0110 src2 src1 0010 0100 src2 ST Rsrc1,@Rsrc2 ST Rsrc1,@+Rsrc2 ST Rsrc1,@-Rsrc2 ST Rsrc1,@(disp16,Rsrc2) INSTRUCTIONS 3.
3 3-111 M32R-FPU Software Manual (Rev.1.01) STB STB load/store instruction Store byte [Mnemonic] (1) STB Rsrc1,@Rsrc2 (2) STB Rsrc1,@(disp16,Rsrc2) [Function] Store (1) * ( char *) Rsrc2 = Rsrc1; (2) .
3 3-112 M32R-FPU Software Manual (Rev.1.01) STH STH load/store instruction Store halfword [M32R-FPU Extended Mnemonic] [Mnemonic] (1) STH Rsrc1,@Rsrc2 (2) STH Rsrc1,@Rsrc2+ [M32R-FPU Extended Mnemonic.
3 3-113 M32R-FPU Software Manual (Rev.1.01) SUB SUB arithmetic operation instruction Subtract [Mnemonic] SUB Rdest,Rsrc [Function] Subtract Rdest = Rdest - Rsrc; [Description] SUB subtracts Rsrc from Rdest and puts the result in Rdest. The condition bit (C) is unchanged.
3 3-114 M32R-FPU Software Manual (Rev.1.01) SUBV SUBV arithmetic operation instruction Subtract with overflow checking [Mnemonic] SUBV Rdest,Rsrc [Function] Subtract Rdest = Rdest - Rsrc; C = overflow ? 1 : 0; [Description] SUBV subtracts Rsrc from Rdest and puts the result in Rdest.
3 3-115 M32R-FPU Software Manual (Rev.1.01) SUBX SUBX arithmetic operation instruction Subtract with borrow [Mnemonic] SUBX Rdest,Rsrc [Function] Subtract Rdest = ( unsigned ) Rdest - ( unsigned ) Rsrc - C; C = borrow ? 1 : 0; [Description] SUBX subtracts Rsrc and C from Rdest and puts the result in Rdest.
3 3-116 M32R-FPU Software Manual (Rev.1.01) TRAP TRAP EIT-related instruction Trap [Mnemonic] TRAP #imm4 [Function] Trap occurrence BPC = PC + 4; BSM = SM; BIE = IE; BC = C ; IE = 0; C = 0; call_trap_handler( imm4 ); [Description] TRAP generates a trap with the trap number specified by the 4-bit immediate value.
3 3-117 M32R-FPU Software Manual (Rev.1.01) UNLOCK UNLOCK load/store instruction Store unlocked [Mnemonic] UNLOCK Rsrc1,@Rsrc2 [Function] Store unlocked if ( LOCK == 1 ) { * ( int *) Rsrc2 = Rsrc1; } LOCK = 0; [Description] When the LOCK bit is 1, the contents of Rsrc1 are stored at the memory location specified by Rsrc2.
3 3-118 M32R-FPU Software Manual (Rev.1.01) INSTRUCTIONS 3.2 Instruction description UTOF UTOF Floating Point Instructions Unsigned integer to float [M32R-FPU Extended Instruction] [Mnemonic] UTOF Rdest,Rsrc [Function] Convert from unsigned integer to floating-point single precision value.
3 3-119 M32R-FPU Software Manual (Rev.1.01) XOR XOR logic operation instruction Exclusive OR [Mnemonic] XOR Rdest,Rsrc [Function] Exclusive OR Rdest = ( unsigned ) Rdest ^ ( unsigned ) Rsrc; [Description] XOR computes the logical XOR of the corresponding bits of Rdest and Rsrc, and puts the result in Rdest.
3 3-120 M32R-FPU Software Manual (Rev.1.01) XOR3 XOR3 logic operation instruction Exclusive OR 3-operand [Mnemonic] XOR3 Rdest,Rsrc,#imm16 [Function] Exclusive OR Rdest = ( unsigned ) Rsrc ^ ( unsigne.
APPENDICES APPENDIX 1 Hexadecimal Instraction Code APPENDIX 2 Instruction List APPENDIX 3 Pipeline Processing APPENDIX 4 Instruction Execution Time APPENDIX 5 IEEE754 Specification Overview APPENDIX 6.
APPENDICES APPENDICES-2 M32R-FPU Software Manual (Rev.1.01) Appendix1 Hexadecimal Instraction Code The bit pattern of each instruction and correspondence of mnemonic are shown below. The instructions enclosed in the bold lines are M32R-FPU extended instructions.
APPENDICES APPENDICES-3 M32R-FPU Software Manual (Rev.1.01) 1000 1001 1010 101 1 1100 11 0 1 111 0 1111 89 BC DE F A b 8 -b 11 b 0 -b 3 hexadecimal numeral 16-bit instruction 32-bit instruction ADDV R.
APPENDICES APPENDICES-4 M32R-FPU Software Manual (Rev.1.01) mnemonic function condition bit (C) ADD Rdest,Rsrc Rdest = Rdest + Rsrc – ADD3 Rdest,Rsrc,#imm16 Rdest = Rsrc + (sh)imm16 – ADDI Rdest,#.
APPENDICES APPENDICES-5 M32R-FPU Software Manual (Rev.1.01) mnemonic function condition bit (C) FMADD Rdest,Rsrc1,Rsrc2 Rdest = Rdest + Rsrc1 * Rsrc2 – FMSUB Rdest,Rsrc1,Rsrc2 Rdest = Rdest - Rsrc1 .
APPENDICES APPENDICES-6 M32R-FPU Software Manual (Rev.1.01) mnemonic function condition bit (C) NEG Rdest,Rsrc Rdest = 0 - Rsrc – NOP /*no-operation*/ – NOT Rdest,Rsrc Rdest = ~ Rsrc – OR Rdest,.
APPENDICES APPENDICES-7 M32R-FPU Software Manual (Rev.1.01) where: typedef singed int s; /* 32 bit signed integer (word)*/ typedef unsigned int u; /* 32 bit unsigned integer (word)*/ typedef signed sh.
APPENDICES APPENDICES-8 M32R-FPU Software Manual (Rev.1.01) Appendix 3 Pipeline Processing Appendix 3.1 Instructions and Pipeline Processing Appendix Figure 3.
APPENDICES APPENDICES-9 M32R-FPU Software Manual (Rev.1.01) The overview of each pipeline stage is shown below. ● IF stage (instruction fetch stage) The instruction fetch (IF) is processed in this stage. There is an instruction queue and instructions are fetched until the queue is full regardless of the completion of decoding in the D stage.
APPENDICES APPENDICES-10 M32R-FPU Software Manual (Rev.1.01) Appendix Figure 3.2.1 Pipeline Flow with no Stall (1) Appendix 3.2 Pipeline Basic Operation (1) Pipeline Flow with no Stall The following diagram shows an ideal pipeline flow that has no stall and executes each instruction in 1 clock cycle.
APPENDICES APPENDICES-11 M32R-FPU Software Manual (Rev.1.01) Appendix Figure 3.2.2 Pipeline Flow with no Stall (2) <Case 4> Three FPU instructions continue consecutively with no register depende.
APPENDICES APPENDICES-12 M32R-FPU Software Manual (Rev.1.01) (2) Pipeline Flow with Stalls A pipeline stage may stall due to execution of a process or branch instruction.
APPENDICES APPENDICES-13 M32R-FPU Software Manual (Rev.1.01) Appendix Figure 3.2.4 Pipeline Flow with Stalls (2) <Case 3> A branch instruction is executed (except for the case in which no branch.
APPENDICES APPENDICES-14 M32R-FPU Software Manual (Rev.1.01) Appendix Figure 3.2.5 Pipeline Flow with Stalls (3) <Case 6> FPSR is accessed by an MVFC instruction after the FPU instruction is exe.
APPENDICES APPENDICES-15 M32R-FPU Software Manual (Rev.1.01) Appendix Figure 3.2.6 Pipeline Flow with Stalls (4) <Case 8> The FPU and integer instructions run consecutively (with no register dep.
APPENDICES APPENDICES-16 M32R-FPU Software Manual (Rev.1.01) Appendix Figure 3.2.7 Pipeline Flow with Stalls (5) <Case 12> The FPU and FMADD/FMSUB instructions run consecutively (with no registe.
APPENDICES APPENDICES-17 M32R-FPU Software Manual (Rev.1.01) Appendix 4 Instruction Execution Time Normally, the E stage is considered as representing as the instruction execution time, however, because of the pipeline processing the execution time for other stages may effect the total instruction execution time.
APPENDICES APPENDICES-18 M32R-FPU Software Manual (Rev.1.01) Appendix 5 IEEE754 Specification Overview The following is a basic overview of the IEEE754 specification. M32R-FPU fulfills the IEEE754 requirements through a combination of software and hardware features.
APPENDICES APPENDICES-19 M32R-FPU Software Manual (Rev.1.01) APPENDIX 5 Appendix 5 IEEE754 Specification Overview Appendix Table 5.1.1 Single Precision Floating-Point Bit Values Exponent Expressed val.
APPENDICES APPENDICES-20 M32R-FPU Software Manual (Rev.1.01) APPENDIX 5 Appendix 5 IEEE754 Specification Overview Appendix 5.2 Rounding The following 4 rounding modes are specified by IEEE754.
APPENDICES APPENDICES-21 M32R-FPU Software Manual (Rev.1.01) (2) Underflow Exception (UDF) The exception occurs when the absolute value of the operation result is less then the largest describable precision in the floating-point format. Appendix Table 5.
APPENDICES APPENDICES-22 M32R-FPU Software Manual (Rev.1.01) APPENDIX 5 Appendix 5 IEEE754 Specification Overview (5) Invalid Operation Exception (IVLD) The exception occurs when an invalid operation is executed. Appendix Table 5.3.5 shows operation results and the respective conditions in which each IVLD occurs.
APPENDICES APPENDICES-23 M32R-FPU Software Manual (Rev.1.01) Appendix 6 M32R-FPU Specification Supplemental Explanation Appendix 6.1 Operation Comparision: Using 1 instruction (FMADD or FMSBU) vs.
APPENDICES APPENDICES-24 M32R-FPU Software Manual (Rev.1.01) (1) Overflow occurs in Step 1 <When EO = 0, EX = 0: OVF and IXCT occur> Type of R0 Condition FMUL + FADD Operation FMADD Operation No.
APPENDICES APPENDICES-25 M32R-FPU Software Manual (Rev.1.01) (2) When underflow occurs in Step 1 <When EU = 0, DN = 1: UDF occurs> Type of R0 Condition FMUL + FADD Operation FMADD Operation Norm.
APPENDICES APPENDICES-26 M32R-FPU Software Manual (Rev.1.01) APPENDIX 6 Appendix 6 M32R-FPU Specification Supplemental Explanation (3) When Invalid Operation Exception occurs in Step 1 ■ If at least.
APPENDICES APPENDICES-27 M32R-FPU Software Manual (Rev.1.01) (4) When Inexact Operation Exception occurs in Step 1 ■ If an Inexact Operation occurs due to rounding: <When EX = 0: IXCT occurs> .
APPENDICES APPENDICES-28 M32R-FPU Software Manual (Rev.1.01) APPENDIX 6 Appendix 6 M32R-FPU Specification Supplemental Explanation Appendix 6.2 Rules concerning Generation of QNaN in M32R-FPU The following are rules concerning generating a QNaN as an operation result.
APPENDICES APPENDICES-29 M32R-FPU Software Manual (Rev.1.01) Appendix 7 Precautions Appendix 7.1 Precautions to be taken when aligning data When aligning or allocating the data area following the code area in a program, the alignment must be done from an address that has an adjusted word alignment.
APPENDICES APPENDICES-30 M32R-FPU Software Manual (Rev.1.01) This page left blank intentionally. APPENDIX 7 Appendix 7 Precautions.
INDEX.
INDEX INDEX-2 M32R-FPU Software Manual (Rev.1.01) Symbol #imm 1-15, 3-2 @(disp,R) 1-15, 3-2 @+R 1-15, 3-2 @-R 1-15, 3-2 @R 1-15, 3-2 @R+ 1-15, 3-2 A Accumulator(ACC) 1-11 Addressing Mode 1-15, 3-2 Ari.
INDEX INDEX-3 M32R-FPU Software Manual (Rev.1.01) L Load/store instructions 2-2 LD 3-61 LDB 3-63 LDH 3-64 LDUB 3-66 LDUH 3-67 LOCK 3-68 ST 3-109 STB 3-111 STH 3-112 UNLOCK 3-117 Logic operation instru.
INDEX INDEX-4 M32R-FPU Software Manual (Rev.1.01) R R 1-15, 3-2 Register direct(R or CR) 1-15, 3-2 Register indirect(@R) 1-15, 3-2 Register indirect and register update 1-15, 3-2 Register relative ind.
RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER SOFTWARE MANUAL M32R-FPU Publication Data : Rev.1.00 Jan 08, 2003 Rev.1.01 Oct 31, 2003 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2003. Renesas Technology Corp., All rights reserved.
M32R Family Software Manual 2- 6 -2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan.
Een belangrijk punt na aankoop van elk apparaat Renesas M32R-FPU (of zelfs voordat je het koopt) is om de handleiding te lezen. Dit moeten wij doen vanwege een paar simpele redenen:
Als u nog geen Renesas M32R-FPU heb gekocht dan nu is een goed moment om kennis te maken met de basisgegevens van het product. Eerst kijk dan naar de eerste pagina\'s van de handleiding, die je hierboven vindt. Je moet daar de belangrijkste technische gegevens Renesas M32R-FPU vinden. Op dit manier kan je controleren of het apparaat aan jouw behoeften voldoet. Op de volgende pagina's van de handleiding Renesas M32R-FPU leer je over alle kenmerken van het product en krijg je informatie over de werking. De informatie die je over Renesas M32R-FPU krijgt, zal je zeker helpen om een besluit over de aankoop te nemen.
In een situatie waarin je al een beziter van Renesas M32R-FPU bent, maar toch heb je de instructies niet gelezen, moet je het doen voor de hierboven beschreven redenen. Je zult dan weten of je goed de alle beschikbare functies heb gebruikt, en of je fouten heb gemaakt die het leven van de Renesas M32R-FPU kunnen verkorten.
Maar de belangrijkste taak van de handleiding is om de gebruiker bij het oplossen van problemen te helpen met Renesas M32R-FPU . Bijna altijd, zal je daar het vinden Troubleshooting met de meest voorkomende storingen en defecten #MANUAl# samen met de instructies over hun opplosinge. Zelfs als je zelf niet kan om het probleem op te lossen, zal de instructie je de weg wijzen naar verdere andere procedure, bijv. door contact met de klantenservice of het dichtstbijzijnde servicecentrum.
