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- 1 - M391B5773DH0 M391B5273DH0 Rev . 1.0, Sep. 2010 SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMA TION AND SPECIFICA TIONS WITHOUT NOTI CE.
- 2 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM Rev ision History Revision No. History Draft Date Remark Editor 1.0 - First Release Sep. 2010 - S.
- 3 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM Table Of Contents 240pin Unbuffered DIM M based on 2Gb D-die 1. DDR3L Unbuffered DIMM Ordering In formation ........ .......................................... ............ ........... ......... ..
- 4 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 1. DDR3L Unbuff ered DIMM Ordering Inf ormation NOTE : 1. "##" - F8/H9/K0 2. F8 - 1066Mbps 7-7-7 / H9 - 1333Mbp s 9-9-9 / K0 - 1600Mbps .
- 5 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 4. x72 DIMM Pin Configurations (F r ont side/Back side) NOTE : NC = No Connect; NU = Not Used; RFU = Reserved Future Use 1. S1 , ODT1, CKE1: Used for dual-r ank UDIMMs; NC on single-rank UDIMMs 2. CK1,NC and CK1 ,NC : Used for dual-rank UDIMMs; not used on single-rank UDIMMs, but terminated 3.
- 6 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 5. Pin Descr iption NOTE : * The V DD and V DDQ pins are tied common to a single power-plane on these designs.
- 7 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 7. Input /Output F unctional Description NOTE : 1. DM8, DQS8 and DQS 8 are for ECC UDIMM only . Symbol Ty p e Funct ion CK0-CK 1 CK 0-CK 1 SSTL CK and CK are differential clock inputs.
- 8 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 7.1 Address Mirror ing F eature Figure 1. Wiring Differences for Mirrored and No n-Mirrored Addresses There is a via grid located under the DRAMs for wiring the CA sign als (address, bank address, command, and control lines) to th e DRAM pins.
- 9 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 8. F unction Block Diagr am: 8.1 2GB, 256Mx72 ECC Mo dule (Popu lated as 1 rank of x8 DDR3 SDRAMs) S0 DQS0 DQS0 DM0 DM CS DQS DQS DQ0 DQ1 DQ2 DQ3 .
- 10 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 8.2 4GB, 512Mx72 ECC Modu le (Populat ed as 2 r anks of x8 DDR3 SDRAMs) S0 DQS0 DQS0 DM0 DM CS DQS DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O .
- 11 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 9. Abso lute Maximum Ratings 9.1 Absolute Maximum DC Ratings NOTE : 1. S tresses greater th an those listed under “A bsolute Maximum Rating s” may cause p ermanent damage to the d evice.
- 12 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 11. AC & DC Input Measurement Levels 11.1 AC & DC Logic Input Leve ls for Single-ended Signals [ T able 2 ] Single Ended AC and DC input leve ls for Command and Ad dress NOTE : 1. For input o nly pins except RESET , V REF = V REFCA (DC) 2.
- 13 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM [ T able 3 ] Single Ended AC and DC input leve ls for DQ and DM NOTE : 1. For input o nly pins except RESET , V REF = V REFDQ (DC) 2.
- 14 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 11.2 V REF T o lerances The dc-tolerance limits and ac-noise limits for the reference voltages V REFCA and V REFDQ are illustrate in Figure 2. It shows a valid reference voltage V REF (t) as a function of time.
- 15 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 11.3 AC and DC Logic Input Levels f or Diff erential Signals 11.3.1 Diff erential Signa ls Definition Figure 3. Definition of dif ferential ac-swing and "time abo ve ac level" tDV AC 11.
- 16 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM [ T able 4 ] Allowed time before ringback (tDV AC) for CK - CK and DQS - DQS (1.35V) [ T able 5 ] Allowed time before ringback (tDV AC) for CK - CK and DQS - DQS (1.5V) Slew Rate [V/ns] tDV AC [p s] @ |V IH/Ldiff (AC)| = 320mV tDV AC [ps] @ |V IH/ Ldiff (AC)| = 270mV min max min max > 4.
- 17 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 11.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, CK , DQS ) has also to comply with cert ain requirements for single-ended signals.
- 18 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 11.3.4 Different ial Input Cross Poi nt Voltage T o guarantee tight setup and hold times as well a s output skew para meters with respect to clock and strob e, each cross point vo ltage of differential input signals (CK, CK and DQS, DQS ) must meet the req uirements in below table.
- 19 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 11.4 Slew Rate Definition for Single Ended Input Signals See "Address / Command Setup, Hold and Dera ting" for si ngle-ended slew rate definitions for addr ess and command signals.
- 20 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 12.3 Single-ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edg es is defined and measured between V OL (AC) and V OH (AC) for single ended signals as shown in below.
- 21 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 12.4 Diff erential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V OLdiff (AC) and V OH- diff (AC) for differential signals as shown in below .
- 22 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 13. IDD specific ation definition Symbol Description IDD0 Operating One Bank Active-Precharge Cur rent CKE: High; External clock: On; tCK, nRC, n.
- 23 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM NOTE : 1) Burst Length: BL8 fixed by MRS: set MR0 A[1, 0]=00B 2) Output Buf fer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01 B; R TT_Nom enabl.
- 24 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 14. IDD SPEC T able M391B5773DH0 : 2GB(256Mx72) Module NOTE : 1. DIMM IDD SPEC is calculated with consid ering de-actived rank(IDLE) is IDD2N. M391B5273DH0 : 4GB(512Mx72) Module NOTE : 1. DIMM IDD SPEC is calculated with consid ering de-actived rank(IDLE) is IDD2N.
- 25 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 15. Input /Output Capacitance [ T able 16 ] Input/Output Capacit ance NOTE : This parameter is Component Input/Output Capacit ance so that is different from Module level Cap acit ance. 1. Although the DM, TDQS and TDQ S pins have different functions, the loading matche s DQ and DQS 2.
- 26 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 16. E lectric al Char acteristics and AC t iming [0 ° C<T CASE ≤ 95 ° C, V DDQ = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V); V DD = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)] 16.1 Refresh Par ameters by Devic e Density NOTE : 1.
- 27 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM [ T able 18 ] DDR3-1066 Speed Bins [ T able 19 ] DDR3-1333 Speed Bins Speed DDR3-1066 Units NOTE CL-nRCD-nRP 7 - 7 - 7 Parameter Symbol min max Internal read command to first data tAA 13.125 20 ns ACT to internal read or write delay time tRCD 13.
- 28 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM [ T able 20 ] DDR3-1600 Speed Bins 16.3.1 Speed Bin T able Notes Speed DDR3-1600 Units NOTE CL-nRCD-nRP 11-11 -11 Parameter Symbol min max Intermal read command to first data tAA 13.75 (13.125) 8 20 ns ACT to internal read or write delay time tRCD 13.
- 29 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM Absolute S pecification [T OPER ; V DDQ = V DD = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)]; NOTE : 1.
- 30 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 17. T iming P aramet ers by Speed Grade [ T able 21 ] T iming Paramete rs by Speed Bin Speed DDR3-80 0 DDR3-1066 DDR3-13 33 DDR3-1600 Units NOTE .
- 31 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM [ Table 21 ] Timing Parame ters by Speed Bin (Cont.) Speed DDR3-800 DDR3-1066 DDR3- 1333 DDR3-1600 Units NOTE Parameter Symbol MIN MAX MIN MAX MI N MAX MIN MAX Data Strobe Timing DQS, DQS differenti al READ Preamble tRPRE 0.
- 32 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM [ T able 21 ] Timing Parameters by Speed Bin (Cont.) Speed DDR3-80 0 DDR3-10 66 DDR3-1333 DDR3-1600 Units NOTE Parameter Symbol MIN MAX MIN MAX M.
- 33 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 17.1 Jitter Notes Specific Note a Unit ’tCK(avg)’ repre sents the actual tCK(avg) of the input cl ock under operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges .
- 34 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 17.2 T iming Parameter Notes 1. Actual val ue dependant upon measuremen t level defi nitions whi ch are TBD. 2. Commands requ iring a locked DL L are: READ (and RAP ) and synchron ous ODT commands.
- 35 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 18. Physical Dimensions 18.1 256Mbx8 based 256Mx72 Modu le (1 Rank) - M391B5773DH0 133.35 ± 0.15 Max 4.0 54.675 Units : Millimeters 9.50 128.95 (2) (4X)3.00 ± 0.1 30.00 ± 0.15 2.30 17.30 The used devi ce is 256M x8 DDR3L SDRAM, FBGA.
- 36 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 18.2 256Mbx8 based 512Mx72 Modu le (2 Ranks) - M391B5273DH0 133.35 ± 0.15 Max 4.0 54.675 Units : Millimeters 9.50 128.95 (2) (4X)3.00 ± 0.1 30.00 ± 0.15 2.30 17.30 The used devi ce is 256M x8 DDR3L SDRAM, FBGA.
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