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Full Speed USB Flash MCU Family C8051F340/1/2/3/4/5/6/7 Rev. 0.5 1/06 Copyright © 2006 by Silicon Laboratories C8051F34x This information applies to a product under dev elopment. Its characteristics and specifications are subject to change without n otice.
C8051F340/1/2/3/4/5/6/7 2 Rev. 0.5 N OTES :.
Rev. 0.5 3 C8051F340/1/2/3/4/5/6/7 T able Of Content s 1. System Overview ............ ................................................. ............................ ........... 17 1.1. CIP-51™ Microcontroller Core .. ...............................
C8051F340/1/2/3/4/5/6/7 4 Rev. 0.5 9.3. Interrupt Handler ................ .................................................................. ............. 87 9.3.1. MCU Interrupt Sources a nd Vectors ............ ................................. ...
Rev. 0.5 5 C8051F340/1/2/3/4/5/6/7 14. Oscillators ................ ................ .................................................................. ........... 135 14.1.Programmable Internal Hi gh-Frequency (H-F) Oscillator ... ................. .
C8051F340/1/2/3/4/5/6/7 6 Rev. 0.5 17.3.SMBus Operation ....... ................ ........................................................... ......... 194 17.3.1.Arbitration ......... ................................................. .................
Rev. 0.5 7 C8051F340/1/2/3/4/5/6/7 21.2.Timer 2 ............. ................................ .................................................. ........... 251 21.2.1.16-bit Timer with Auto-Rel oad............... ....................................
C8051F340/1/2/3/4/5/6/7 8 Rev. 0.5 N OTES :.
Rev. 0.5 9 C8051F340/1/2/3/4/5/6/7 List of Figures and T ables 1. System Overview Table 1.1. Product Selection Guide . ............... ............................................. ........... 18 Figure 1.1. C8051F340/1/4/5 Blo ck Diagram ............
C8051F340/1/2/3/4/5/6/7 10 Rev. 0.5 8. Voltage Regulator (REG0) Table 8.1. Voltage Regulator El ectrical Specificati ons .............. ................. ............. 69 Figure 8.1. REG0 Configuratio n: USB Bus-Powered ... ...........................
Rev. 0.5 11 C8051F340/1/2/3/4/5/6/7 Figure 16.2. USB0 Regi ster Access Scheme ........ ................................................. 166 Table 16.2. USB0 C ontroller Registers .......... ............................................... ......... 169 Figure 16.
C8051F340/1/2/3/4/5/6/7 12 Rev. 0.5 Figure 20.10. SPI Slave Timing (C KPHA = 0) .............. ................................. ......... 240 Figure 20.11. SPI Slave Timing (C KPHA = 1) .............. ................................. ......... 240 Table 20.
Rev. 0.5 13 C8051F340/1/2/3/4/5/6/7 List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 48 SFR Definition 5.2. AMX0N: AMUX 0 Negative Channel Select . . . . . . . . . . . . . . . . . . 49 SFR Definition 5.
C8051F340/1/2/3/4/5/6/7 14 Rev. 0.5 SFR Definition 14.3. OSCLCN: Inter nal L-F Oscillator Control . . . . . . . . . . . . . . . . . . 138 SFR Definition 14.4. OSCXCN: External Oscillator C ontrol . . . . . . . . . . . . . . . . . . . . 141 SFR Definition 14.
Rev. 0.5 15 C8051F340/1/2/3/4/5/6/7 USB Register Definiti on 16.20. EINCSRH: USB0 IN Endpoi nt Control High Byte . . . 187 USB Register Defini tion 16.21. EOUTCSRL: USB0 OUT Endpoint Control Low Byte 189 USB Register Definition 16.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte 190 USB Register Definiti on 16.
C8051F340/1/2/3/4/5/6/7 16 Rev. 0.5 C2 Register Definition 23.2. DEVICE ID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 279 C2 Register Definition 23.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 280 C2 Register Definition 23.
Rev. 0.5 17 C8051F340/1/2/3/4/5/6/7 1. System Overview C8051F340/1/2/3/4/5/6/7 devices are fu lly integrated m ixed-sign al System-on-a-Chip MCUs. Highlighted features are listed below .
C8051F340/1/2/3/4/5/6/7 18 Rev. 0.5 Ta b l e 1.1. Product Selection Guide Ordering Pa rt Number MIPS (Peak) Flash Memory (Bytes) RAM Calibrated Internal Oscillator Low Frequency Oscillator USB with 1k.
Rev. 0.5 19 C8051F340/1/2/3/4/5/6/7 Figure 1.1. C8051F340/1/4/5 Block Diagram Analog Peripherals 10-bit 200ksps ADC A M U X Temp Sensor 2 Comparators + - VREF VDD CP0 VDD + - CP1 VREF Debug / Programmi ng Hardware Port 0 Drivers P0.
C8051F340/1/2/3/4/5/6/7 20 Rev. 0.5 Figure 1.2. C8051F342/3/6/7 Block Diagram Analog Peripherals 10-bit 200 ksps ADC A M U X Temp Sensor 2 Comparators + - VREF VDD CP0 VDD + - CP1 VREF Debug / Programming Hardware Port 0 Drivers P0.
Rev. 0.5 21 C8051F340/1/2/3/4/5/6/7 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Comp atible The C8051F340/1 /2/3/4/5/6/7 family utilizes Silicon Labs' proprietary CIP- 51 microcontroller core.
C8051F340/1/2/3/4/5/6/7 22 Rev. 0.5 Figure 1.3. On-Chi p Clock and Reset PCA WDT Missing Clock Detector (one- shot) Software Reset (SWRSF ) System Reset Reset Funnel Px.
Rev. 0.5 23 C8051F340/1/2/3/4/5/6/7 1.2. On-Chip Memory The CIP-51 has a sta ndard 8051 progr am and dat a addr ess configuration. It in cludes 256 bytes of data RAM, with the upper 128 bytes du al-mappe d. Indirect addressing accesses the up per 128 bytes of gene ral purpose RAM, and direct addr essing accesses the 128 byte SFR addre ss space .
C8051F340/1/2/3/4/5/6/7 24 Rev. 0.5 1.3. Universal Serial Bus Controller The Universal Serial Bus Controller (USB0) is a USB 2.0 compliant Full or Low S peed function with inte - grated transceiver and endp oint FIFO RAM.
Rev. 0.5 25 C8051F340/1/2/3/4/5/6/7 1.4. V oltage Regulator C8051F340/1/2/3/4/5/6/7 devices include a voltage regulator (REG0). When en abled, the REG0 output appears on the V DD pin, and can also be used to power other e xternal devices. REG0 can be e nabled/dis - abled by software.
C8051F340/1/2/3/4/5/6/7 26 Rev. 0.5 1.6. Programmable Digit al I/O and Crossbar C8051F340/1/4/5 devices include 40 I/O pins (five byte-wide Ports); C8 051F342/3/6/7 devices inclu de 25 I/O pins (three byte-wide Port s, and a 1-bi t-wide Port ). The C8051F 340/1/2/3/4/5/6/7 Port s behave like typ - ical 8051 Ports with a few enhancement s.
Rev. 0.5 27 C8051F340/1/2/3/4/5/6/7 1.7. Serial Port s The C8051F340/1/2/3/4/ 5/6/7 Family includes an SMBus/I2C inter face, full-duplex UART s, and an Enhanced SPI inte rface. Each of the serial buses is fully implemented in hardwa re and makes extensive use of the CIP-51's in terrupts, thus requiring very little CPU intervention.
C8051F340/1/2/3/4/5/6/7 28 Rev. 0.5 1.9. 10-Bit Analog to Digit al Converter The C8051F340/1/2/3/4/5 /6/7 devices include an on-chip 10-bit SAR ADC with a true di f fe rential inpu t mul - tiplexer . With a maximum throughput of 200 ksp s, the ADC of fers true 10-b it linearity with an INL o f ±1LSB.
Rev. 0.5 29 C8051F340/1/2/3/4/5/6/7 1.10. Comp arators C8051F340/1/2/3/4/5/6/7 devices include two on-chip volt age comp arators that are enabled/disabled and configured via user soft ware. Port I/O pins may be co nfigured as comparator inpu ts via a selection mux.
C8051F340/1/2/3/4/5/6/7 30 Rev. 0.5 2. Absolute Maximum Ratings Ta b l e 2.1. Absolute Maximum Ratings* Parameter Conditions Min T yp Max Unit s Ambient temperature under bias –55 125 °C S to rage T emp erature –65 150 °C V oltage on any Port I/O Pin or /RST with respect to GND –0.
Rev. 0.5 31 C8051F340/1/2/3/4/5/6/7 3. Global DC Electrical Characteristics Other electric al characteristics tables ar e found in the dat a sheet section correspond ing to the associated peripherals. For more information o n electrical characte ristics for a specific perip heral, refer to the p age indicated in Ta b l e 3.
C8051F340/1/2/3/4/5/6/7 32 Rev. 0.5 Ta b l e 3.2. Index to Electrical Characteristics T ables Ta b l e T i t l e Page No. ADC0 Electrical Characteristics 56 V oltage Refe re nce Electr ical Characteri.
Rev. 0.5 33 C8051F340/1/2/3/4/5/6/7 4. Pinout and Package Definitions Ta b l e 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7 Name Pin Numbers Ty p e Description 48-pin 32-pin V DD 10 6 Power In Power Out 2.7–3.6 V Power Sup ply V oltage Input.
C8051F340/1/2/3/4/5/6/7 34 Rev. 0.5 P1.0 46 26 D I/O or A In Port 1.0. See Section 15 for a complete descrip t ion of Port 1. P1.1 45 25 D I/O or A In Port 1.1. P1.2 44 24 D I/O or A In Port 1.2. P1.3 43 23 D I/O or A In Port 1.3. P1.4 42 22 D I/O or A In Port 1.
Rev. 0.5 35 C8051F340/1/2/3/4/5/6/7 P3.3 27 - D I/O or A In Port 3.3. P3.4 26 - D I/O or A In Port 3.4. P3.5 25 - D I/O or A In Port 3.5. P3.6 24 - D I/O or A In Port 3.6. P3.7 23 - D I/O or A In Port 3.7. P4.0 22 - D I/O or A In Port 4.0. See Section 15 for a complete descrip t ion of Port 4.
C8051F340/1/2/3/4/5/6/7 36 Rev. 0.5 Figure 4.1. TQFP-48 Pi nout Diagram (T op V iew) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 VBUS P2.2 P2.0 P1.7 P1.6 P1.2 P2.4 P2.3 P3.5 P3.4 P3.2 P3.1 P2.1 P0.
Rev. 0.5 37 C8051F340/1/2/3/4/5/6/7 Figure 4.2. TQFP-48 Package Diagram E E1 D D1 48 1 A1 e b PIN 1 IDENTIFIER A2 A T able 4.2. TQFP-48 Package Dimensions MM MIN TYP MAX A- - 1 . 2 0 A1 0.05 - 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0.27 D- 9 . 0 0 - D1 - 7.
C8051F340/1/2/3/4/5/6/7 38 Rev. 0.5 Figure 4.3. LQFP-32 Pi nout Diagram (T op V iew) 1 VBUS P1.2 P1.7 P1.4 P1.3 P1.5 D+ D- GND P0.1 P0.0 P2.0 P2.1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 P1.6 C8051F342/3/6/7 Top View VDD REGI N /RST / C2C K P3.
Rev. 0.5 39 C8051F340/1/2/3/4/5/6/7 Figure 4.4. LQFP-32 Package Diagram PIN 1 IDENTIFIER A1 e b 1 32 E1 D1 D E A2 A T able 4.3. LQFP-32 Package Dimensions MM MIN TYP MAX A- - 1 . 6 0 A1 0.05 - 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 D- 9 . 0 0 - D1 - 7.
C8051F340/1/2/3/4/5/6/7 40 Rev. 0.5 N OTES :.
Rev. 0.5 41 C8051F340/1/2/3/4/5/6/7 5. 10-Bit ADC (ADC0) The ADC0 subsystem for the C8051F340/1/2/3/4/5/6/7 c onsists of two analog multip lexers (referred to col - lectively as AMUX0), and a 20 0 ksps, 10-bit successive-approxima tion-regist er ADC with integr ated track-and-hold and programm able window detector .
C8051F340/1/2/3/4/5/6/7 42 Rev. 0.5 5.1. Analog Multiplexer AMUX0 selects the po sitive and negative input s to the ADC. The positive input (AIN+) can be conn ected to individual Port pins, the o n-chip temperature sensor , or the positive power supply (V DD ) .
Rev. 0.5 43 C8051F340/1/2/3/4/5/6/7 5.2. T emperature Sensor The temperature sensor tra nsfer function is shown in Figure 5.2. The outp ut volt age (V TEMP ) is the positive ADC input when the temperature se nsor is selected by bits AMX0P4-0 in register AMX0P .
C8051F340/1/2/3/4/5/6/7 44 Rev. 0.5 Figure 5.3. T emperature Sensor Error with 1- Poin t Calibration (VREF = 2.40 V) -40.00 -20.00 0.0 0 20.0 0 40.0 0 60.0 0 80.0 0 Temperature (degrees C) Error (degrees C) -5.00 -4.00 -3.00 -2.00 -1.00 0.0 0 1.0 0 2.
Rev. 0.5 45 C8051F340/1/2/3/4/5/6/7 5.3. Modes of Operation ADC0 has a maximum conversion speed of 200 ksp s. The ADC0 con version clock is a divided ve rsion of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + 1) for 0 ≤ AD0SC ≤ 31).
C8051F340/1/2/3/4/5/6/7 46 Rev. 0.5 5.3.2. T racking Modes The AD0TM bit in r egister ADC0CN controls the ADC0 track-and -hold mode. In its d efault state, the ADC0 input is continuously tracked, except when a conversi on is in progress. When the AD0TM bit is logic 1, ADC0 operates in low-powe r track-and-hold mode.
Rev. 0.5 47 C8051F340/1/2/3/4/5/6/7 5.3.3. Settling Tim e Requirement s When the ADC0 input configuration is changed (i.e., a differe nt AMUX0 selection is made), a minimum tracking time is required befo re an accurate conversion c an be performed .
C8051F340/1/2/3/4/5/6/7 48 Rev. 0.5 SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select Bits7–5: UNUSED. Read = 000b; Write = don’t care . Bits4–0: AMX0P4–0: AMUX0 Positive Input Selectio.
Rev. 0.5 49 C8051F340/1/2/3/4/5/6/7 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0N4–0: AMUX0 Negative Input Selection. Note that when GND is selected as t he Nega tive Input, ADC0 operates in Sing le-ended mode.
C8051F340/1/2/3/4/5/6/7 50 Rev. 0.5 SFR Definition 5.3. ADC0CF: ADC0 Configuration SFR Definition 5.4. ADC0H: ADC0 Dat a W ord MSB SFR Definition 5.5. ADC0L: ADC0 Dat a Word LSB Bits7–3: AD0SC4–0: ADC0 SAR Co nv ersion Clock Per iod Bits.
Rev. 0.5 51 C8051F340/1/2/3/4/5/6/7 SFR Definition 5.6. ADC0CN: ADC0 Control Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conver sions. Bit6: AD0TM: ADC0 Tr ack Mode Bit.
C8051F340/1/2/3/4/5/6/7 52 Rev. 0.5 5.4. Programmable Window Detector The ADC Programmable Win dow Detector continuo us ly compares the ADC0 conver sion result s to user-prog rammed limits, and no tifies the syste m when a desired condition is detected.
Rev. 0.5 53 C8051F340/1/2/3/4/5/6/7 SFR Definition 5.9. ADC0L T H: ADC0 Less-Than Dat a High Byte SFR Definition 5.10. ADC0L TL: ADC0 Less-Than Dat a Low Byte Bits7–0: High byte of ADC0 Less-Than Dat a W or d.
C8051F340/1/2/3/4/5/6/7 54 Rev. 0.5 5.4.1. Window Detector In Single-Ended Mode Figure 5.6 shows two ex ample wind ow comparisons fo r right-justified, si ngle-ended dat a, with ADC0L TH:ADC0L TL = 0x0080 (128 d) and ADC0G TH: ADC0G TL = 0x0040 (64d).
Rev. 0.5 55 C8051F340/1/2/3/4/5/6/7 5.4.2. Window Detector In Differential Mode Figure 5.8 shows two examp le window compa risons for ri ght-justified, dif ferentia l data, with ADC0L TH:ADC0L TL = 0x0040 (+64d) and ADC0G TH:ADC0G TH = 0xFFFF (-1d).
C8051F340/1/2/3/4/5/6/7 56 Rev. 0.5 Ta b l e 5.1. ADC0 Electrical Characteristics V DD = 3.0 V , VREF = 2.40 V , –40 to +85 °C u nless othe rwise specif ied Paramete r Conditions Min Ty p Max Units DC Accuracy Resolution 10 bits Integral Nonlinearity ±0.
Rev. 0.5 57 C8051F340/1/2/3/4/5/6/7 6. V olt age Reference The V oltage refere nce MUX on C8051F340/1/2 /3/4/5/6/7 devices is configurable to u se an externally con - nected volt age reference, the on-ch ip reference volt age genera tor , or the power supply volt age V DD (se e Figure 6.
C8051F340/1/2/3/4/5/6/7 58 Rev. 0.5 SFR Definition 6.1. REF0CN: Reference Control Ta b l e 6.1. V oltage Reference Electrical Characteristics V DD = 3.0 V ; –40 to +85 °C Unless Oth erwise S pecified Parameter Conditions Min Ty p Max Unit s Internal Reference (REFBE = 1) Output V olt age 25 °C ambient 2.
Rev. 0.5 59 C8051F340/1/2/3/4/5/6/7 7. Comp arators C8051F340/1/2/3/4/5/6/7 devices in clude two o n-chip progr ammable voltage Comparator s. A block dia - gram of the comp arators is sh own in Figure 7.1 , wher e “n” is the compa rator number (0 or 1).
C8051F340/1/2/3/4/5/6/7 60 Rev. 0.5 Figure 7.1. Comp arator Functional Block Diagram Comparator outp uts can be polled in software, used as an interrupt so urce, and/or ro uted to a Port pin .
Rev. 0.5 61 C8051F340/1/2/3/4/5/6/7 Figure 7.2. Compar ator Hysteresis Plot Comparator hyste resis is prog rammed us ing Bits3-0 in the Comparator Contro l Register CPTnCN (shown in SFR Definition 7.1 and SFR Definition 7.4 ). The amount of n egative hyst eresis voltage is determined b y the settings of the CPnHYN bits .
C8051F340/1/2/3/4/5/6/7 62 Rev. 0.5 SFR Definition 7.1. CPT0CN: Comp arator0 Control Bit7: CP0EN: Comparator0 En ab le Bit. 0: Comparator 0 Disabled. 1: Comparator 0 Enabled. Bit6: CP0OUT : Comparator 0 Ou tp ut S tate Flag. 0: V o ltage on CP0+ < C P0–.
Rev. 0.5 63 C8051F340/1/2/3/4/5/6/7 SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection Bit7: U NUSED. Read = 0b, Write = don’t care . Bits6–4: CMX0N2–CMX0N0: Comp arator0 Negative Input MUX Sele ct. These bits selec t which Port p in is used as the Comparator0 negative inp ut.
C8051F340/1/2/3/4/5/6/7 64 Rev. 0.5 SFR Definiti on 7.3. CPT0MD: Comp arator 0 Mode Selection Bits7–6: UNUSED. Read = 00b. Write = don’t care. Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator 0 rising-edge interru pt disabled.
Rev. 0.5 65 C8051F340/1/2/3/4/5/6/7 SFR Definition 7.4. CPT1CN: Comp arator1 Control Bit7: CP1EN: Comparator1 En ab le Bit. 0: Comparator 1 Disabled. 1: Comparator 1 Enabled. Bit6: CP1OUT : Comparator 1 Ou tp ut S tate Flag. 0: V o ltage on CP1+ < C P1–.
C8051F340/1/2/3/4/5/6/7 66 Rev. 0.5 SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection Bit7: UNUSED. Read = 0b , Write = don’t care. Bits6–4: CMX1N2–CMX1N0: Comp arat or1 Nega tive Input MUX Select. These bit s select which Port pin is us ed as the Comp arator1 negative inp ut.
Rev. 0.5 67 C8051F340/1/2/3/4/5/6/7 SFR Definiti on 7.6. CPT1MD: Comp arator 1 Mode Selection Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP1RIE: Comparator1 Rising-Edge Interrupt Enable. 0: Comparator 1 rising-edge interru pt disabled.
C8051F340/1/2/3/4/5/6/7 68 Rev. 0.5 Ta b l e 7.1. Comparator Electri cal Characteristics V DD = 3.0 V , –40 to +85 °C unless other w ise noted. All specifications apply to both Comp arator0 and Comp arator1 unless otherwise noted. Paramete r Conditions Min Ty p Max Units Response T ime: Mode 0, Vcm* = 1.
Rev. 0.5 69 C8051F340/1/2/3/4/5/6/7 8. V oltage Regulator (REG0) C8051F340/1/2/3/4/5/6/7 devices include a voltage regulator (REG0). When en abled, the REG0 output appears on the V DD pin and can be used to powe r external d evices. REG0 can be en abled/disabled by software using bit REGEN in register R EG0CN.
C8051F340/1/2/3/4/5/6/7 70 Rev. 0.5 Figure 8.1. REG0 Confi guration: USB Bus-Powered Figure 8.2. REG0 Configur ation: USB Self-Powered Voltage Regulator (REG 0) 5 V In 3 V Out VBUS Sens e REGIN VBUS F.
Rev. 0.5 71 C8051F340/1/2/3/4/5/6/7 Figure 8.3. REG0 Conf iguration: USB Self-Pow ered, Regulator Disabled Figure 8.4. REG0 Configur ation: No USB Connection Voltage Regu lator (REG0) 5 V In 3 V O ut .
C8051F340/1/2/3/4/5/6/7 72 Rev. 0.5 SFR Definition 8.1. REG0CN: V olt age Regulator Control Bit7: REGDIS: V oltag e Regulator Disable. 0: V o ltage Regulator Ena bled. 1: V o ltage Regulator Disab led. Bit6: VBST A T : VBUS Signal S tatus. 0: VBUS signal currently absent (device not att ached to USB network) .
Rev. 0.5 73 C8051F340/1/2/3/4/5/6/7 9. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcon troller . The CIP-51 is fully compatible with the MCS-51™ instruction set; st andard 803x/805x a ssemble rs and compilers can be used to develop sof t - ware.
C8051F340/1/2/3/4/5/6/7 74 Rev. 0.5 Performance The CIP-51 emplo ys a p ipeli ned architectu re tha t grea tly increases it s instr uction throug hput over the st an - dard 8051 architecture. In a standar d 8051, all instructions except for MUL and DIV ta ke 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 MHz.
Rev. 0.5 75 C8051F340/1/2/3/4/5/6/7 CIP-51 Instruction Set Summar y , which includes the mnemonic, number of bytes, and number of clock cycles for each instruction.
C8051F340/1/2/3/4/5/6/7 76 Rev. 0.5 ORL A, direct OR direct byte to A 2 2 ORL A, @Ri OR indirect RAM to A 1 2 ORL A, #data OR immediate to A 2 2 ORL direct, A OR A to direct byte 2 2 ORL direct, #d at.
Rev. 0.5 77 C8051F340/1/2/3/4/5/6/7 XCH A, @Ri Exchange indirect RAM with A 1 2 XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2 Boolean Manipulation CLR C Clear Carry 1 1 CLR bit Clear dire.
C8051F340/1/2/3/4/5/6/7 78 Rev. 0.5 Notes on Registers, Operands and Addr essing Modes: Rn - Register R0-R7 of the curren tly selected register bank. @Ri - Data RAM location address ed indirectly thro ugh R0 or R1. rel - 8-bit, signed (two’ s complem ent) of fset relative to the first byte of the following instr uction.
Rev. 0.5 79 C8051F340/1/2/3/4/5/6/7 9.2. Memory Organization The memory organ ization of the CIP-51 Syste m Controller is similar to that of a stan dard 8051. There ar e two separa te memory sp aces: prog ram memory and data m emory . Progra m and dat a memory sh are the same addres s sp ace but are ac cessed via different in struction types.
C8051F340/1/2/3/4/5/6/7 80 Rev. 0.5 9.2.2. Dat a Memory The CIP-51 includes 256 of intern al RAM mapped in to the dat a memory sp ace from 0x00 through 0 xFF . The lower 128 bytes of data memory are used for ge neral purpose register s and scratch pad memory .
Rev. 0.5 81 C8051F340/1/2/3/4/5/6/7 9.2.6. Spec ial Function Registers The direct-access dat a memory locations from 0x80 to 0xFF constitute the sp ecial function registers (SFRs). The SFRs provide control and dat a exchang e with the CIP- 51's resources and per ipherals.
C8051F340/1/2/3/4/5/6/7 82 Rev. 0.5 Ta b l e 9.3. Special Function Registers SFRs are listed in alph abetical order . All undefine d SFR locatio ns are reserved.
Rev. 0.5 83 C8051F340/1/2/3/4/5/6/7 P1MDIN 0xF2 Port 1 Inpu t Mo de Con fig ur at ion 156 P1MDOUT 0xA5 Port 1 Output Mode Con figuration 156 P1SKIP 0xD5 Port 1 Skip 157 P2 0xA0 Port 2 Latch 157 P2MDIN.
C8051F340/1/2/3/4/5/6/7 84 Rev. 0.5 SBUF0 0x99 UART0 Dat a Buf fer 217 SCON0 0x98 UART0 Control 216 SMB0CF 0xC1 SMBus Configuration 200 SMB0CN 0xC0 SMBus Control 202 SMB0DA T 0xC2 SMBus Data 204 SMOD1.
Rev. 0.5 85 C8051F340/1/2/3/4/5/6/7 9.2.7. Register Descriptions Following are descr iptions of SFRs related to the operati on of the CIP-51 System Controller .
C8051F340/1/2/3/4/5/6/7 86 Rev. 0.5 SFR Definiti on 9.4. PSW: Program S tatus W ord SFR Definition 9.5. ACC: Accumulator Bit7: CY : Ca rry Flag . This bit is set when the last arithmetic operat ion resulted in a carry (addition) or a bo rrow (subtraction).
Rev. 0.5 87 C8051F340/1/2/3/4/5/6/7 SFR Definiti on 9.6. B: B Register 9.3. Interrupt Handler The CIP-51 includes a n extended inter rupt system supp orting multiple interr upt sources with two priority levels.
C8051F340/1/2/3/4/5/6/7 88 Rev. 0.5 /INT0 and /IN T1 are assigned to Port pins as define d in the IT01CF register (see SFR Definition 9.13). Note that /INT0 and /INT0 Port p in assignment s are indep endent of any Cr ossbar assignment s.
Rev. 0.5 89 C8051F340/1/2/3/4/5/6/7 9.3.5. Interrupt Register Descriptions The SFRs used to enable th e inte rrupt sources an d set t heir priori ty level ar e descr ibed be low .
C8051F340/1/2/3/4/5/6/7 90 Rev. 0.5 SFR Definition 9.7. IE: Interrupt Enable Bit7: EA: Enable All Interrupts. This bit globally enab les/disabl es all interrupt s. It overrides the individual interrupt mask set- tings. 0: Disable all interrupt sources.
Rev. 0.5 91 C8051F340/1/2/3/4/5/6/7 SFR Definition 9.8. IP: Interrupt Priority Bit7: UNUSED. Read = 1, Write = don't care. Bit6: PSPI0: Serial Periph eral Interface (SPI0) In terrupt Priority Control. This bit set s the priori ty of the SPI0 interrupt.
C8051F340/1/2/3/4/5/6/7 92 Rev. 0.5 SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 Bit7: ET3: Enable T imer 3 Interrupt. This bit sets the masking of the T imer 3 interrupt. 0: Disable T imer 3 interrupt s. 1: Enable interrupt reque st s generated by the TF3L or TF3H flags.
Rev. 0.5 93 C8051F340/1/2/3/4/5/6/7 SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 Bit7: PT3: T imer 3 Interr upt Priority Control. This bit set s the priori ty of the T imer 3 interrupt. 0: Timer 3 interrupts se t to low priority level. 1: T imer 3 interrupts set to high priority level.
C8051F340/1/2/3/4/5/6/7 94 Rev. 0.5 SFR Definition 9.1 1. EIE2: Extended Interrupt Enable 2 SFR Definition 9.12. EIP2: Extended Interrupt Priority 2 Bits7–2: UNUSED. Read = 000000 b. Write = don’t care. Bit1: ES1: Enable UART1 Interr upt. This bit sets the ma sking of the UART1 interrupt.
Rev. 0.5 95 C8051F340/1/2/3/4/5/6/7 SFR Definition 9.13. IT01CF: INT0/INT 1 Configuration Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low . 1: /INT1 inp ut is active h igh. Bits6–4: IN1SL2–0: /INT1 Port Pin Selection Bit s These bit s select which Port pin is assigned to /INT1.
C8051F340/1/2/3/4/5/6/7 96 Rev. 0.5 9.4. Power Management Modes The CIP-51 core has two sof tware programmable power manage ment modes: Idle and S top.
Rev. 0.5 97 C8051F340/1/2/3/4/5/6/7 SFR Definition 9.14. PCON: Power Control Bits7–2: GF5–GF0: General Pur pose Flags 5–0. These are general purp ose flags for use under sof tware control. Bit1: STOP: S top Mode Select. Setting this bit will place the CIP-51 in S top mode.
C8051F340/1/2/3/4/5/6/7 98 Rev. 0.5 N OTES :.
Rev. 0.5 99 C8051F340/1/2/3/4/5/6/7 10. Prefetch Engine The C8051F340/1/2/3/4/5/6/7 family of devices in corporat e a 2-byte prefetch engine. Because the access time of the FLASH memory is 40 n s, and the minimum instruction time is roughl y 20 ns, the pr efetch engine is necessary for full- speed code execution.
C8051F340/1/2/3/4/5/6/7 100 Rev. 0.5 N OTES :.
Rev. 0.5 101 C8051F340/1/2/3/4/5/6/7 1 1. Reset Sources Reset circuitry allows the controller to be easily placed in a pred efined default condition. On entry to this reset state, th e following occur.
C8051F340/1/2/3/4/5/6/7 102 Rev. 0.5 1 1.1. Power-On Reset During power-up, the de vice is held in a rese t state and the /RST pin is driven low until V DD settles above V RST . A Power-On Reset delay (T PORDelay ) occurs before the de vice is released from reset; this delay is typically less than 0.
Rev. 0.5 103 C8051F340/1/2/3/4/5/6/7 1 1.2. Power-Fail Reset / V DD Monitor When a power-down transition or power irregular ity causes V DD to drop below V RST , the power supply monitor will drive the /RST pin low and ho ld the CIP-51 in a reset state (see Figure 11 .
C8051F340/1/2/3/4/5/6/7 104 Rev. 0.5 1 1.3. External Reset The external /RST pin provides a means for extern al ci rcuitry to force the device into a reset state.
Rev. 0.5 105 C8051F340/1/2/3/4/5/6/7 1 1.8. Sof tware Reset Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol - lowing a soft ware forced reset. The st ate of the /RST pin is unaf fected by this reset.
C8051F340/1/2/3/4/5/6/7 106 Rev. 0.5 SFR Definition 11 . 2 . RSTSRC: Reset Source Bit7: USBRSF: USB Reset Flag 0: Read: Last reset was not a USB reset; Wri te : USB resets disabled. 1: Read: Last reset was a USB reset; Wr i te : USB resets enabled. Bit6: F ERROR: Flash Error Indicator .
Rev. 0.5 107 C8051F340/1/2/3/4/5/6/7 Ta b l e 11 . 1 . Reset Electrical Characteristics –40 to +85 °C unless otherwise s pecified. Parameter Conditions Min T yp Max Unit s /RST Output Low V oltage I OL = 8.5 mA, V DD = 2.7 to 3.6 V 0.6 V /RST Input High V oltage 0.
C8051F340/1/2/3/4/5/6/7 108 Rev. 0.5 N OTES :.
Rev. 0.5 109 C8051F340/1/2/3/4/5/6/7 12. Flash Memo ry On-chip, re-programmab le Flash memory is included fo r program code and non-vo latile data storag e. The Flash memo ry can be prog rammed in-sy stem throug h the C2 inte rface or by s oftware using the MO VX instruction.
C8051F340/1/2/3/4/5/6/7 110 Rev. 0.5 12.1.3. Flash Write Procedure Bytes in Flash mem ory can be written on e byte at a time, or in groups of two. Th e FLBWE bit in registe r PFE0CN ( SFR Definit ion 10.1 ) controls whether a single byte or a block of two bytes is written to Flash during a write operation.
Rev. 0.5 111 C8051F340/1/2/3/4/5/6/7 12.2. Non-volatile Dat a S torage The Flash memory can be used for non-vo latile data storage as well as p rogram code. This allows dat a such as calibration coefficient s to be calculated and stor ed at run time. Dat a is written using the M OVX write instruction and read using the MOVC instructi on.
C8051F340/1/2/3/4/5/6/7 112 Rev. 0.5 Figure 12.1. Flash Program Me mory Map and Security Byte Access limit set according to the FLASH security lock byte C8051F340/2/4 /6 0x0000 0xFBFF Lock B y te Rese.
Rev. 0.5 113 C8051F340/1/2/3/4/5/6/7 The level of FLASH security depends on the FLASH access meth od. The three FLASH access methods that can be restricted a re reads, w r ites, and erases from the C2 debug in terface, user fi r mware executing on unlocked p ages, and user firm ware executing on locke d pages.
C8051F340/1/2/3/4/5/6/7 114 Rev. 0.5 SFR Definition 12.1. PSCTL: Program Store R/W Control SFR Definition 12.2. FLKEY : Flash Lock and Key Bits7–3: Unused: Read = 00 000b.
Rev. 0.5 115 C8051F340/1/2/3/4/5/6/7 SFR Definition 12.3. FLSCL: F lash Scale Bits7: FOSE: Flash One-shot En able This bit enables the Flash read one-shot. W hen the Flash one- shot disabled, the Flash sense amps are enabled for a full clock cycle during Flash reads.
C8051F340/1/2/3/4/5/6/7 116 Rev. 0.5 N OTES :.
Rev. 0.5 117 C8051F340/1/2/3/4/5/6/7 13. External Data Memory Interface and On-Chip XRAM 4k Bytes (C8 051F340/2/ 4/6) or 2k Bytes (C8051F341/3/5/7) of RAM are included on-chip , and mapped into the external dat a memory space (XRAM) .
C8051F340/1/2/3/4/5/6/7 118 Rev. 0.5 13.2. Accessing USB FIFO Sp ace The C8051F340/1/2 /3/4/5/6/7 include 1k of RA M which functions a s USB FIFO space. Figure 13.1 shows an expand ed view of the FIFO space an d user XRAM . FIFO sp ace is normally accessed via USB FIFO registers; see Sec tion “16.
Rev. 0.5 119 C8051F340/1/2/3/4/5/6/7 13.3. Configuring the External Memory Interface Configuring the External Memory Interface co nsists of five step s: 1. Configure the Outpu t Modes of the associated port pin s as either push-p ull or open-drai n (push-pull is most common), and skip the associated pins in the crossbar .
C8051F340/1/2/3/4/5/6/7 120 Rev. 0.5 SFR Definition 13.1. EMI0CN: External Memo ry Interface Control Bits7–0: PGSE L[7:0]: XR AM Page Select Bits. The XRAM Page Select Bit s provide the high byte of the 16-bit exter n al da ta memor y address when using an 8-bit MOVX command, ef fectively selecting a 256-byte p age of RAM.
Rev. 0.5 121 C8051F340/1/2/3/4/5/6/7 SFR Definition 13.2. EMI0CF: External Memory Configuration Bit7: Unused. Read = 0b. Write = don’t care . Bit6: USBF AE: USB FIFO Access Enable. 0: USB FIFO RAM not availabl e through MOVX instruction s. 1: USB FIFO RAM available using MOVX instru ctions.
C8051F340/1/2/3/4/5/6/7 122 Rev. 0.5 13.5. Multiplexed and Non-multiplexed Selection The External Memory In terface is capable of acting in a Multiplexe d mode or a No n-multiplexed mode, depending on the st ate of the EMD2 (EMI0CF .
Rev. 0.5 123 C8051F340/1/2/3/4/5/6/7 13.5.2. Non-multiplexed Configuration In Non-multiplexe d mode, the Dat a Bus and the Address Bus pins are n ot shared. An example o f a Non-multiplexed Config uration is shown in Figure 13.3 . See Se ction “13.7.
C8051F340/1/2/3/4/5/6/7 124 Rev. 0.5 13.6.1. Internal XRAM Only When EMI0CF .[3:2] are set to ‘00’, all MOVX instructions will ta rget the internal XRAM space on the device. Memory accesses to addresses beyond the populated space will wrap on 2k or 4k boundaries (depending on the RAM availa ble on the device).
Rev. 0.5 125 C8051F340/1/2/3/4/5/6/7 13.6.3. Split Mode with Bank Select When EMI0CF .[3:2] are set to ‘1 0’, the XRAM memory map is split into two ar eas, on-chip space an d off-chip space. • Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
C8051F340/1/2/3/4/5/6/7 126 Rev. 0.5 SFR Definition 13.3. EMI0TC: External Me mory T iming Control Bits7–6: EAS1–0: EMIF Addr ess Setup T ime Bits. 00: Address setup time = 0 SYS CLK cycles. 01: Address setup time = 1 SYS CLK cycle. 10: Address setup time = 2 SYS CLK cycles.
Rev. 0.5 127 C8051F340/1/2/3/4/5/6/7 13.7.1. Non-multiplexed Mode 13.7.1.1.16-bit MOVX: EMI0CF[4:2] = ‘1 01’, ‘1 10’, or ‘1 1 1’. Figure 13.5. Non-multip lexed 16-bit MOVX Timing EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPL P3 P2 P1.
C8051F340/1/2/3/4/5/6/7 128 Rev. 0.5 13.7.1.2.8-bit MOVX without Bank Se lect: EMI0CF[4:2] = ‘101’ or ‘1 1 1’. Figure 13.6. Non-multip lexed 8-bit MOVX withou t Bank Select Timing EMIF ADDRESS (8 LSBs) from R0 or R1 P3 P2 P1.7 P1.6 P4 EMIF WRITE D ATA P3 P1.
Rev. 0.5 129 C8051F340/1/2/3/4/5/6/7 13.7.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘1 10’. Figure 13.7. Non-multip lexed 8-bit MOVX with Bank Select Timing P4 P3 P4 ADDR[15:8] AD[7:0] P3 P1.
C8051F340/1/2/3/4/5/6/7 130 Rev. 0.5 13.7.2. Multiplexed Mode 13.7.2.1.16-bit MOVX: EMI0CF[4:2] = ‘0 01’, ‘010’, or ‘01 1’. Figure 13.8. Multiple xed 16-bit MOVX Timing P4 P3 P4 ADDR[15: 8] AD[7:0 ] P3 P1.
Rev. 0.5 131 C8051F340/1/2/3/4/5/6/7 13.7.2.2.8-bit MOVX without Bank Se lect: EMI0CF[4:2] = ‘001’ or ‘01 1’. Figure 13.9. Multiplexed 8-bit MO VX without Bank Select T iming P4 P3 P4 ADDR[15:8] AD[7:0] P1.
C8051F340/1/2/3/4/5/6/7 132 Rev. 0.5 13.7.2.3.8-bit MOVX with Bank Select : EMI0CF[4:2 ] = ‘010’. Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing P4 P3 P4 ADDR[15:8] AD[7:0] P3 P1.
Rev. 0.5 133 C8051F340/1/2/3/4/5/6/7 Ta b l e 13.1. AC Parameters for Exte rnal Memory Interface Parameter Description Min* Max* Unit s T ACS Address / Control Setup T ime 0 3 x T SYSCLK ns T ACW Addr.
C8051F340/1/2/3/4/5/6/7 134 Rev. 0.5 N OTES :.
Rev. 0.5 135 C8051F340/1/2/3/4/5/6/7 14. Oscillators C8051F340/1/2/3/4/5/6/7 de vices include a prog rammable internal high-fre quency oscillator , a program - mable internal low-frequency oscillator (C8051F 340/1/2/3/4/5), an exte rnal oscillator drive circuit, and a 4x Clock Multiplier .
C8051F340/1/2/3/4/5/6/7 136 Rev. 0.5 14.1. Programmable Internal Hi gh-Frequency (H-F) Oscillator All C8051F340/1/2/3/4/5/6/7 devices include a programmable internal oscillator that defaults as the system clock after a system rese t. The internal oscillato r period can be programmed via the OSCICL register shown in SFR Definition 14.
Rev. 0.5 137 C8051F340/1/2/3/4/5/6/7 SFR Definition 14.2. OSCICL: Internal H-F Oscillat or Calibration 14.2. Programmable Internal Low -Frequency (L-F) Oscillator The C8051F340/1/2/3/4/5 dev ices include a prog rammable internal os cillator which operat es at a nominal frequency of 80 kHz.
C8051F340/1/2/3/4/5/6/7 138 Rev. 0.5 SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control Bit7: OSC LEN: Internal L-F Oscillator Enable. 0: Internal L-F Oscillator Disabled. 1: Internal L-F Oscillator Enabled. Bit6: OSC LR DY : Internal L-F Oscillator Ready Flag.
Rev. 0.5 139 C8051F340/1/2/3/4/5/6/7 14.3. External Oscill ator Drive Circuit The external oscillator circuit may driv e an external crystal, ce ramic resonator , capacito r , or RC network.
C8051F340/1/2/3/4/5/6/7 140 Rev. 0.5 14.3.3. External RC Example If an RC network is used as an external oscillator so urce for the MCU, the circ uit should be configured as shown in Figure 14.
Rev. 0.5 141 C8051F340/1/2/3/4/5/6/7 SFR Definition 14.4. OSCXCN: External Oscillator Control Bit7: XTL VLD: Crystal Oscillator V a lid Flag. (Read only when XOSCMD = 1 1x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal Oscillator is running and stable.
C8051F340/1/2/3/4/5/6/7 142 Rev. 0.5 14.4. 4x Clock Multiplier The 4x Clock Multiplier allows a 12 MHz oscillator to generate the 48 MHz clock required for Full S peed USB communication (see Section “16.4. USB Clock Configuration” on p age 170 ). A divided version of the Multiplier output can also be used as the system clock.
Rev. 0.5 143 C8051F340/1/2/3/4/5/6/7 14.5. System and US B Clock Selection The internal oscillator requires littl e start-up time and may be selected as the system or USB clock immedi - ately following the O SCICN write that enab les th e inte rnal oscillator .
C8051F340/1/2/3/4/5/6/7 144 Rev. 0.5 SFR Definition 14.6. CLKSEL: Clock Select Bit 7: Unused. Read = 0b; Write = do n’t care. Bits6–4: USBCLK2–0: USB Clock Select These bit s select the clock supplied to USB0. When oper ating USB0 in full-speed mode, th e selected clock should be 4 8 MHz.
Rev. 0.5 145 C8051F340/1/2/3/4/5/6/7 Ta b l e 14.1. Oscillator Electrical Characteristics V DD = 2.7 to 3.6 V ; –40 to +85 °C unless otherwise specified Parameter Conditions Min T yp Max Unit s Internal High-Frequency Oscillator (U sing Factory- Calibrated Settings ) Oscillator Frequency IFCN = 1 1b 1 1.
C8051F340/1/2/3/4/5/6/7 146 Rev. 0.5 N OTES :.
Rev. 0.5 147 C8051F340/1/2/3/4/5/6/7 15. Port Inp ut/Output Digital an d analog reso urces are ava ilable through 40 I/O pins (C8051F34 0/1/4/5) or 25 I/O pins (C8051F342/3/6/7). Port pins are orga nized as shown in Figure 15.1 . Each of the Port pins can be defined as general-pu r pose I/O (GPI O) or an a log in pu t; Port pi ns P0.
C8051F340/1/2/3/4/5/6/7 148 Rev. 0.5 Figure 15.2. Port I/O Cell Block Di agram GND /PORT-OUTE NABLE PORT-OUT PUT PUSH-P ULL VDD VDD /W EAK-PULLUP (WEA K) PORT PAD ANALOG INPUT Analog Select PORT-INP U.
Rev. 0.5 149 C8051F340/1/2/3/4/5/6/7 15.1. Priority Crossbar Decoder The Priority Crossb ar Decoder (F igure 15.3) assigns a priority to each I/O function, starting a t the top with UART0.
C8051F340/1/2/3/4/5/6/7 150 Rev. 0.5 Figure 15.4. Crossbar Priority D ecoder with Cryst al Pins Skipped Registers XBR0, XBR1, and XBR2 ar e used to assign the d igital I/O r esources to the physical I/O Po rt pins.
Rev. 0.5 151 C8051F340/1/2/3/4/5/6/7 15.2. Port I/O Initialization Port I/O initialization consis ts of the following step s: S tep 1. Select the input mode (analog or digital) for all Por t pins, using the Port Input Mode register (PnMDIN).
C8051F340/1/2/3/4/5/6/7 152 Rev. 0.5 SFR Definition 15.1. XBR0: Port I/O Cro ssbar Register 0 Bit7: CP1AE: Comparator1 Asynchronou s Output Enable 0: Asynchronou s CP1 un av ailable at Port pin. 1: Asynchro nous CP1 ro uted to Por t pin. Bit6: CP1E: Comparator1 Output En able 0: CP1 unavailable at Port pin.
Rev. 0.5 153 C8051F340/1/2/3/4/5/6/7 SFR Definition 15.2. XBR1: Port I/O Cro ssbar Register 1 SFR Definition 15.3. XBR2: Port I/O Cro ssbar Register 2 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-up s enabled (except for Port s whose I/O are configured as analog input or push-pull output).
C8051F340/1/2/3/4/5/6/7 154 Rev. 0.5 15.3. General Purpose Port I/O Port pins that remain un assigned by the Crossbar an d are not used by analog p eripherals can be used for general purpo se I/O. Port s 3-0 are accessed through corresponding special function registers (S FRs) that are both byte addressable and bit addressable.
Rev. 0.5 155 C8051F340/1/2/3/4/5/6/7 SFR Definition 15.6. P0MDOUT : Port0 Output Mode SFR Definition 15.7. P0SKIP: Port0 Skip Bits7–0: Output Configuration Bit s for P0.7–P0.0 (res pe ctively): ignored if corresponding bit in regis- ter P0MDIN is logic 0.
C8051F340/1/2/3/4/5/6/7 156 Rev. 0.5 SFR Definition 15.8. P1: Port1 Latch SFR Definition 15.9. P1MDIN: Port1 Input Mode SFR Definition 15.10. P1MDOUT : Port1 Output Mode Bits7–0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Re gisters (when XBARE = ‘1’).
Rev. 0.5 157 C8051F340/1/2/3/4/5/6/7 SFR Definition 15.1 1. P1SKIP: Port1 Skip SFR Definition 15.12. P2: Port2 Latch SFR Definition 15.13. P2MDIN: Port2 Input Mode Bits7–0: P1SKIP[7:0]: Port1 Cr ossbar Skip Enable Bits. These bits select Por t pin s to be skipped by the Crossbar Decoder .
C8051F340/1/2/3/4/5/6/7 158 Rev. 0.5 SFR Definition 15.14. P2MDOUT : Port2 Output Mode SFR Definiti on 15.15. P2SKIP: Port2 Skip Bits7–0: Output Configuration Bit s for P2.7–P2.0 (res pe ctively): ignored if corresponding bit in regis- ter P2MDIN is logic 0.
Rev. 0.5 159 C8051F340/1/2/3/4/5/6/7 SFR Definition 15.16. P3: Port3 Latch SFR Definition 15.17. P3MDIN: Port3 Input Mode SFR Definition 15.18. P3MDOUT : Port3 Output Mode Bits7–0: P3.[7:0] Write - Outp ut appears on I/O pins. 0: Logic Low O utput. 1: Logic High O utput (high impedance if corresponding P3MDOUT .
C8051F340/1/2/3/4/5/6/7 160 Rev. 0.5 SFR Definiti on 15.19. P3SKIP: Port3 Skip SFR Definition 15.20. P4: Port4 Latch Bits7–0: P3SKIP[3:0]: Port3 Cr ossbar Skip Enable Bits.
Rev. 0.5 161 C8051F340/1/2/3/4/5/6/7 SFR Definition 15.21. P4MDIN: Port4 Input Mode SFR Definition 15.22. P4MDOUT : Port4 Output Mode Bits7–0: Analog Input Configuration Bit s for P4.7–P4.0 (respectively). Port pins configured as analog input s have their weak pull-u p, digital driver , and digit a l receiver disabled .
C8051F340/1/2/3/4/5/6/7 162 Rev. 0.5 Ta b l e 15.1. Port I/O DC Electri cal Characteristics V DD = 2.7 to 3.6 V , –40 to +85 °C u nless otherwise specified Parameters Conditions Min T yp Max Unit s Output High V oltage I OH = –3 mA, Port I/ O push-pull I OH = –10 µA, Port I/O push-pull I OH = –10 mA, Port I/O push-pull V DD – 0.
Rev. 0.5 163 C8051F340/1/2/3/4/5/6/7 16. Universal Serial Bus Controller (USB0) C8051F340/1/2/3/4/5/6/7 devices include a comple te Full/Low S peed USB function for USB peripheral implementations*.
C8051F340/1/2/3/4/5/6/7 164 Rev. 0.5 16.1. End point Addressing A total of eight endpoint pipes are available. T he control endpoint (E ndpoint0) al ways functions as a bi-directional IN/OUT end point. The other endpo ints are imple mented as three pairs of IN/OUT end point pipes: 16.
Rev. 0.5 165 C8051F340/1/2/3/4/5/6/7 SFR Definition 16.1. USB0XCN: USB0 T ransceiver Control Bit7: PREN : Internal Pu ll-up Resistor Enable The location of the pull-up resistor (D + or D–) is determined by the SPEED bit. 0: Internal pull-up resistor disabled (d evic e ef fectively det ached from the USB network).
C8051F340/1/2/3/4/5/6/7 166 Rev. 0.5 16.3. USB Register Access The USB0 controller reg isters listed in T able 16.2 ar e accessed th rough two SFRs : USB0 Addre ss (USB0ADR) and USB0 Data (USB0DA T). The USB0ADR register se lects which USB register is targeted by reads/writes of the USB0DA T register .
Rev. 0.5 167 C8051F340/1/2/3/4/5/6/7 SFR Definition 16.2. USB0ADR: USB0 Indirect Address Bits7: BUSY : USB0 Register Read Busy Flag This bit is used during indirect USB0 register ac cesses. Sof tware should wr ite ‘1’ to this bit to initiate a read of the USB0 register targeted by the USBAD DR bits (USB0ADR.
C8051F340/1/2/3/4/5/6/7 168 Rev. 0.5 SFR Definition 16.3. USB0DA T : USB0 Dat a This SFR is used to indirectly read and write USB0 registers. Wri te Procedure: 1. Poll for BUSY (USB 0AD R.7) => ‘0’. 2. Load the target USB0 register address into the USBADDR bits in register USB0ADR.
Rev. 0.5 169 C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.4. INDEX: USB0 End point Index Ta b l e 16.2. USB0 Controller Registers USB Register Name USB Register Address Description Page Numbe r .
C8051F340/1/2/3/4/5/6/7 170 Rev. 0.5 16.4. USB Clock Configuration USB0 is cap able of communication a s a Full or Low S peed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operati ng as a Low S peed func tion, the USB0 clock must be 6 MHz.
Rev. 0.5 171 C8051F340/1/2/3/4/5/6/7 16.5. FIFO Management 1024 bytes of on-chip XRAM a re used as FIFO sp ace for USB0. This FIFO space is sp lit between Endpoint s0-3 as shown in Figu re 16.3 . FIFO space allocated for End point s1-3 is configurable as IN, OUT , or both (S plit Mode: half IN, half OUT).
C8051F340/1/2/3/4/5/6/7 172 Rev. 0.5 16.5.2. FIFO Double Buffering FIFO slots for End point s1-3 can be configured for double-buffered mode. In this mode , the maximum packet size is halved an d the FIFO may cont ain tw o packets at a time. This mode is availa ble for Endpoint s1-3.
Rev. 0.5 173 C8051F340/1/2/3/4/5/6/7 16.6. Function Addressing The F ADDR register holds the current USB0 function addre ss. Soft ware should wr ite the host-assig ned 7-bit function address to the F ADDR register when rec eived as part of a SET_ADDRESS command.
C8051F340/1/2/3/4/5/6/7 174 Rev. 0.5 “14. Oscillators” on p age 135 for more details on internal oscillator configuration, in cluding the Suspend mode feature of the internal oscillator .
Rev. 0.5 175 C8051F340/1/2/3/4/5/6/7 USB Register Definition 16. 8. POWER: USB0 Power Bit7: ISO UD: ISO Update This bit af fects a ll IN Isochronous end points. 0: When software writes INPRDY = ‘1’, USB0 w ill send the pa cket when the next IN token is received.
C8051F340/1/2/3/4/5/6/7 176 Rev. 0.5 USB Register Definition 16.9. FRAMEL: USB0 Frame Number Low USB Register Definiti on 16.10. FRAMEH: US B0 Frame Number High 16.8. Interrupt s The read-only USB0 interru pt flags are located in the USB registers sh own in USB Register Definition 16.
Rev. 0.5 177 C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.1 1. IN1I NT : USB0 IN Endpoint Interrupt USB Register Definition 16.12. OUT1INT : USB0 Out Endpoint Interrupt Bits7–4: Unused. Read = 0000b. W rite = don’t care. Bit3: IN3: IN Endpoint 3 Interrupt-pend ing Flag This bit is cleare d when sof twa re reads the IN1INT register .
C8051F340/1/2/3/4/5/6/7 178 Rev. 0.5 USB Register Definition 16.13. CMINT : USB0 Common Interrupt Bits7–4: Unused. Read = 0000b; W rite = don’t care.
Rev. 0.5 179 C8051F340/1/2/3/4/5/6/7 USB Register Definition 16. 14. IN1IE: USB0 IN Endpoint Interrupt Enable USB Register Definition 16.15. OUT1IE: USB0 Out End point Interrupt Enable Bits7–4: Unused. Read = 0000b. W rite = don’t care. Bit3: IN3E: IN Endpoint 3 Interrupt Enable 0: IN Endpoint 3 inte rrupt disabl ed.
C8051F340/1/2/3/4/5/6/7 180 Rev. 0.5 USB Register Definition 16.16. CM IE: USB0 Common Interrupt Enable 16.9. The Serial Interface Engine The Serial Inter face Engine (SIE) perfor ms all low level USB protocol tasks, interr upting the processor when data has successfully been trans mitted or received.
Rev. 0.5 181 C8051F340/1/2/3/4/5/6/7 The E0CNT register (USB Register Defin ition 16.18) holds the n umber of received data bytes in th e Endpoint0 FIFO . Hardware will automatically detect protocol errors and send a ST AL L condition in response. Firmware may force a ST ALL conditio n to abo rt the cu rr ent tra nsfer .
C8051F340/1/2/3/4/5/6/7 182 Rev. 0.5 16.10.3.End point0 OUT T ransactions When a SETUP request is received that requires th e host to transmit data to USB0, one or more OUT requests will be sent by the host. W hen an OUT packet is su ccessfully received by USB0, hardware will set the OPRDY bit (E0CSR.
Rev. 0.5 183 C8051F340/1/2/3/4/5/6/7 USB Register Definiti on 16.17. E0CSR: USB0 End point0 Control Bit7: SSUEND: Serviced Setup End Wri t e: Software should set this bit to ‘1’ afte r serv icing a Setup En d (bit SUEND) e vent. Hardware clears the SUEND bit when software writes ‘1’ to SSUEND.
C8051F340/1/2/3/4/5/6/7 184 Rev. 0.5 USB Register Definiti on 16.18. E0CNT : USB0 Endpoint 0 Dat a Count 16.1 1. Configuring Endpoint s1-3 Endpoint s1-3 are config ured and cont ro lled through their own set s of the following co ntrol/status registers: IN registers EINCSRL and EINCSRH, and OUT re gi sters EOUTCSRL and EOUTCSRH.
Rev. 0.5 185 C8051F340/1/2/3/4/5/6/7 Writing ‘1’ to INPRDY without writin g any dat a to the endpoint FIFO w ill cause a zero-length p acket to be transmitted upon reception of the next IN token. A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EINCSRL.
C8051F340/1/2/3/4/5/6/7 186 Rev. 0.5 USB Register Definition 16.19. EINCSRL: USB0 IN Endpoint Control Low Byte Bit7: Unused. Read = 0; Write = don’t care. Bit6: CLRDT : Clear Data T oggle. Wri t e: Software should wr ite ‘1’ to this bit to reset the IN End point dat a toggle to ‘0’.
Rev. 0.5 187 C8051F340/1/2/3/4/5/6/7 USB Register Definition 16. 20. EINCSRH: USB0 IN En d point Control High Byte 16.13. Controlling Endpoint s1-3 OUT Endpoint s1-3 OUT are managed via USB registers EOUTCSRL and EOUTCSRH. All OUT endpoi nts can be used for In terr upt, Bulk, or Isochr onous transfers.
C8051F340/1/2/3/4/5/6/7 188 Rev. 0.5 A Bulk or Interrupt pi pe ca n be sh ut down ( or Halted ) by writing ‘1’ to the SDSTL bit (EOUTCSRL.5). While SDSTL = ‘1’, hardware will respond to all OUT requests with a ST ALL condi tion. Each time hardware gen - erates a ST ALL condition, an interr upt will be generated an d the STSTL bit (EOUTCSRL.
Rev. 0.5 189 C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.21. EOUTCSRL: USB0 OUT Endpoint Control Low Byte Bit7: CLRDT : Clear Data T oggle Wri t e: Software should wr ite ‘1’ to this bit to reset the OUT end point dat a toggle to ‘0’. Read: This bit always reads ‘0’.
C8051F340/1/2/3/4/5/6/7 190 Rev. 0.5 USB Register Defini tion 16.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte USB Register Definition 16.23. EOUTCNTL: USB0 OUT End point Count Low USB Register Definition 16.
Rev. 0.5 191 C8051F340/1/2/3/4/5/6/7 Ta b l e 16.4. USB T ransceiver Electri cal Characteristics V DD = 3.0 to 3.6 V , –40 to +85 °C u nless otherwise specified Parameters Symbol Conditions Min T yp Max Units Tr a n s m i t t e r Output High V oltage V OH 2.
C8051F340/1/2/3/4/5/6/7 192 Rev. 0.5 N OTES :.
Rev. 0.5 193 C8051F340/1/2/3/4/5/6/7 17. SMBus The SMBus I/O interface is a two-wire, bi-directional se rial bus. The SMBus is compliant with the System Management Bus S pecification, version 1.
C8051F340/1/2/3/4/5/6/7 194 Rev. 0.5 17.1. Supporting Document s It is assumed the reader is familiar with or has access to th e following suppo rting document s: 1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor . 2. The I2C-Bus S pecification -- V e rsion 2.
Rev. 0.5 195 C8051F340/1/2/3/4/5/6/7 The direction bi t (R/W) occupies the least-significan t bit position of th e address byte. The di rection bit is set to logic 1 to indicate a "READ" operation and cleare d to logic 0 to indicate a "WRITE" operation.
C8051F340/1/2/3/4/5/6/7 196 Rev. 0.5 17.3.2. Clock Low Extension SMBus provides a clock synchronizati on mechanism, similar to I2C, wh ich allows devices with dif ferent speed capabilities to coexist on the bus. A clock-low extensio n is used during a transf er in order to allow slower slave devices to communicate with faster masters.
Rev. 0.5 197 C8051F340/1/2/3/4/5/6/7 SMBus configuration optio ns include: • T imeout detection (SCL Low T imeout and/or Bus Free T imeout) • SDA setup and hold time extensions • Slave event en ab le /d isab le • Clock source selection These options are selected in the SMB0CF register , as described in Section “17.
C8051F340/1/2/3/4/5/6/7 198 Rev. 0.5 17.4.1. SMBus Configuration Register The SMBus Configuration re gister (S MB0CF) is used to en able the SMBus Master an d/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options.
Rev. 0.5 199 C8051F340/1/2/3/4/5/6/7 Figure 17.4 shows the typical SCL generation described by Equa tion 17.2. Notice that T HIGH is typically twice as large as T LOW . The actual SCL outpu t may vary due to other devices o n the bus (SCL may be extended lo w by slower sla ve devices, or d riven low by co ntending mast er devices).
C8051F340/1/2/3/4/5/6/7 200 Rev. 0.5 SFR Definition 17.1. SMB0CF: SMBus Clock/Configuration Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the inter face const antly mon- itors the SDA and SCL pin s. 0: SMBus interface disabled.
Rev. 0.5 201 C8051F340/1/2/3/4/5/6/7 17.4.2. SMB0CN Control Register SMB0CN is used to control the interface an d to provid e st atus information (see SFR Definition 17.2). The higher four bit s of SMB0CN (MASTER, TXMODE, ST A, and ST O) form a st atus vector that can be used to jump to service routines.
C8051F340/1/2/3/4/5/6/7 202 Rev. 0.5 SFR Definition 17.2. SMB0CN: SMBus Control Bit7: M ASTER: SMB us Mast er/Slave Indicator . This read-only bit indicates when the SMBus is operating as a master . 0: SMBus operating in Slave Mode. 1: SMBus operating in Master Mod e.
Rev. 0.5 203 C8051F340/1/2/3/4/5/6/7 Ta b l e 17.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: Cleared by Hardware When: MASTER • A ST AR T is gen erated. • A STOP is generated. • Arbitration is lost. TXMODE • ST AR T is generated .
C8051F340/1/2/3/4/5/6/7 204 Rev. 0.5 17.4.3. Data Re gister The SMBus Data registe r SMB0DA T holds a byte of serial dat a to be transmi tted or one that has just been received. Sof tware may safely rea d or write to the da ta register when the SI flag is set.
Rev. 0.5 205 C8051F340/1/2/3/4/5/6/7 Figure 17.5. T ypical Mast er T ransmitter Sequence A A A S W P Data Byte Data By te SLA S = START P = STOP A = ACK W = WR ITE SLA = Slave Addres s Received by SMB.
C8051F340/1/2/3/4/5/6/7 206 Rev. 0.5 17.5.2. Master Receiver Mode Serial data is receive d on SDA while t he serial c lock is output on SCL. The SMBus interfa ce generat es the ST ART condition and tr ansmits the first b yte cont aining the address of the tar get slave and the dat a direc - tion bit.
Rev. 0.5 207 C8051F340/1/2/3/4/5/6/7 17.5.3. Slave Receiver Mode Serial data is received on SDA and the clock is re ceived on SCL. When slave event s are enabled (INH = 0), the inter face en ters Slav e Rece iver Mo de wh en a ST ART followed by a s lav e addr ess an d dir ectio n bit (WRITE in this case) is received.
C8051F340/1/2/3/4/5/6/7 208 Rev. 0.5 17.5.4. Slave T ransmitter Mode Serial dat a is transmi tted on SDA and the clock is re ceived on SCL . When slave even ts are en abled (INH = 0), the interface en.
Rev. 0.5 209 C8051F340/1/2/3/4/5/6/7 Ta b l e 17.4. SMBus St atus Decoding Mode V alues Read Current SMbus S t ate T ypical Response Options Va l u e s Wri t te n Stat us Ve c t o r ACKRQ ARBLOST ACK ST A ST o ACK Master T ransmitter 111 0 0 0 X A master ST ART was gen erated.
C8051F340/1/2/3/4/5/6/7 210 Rev. 0.5 Slave T ransmitter 0100 000 A slave byte was transmitted; NACK received. No action required (expect - ing ST OP condition). 0 0 X 001 A slave byte was transmitted; ACK received. Lo ad SMB0DA T with next data byte to transmit.
Rev. 0.5 211 C8051F340/1/2/3/4/5/6/7 18. UART0 UART0 is an asynchronous , full duplex serial port offering modes 1 and 3 of the standard 805 1 UART . Enhanced baud rate su pport allows a wide r ange o f clock sour ces to gene rate st andard baud rates (de t ails in Section “18.
C8051F340/1/2/3/4/5/6/7 212 Rev. 0.5 18.1. Enhanced Baud Rate Generation The UART 0 baud rate is generated by T imer 1 in 8-bit auto-reload mode. The TX clock is genera ted by TL1; the RX clock is generated by a copy of TL1 (shown as RX T imer in Figure 18.
Rev. 0.5 213 C8051F340/1/2/3/4/5/6/7 Figure 18.3. UART Interconnect Diagram 18.2.1. 8-Bit UART 8-Bit UART mode uses a total of 10 bits per dat a byte: one st art bit, e ight dat a bit s (LSB first), a nd one stop bit. Data are transm itted LSB firs t from the TX0 pin a nd received at the RX0 pin.
C8051F340/1/2/3/4/5/6/7 214 Rev. 0.5 18.2.2. 9-Bit UART 9-bit UAR T mode uses a tot al of eleven bit s per data byte: a start bit, 8 data b its ( LSB first), a prog ramma - ble ninth dat a bit, and a stop bit. The state of the nint h transmit data bit is determ ined by the v alue in TB80 (SCON0.
Rev. 0.5 215 C8051F340/1/2/3/4/5/6/7 Figure 18.6. UART Multi-Processor Mode Interconnect Diagram Master Device Slave Device TX RX RX TX Slave Device RX TX Slave Device RX TX V+.
C8051F340/1/2/3/4/5/6/7 216 Rev. 0.5 SFR Definition 18.1. SCON0: Serial Port 0 Control Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the U ART0 Operation Mode . 0: 8-bit UAR T with V ariable Baud Rate. 1: 9-bit UAR T with V ariable Baud Rate.
Rev. 0.5 217 C8051F340/1/2/3/4/5/6/7 SFR Definition 18.2. SBUF0: Serial (UART0 ) Port Dat a Buffer Bits7–0: SBUF0[7:0]: Serial Da ta Buf fer Bit s 7–0 (MSB-LSB) This SFR accesses tw o registers; a transmit sh ift register and a receive latch re gister .
C8051F340/1/2/3/4/5/6/7 218 Rev. 0.5 Ta b l e 18.1. T imer Settings for St andard Baud Rates Using The In ternal Oscillator Ta r g e t Baud Rate (bp s) Actual Baud Rate (bp s) Baud Rate Error Oscillator Divide Factor Tim er Cl o ck Source SCA1-SCA0 (pre-scale select* T1M* Tim e r 1 Reload Va l u e ( h e x ) SYSCLK = 12 MHz 230400 23076 9 0.
Rev. 0.5 219 C8051F340/1/2/3/4/5/6/7 19. UART1 (C8051F340/1/4/5 Only) UART1 is an asynch ronou s, full dup lex serial port of feri ng a variety of data formatting options. A dedicated baud rate generator with a 16-bi t timer and select able prescaler is included, which can generate a wide range of baud rates (det ails in Sect ion “19.
C8051F340/1/2/3/4/5/6/7 220 Rev. 0.5 19.1. Baud Rate Generator The UAR T1 baud rate is generated by a dedicated 16-bi t timer which runs fr om the controller ’s core clock (SYSCLK), and has prescaler options of 1, 4, 12, or 48. Th e timer and prescaler op tions combined allow for a wide selection of baud rates over many SYSCLK fre que ncies.
Rev. 0.5 221 C8051F340/1/2/3/4/5/6/7 19.2. Dat a Format UART1 ha s a number of available options for d ata format ting. Data tr ansfers begin with a st art bit (logic low), followed by the data bit s (sent LSB- first), a parity or extra bit (if selecte d), and end with o ne or two stop bits (logic high ).
C8051F340/1/2/3/4/5/6/7 222 Rev. 0.5 19.3. Configuration and Operation UART1 pro vides standa rd asynchronous, full d uplex communication. It can operate in a po int-to-point serial communications a pplication, or as a node on a multi-processor serial in terface.
Rev. 0.5 223 C8051F340/1/2/3/4/5/6/7 byte in the FIFO. After SBUF1 is re ad, the next byte in the FIFO is loaded into SBUF 1, and space is made available in the FIFO for anothe r incoming byte.
C8051F340/1/2/3/4/5/6/7 224 Rev. 0.5 SFR Definition 19.1. SCON1: UART1 Control Bit7: OVR1: Rece ive FIFO Over run Flag. This bit is used to indicate a re ceive F IF O ove r ru n con d itio n. 0: Receive F IFO Overrun has not occ urred. 1: Receive FIFO Overrun has occurred (an incom i ng character was discarded due to a full FIFO).
Rev. 0.5 225 C8051F340/1/2/3/4/5/6/7 SFR Definition 19.2. SMOD1: UART1 Mode Bit7: M CE1: Multiprocessor Communication Enable . 0: RI will be activated if stop bit(s) are ‘1’. 1: RI will be activated if stop bit(s) and extra bit are ‘1’ (e xtra bit must be enabled using XBE1).
C8051F340/1/2/3/4/5/6/7 226 Rev. 0.5 SFR Definition 19.3. SBUF1: UART1 Data Buffer SFR Definition 19.4. SBCON1: UART1 Baud Rate Generator Control Bits7–0: SBUF1[7:0]: Serial Da ta Buf fer Bit s 7–0 (MSB-LSB) This SFR is used to both send data fro m th e UART an d to read received dat a from the UART1 receive FIFO.
Rev. 0.5 227 C8051F340/1/2/3/4/5/6/7 SFR Definition 19.5. SBRLH1: UART1 Baud Rate Generator High Byte SFR Definition 19.6. SBRLL1: UART1 Baud Rate Generator Low Byte Bits7–0: SBR LH1[7:0]: High Byte of relo ad value for UART1 Baud Rate Genera to r .
C8051F340/1/2/3/4/5/6/7 228 Rev. 0.5 N OTES :.
Rev. 0.5 229 C8051F340/1/2/3/4/5/6/7 20. Enhanced Serial Peri pheral Interface (SPI0) The Enhanced Ser ial Periphera l Interface (SPI0) pr ov ides access to a flexible, full-duplex synchronous serial bus.
C8051F340/1/2/3/4/5/6/7 230 Rev. 0.5 20.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below . 20.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) sig nal is an output fr om a master dev ice and an inpu t to slav e dev ices.
Rev. 0.5 231 C8051F340/1/2/3/4/5/6/7 20.2. SPI0 Master Mode Operation A SPI master device initiate s all data tra nsfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). W riting a byte of da ta to the SPI0 data reg ister (SPI0DA T) when in master mode writes to the transmit buf fe r .
C8051F340/1/2/3/4/5/6/7 232 Rev. 0.5 Figure 20.2. Multiple-Master Mode Connect ion Diagram Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram Figure 20.
Rev. 0.5 233 C8051F340/1/2/3/4/5/6/7 20.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master , it will operate as a SPI slav e. As a slave, bytes are shifted in through the MOSI pin a nd out through the MISO pin by a ma ster device controlling the SCK sig - nal.
C8051F340/1/2/3/4/5/6/7 234 Rev. 0.5 20.5. Serial Clock Timing Four combinations of ser ial clock p hase and polarity can be selected using the cloc k control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit ( SPI0CFG .5) selects one of two clock ph ases (edge used to latch the dat a).
Rev. 0.5 235 C8051F340/1/2/3/4/5/6/7 Figure 20.6. Slave Mode Data /Clock T iming (CKPHA = 0) Figure 20.7. Slave Mode Data /Clock T iming (CKPHA = 1) MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MIS O.
C8051F340/1/2/3/4/5/6/7 236 Rev. 0.5 20.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system contr oller: SPI0CN Control Register , SPI0DA T Data Re gister , SPI0CFG Configura tion Register , and SPI0CKR C lock Rate Register .
Rev. 0.5 237 C8051F340/1/2/3/4/5/6/7 SFR Definition 20.2. SPI0CN: SPI0 Control Bit 7: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a dat a trans fer . If interrupt s are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine.
C8051F340/1/2/3/4/5/6/7 238 Rev. 0.5 SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate SFR Definition 20.4. SPI0DA T : SPI0 Dat a Bits 7–0: SCR7–SCR0: SPI0 Clock Rate. These bit s determine the frequ ency of the SCK output when the SPI0 module is con figured for master mode operatio n.
Rev. 0.5 239 C8051F340/1/2/3/4/5/6/7 Figure 20.8. SPI Master Tim in g (C K PH A = 0 ) Figure 20.9. SPI Master Tim in g (C K PH A = 1 ) SCK* T MCKH T MCKL MOSI T MIS MISO * SCK is shown f or CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. T MIH SCK* T MCKH T MCK L MISO T MIH MOSI * SCK is sh own for CKPOL = 0.
C8051F340/1/2/3/4/5/6/7 240 Rev. 0.5 Figure 20.10. SPI Slave Timing (CKPHA = 0) Figure 20.1 1. SPI Slave Timing (CKPHA = 1) SCK* T SE NSS T CKH T CKL MOSI T SIS T SIH MISO T SD T SOH * SCK is shown for CKPOL = 0. SCK is the op posite polarity for CKPOL = 1.
Rev. 0.5 241 C8051F340/1/2/3/4/5/6/7 Ta b l e 20.1. SPI Slave Timing Parameters Paramete r Description Min Max Unit s Master Mode T iming* (See Figure 20.
C8051F340/1/2/3/4/5/6/7 242 Rev. 0.5 N OTES :.
Rev. 0.5 243 C8051F340/1/2/3/4/5/6/7 21. T imers Each MCU includes four counter/timers: two ar e 16-bit counter/time rs compatible with th ose found in the standar d 8051, and two are 16 -bit auto-reload timer for use with th e ADC, SMBus, USB (frame measure - ments), Low-Frequency Oscillator (p eriod measurements), or for general purpose use.
C8051F340/1/2/3/4/5/6/7 244 Rev. 0.5 The C/T0 bit (TMOD.2) selects the cou nter/timer's cloc k source. Whe n C/T0 is set to logic 1, high-to-low transitions at the selected T imer 0 input pin (T0) incremen t the timer register (Refer to Se ction “15.
Rev. 0.5 245 C8051F340/1/2/3/4/5/6/7 21.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configur es T imer 0 and T imer 1 to ope rate as 8- bit counter/time rs with automatic reload of the st art value. TL0 holds the count and T H0 holds the reload va lue.
C8051F340/1/2/3/4/5/6/7 246 Rev. 0.5 21.1.4. Mode 3: T wo 8-bit Counter/T imers (T imer 0 Only) In Mode 3, T imer 0 is configured as two separate 8- bit counter/time rs held in TL0 and TH0. The coun ter/ timer in TL0 is co ntrolled using the T imer 0 control/status bits in TCO N and TMOD: T R0, C/T0, GA TE0 a nd TF0.
Rev. 0.5 247 C8051F340/1/2/3/4/5/6/7 SFR Definition 21.1. TCON: T imer Control Bit7: TF1: Timer 1 Over flow Flag. Set by hardware when T imer 1 overflows. This flag can be cleared by soft ware but is auto- matically cleared when the CPU vectors to the T imer 1 interrupt service routine.
C8051F340/1/2/3/4/5/6/7 248 Rev. 0.5 SFR Definition 21.2. TMOD: Timer Mode Bit7: GA TE1: Ti me r 1 Gate Control. 0: T imer 1 enabled when TR1 = 1 irres pe ctiv e of /IN T1 log ic leve l. 1: T imer 1 enabled only whe n TR1 = 1 AND /INT1 is active as defined by bit IN1PL in regis- ter INT01CF (see SFR Definition 9.
Rev. 0.5 249 C8051F340/1/2/3/4/5/6/7 SFR Definition 21.3. CKCON: Clock Control Bit7: T3MH: T imer 3 H igh Byte Clock Select. This bit selects th e clock supplied to the T imer 3 high byte if T imer 3 is configured in sp lit 8-bit timer mode. T3MH is ignor ed if T imer 3 is in any other mode.
C8051F340/1/2/3/4/5/6/7 250 Rev. 0.5 SFR Definition 21.4. TL0: T imer 0 Low Byte SFR Definition 21.5. TL1: T imer 1 Low Byte SFR Definition 21.6. TH0: T imer 0 High Byte SFR Definition 21.7. TH1: T imer 1 High Byte Bits 7–0 : TL0: T imer 0 Lo w Byte.
Rev. 0.5 251 C8051F340/1/2/3/4/5/6/7 21.2. Timer 2 T imer 2 is a 16-bit time r formed by two 8-bi t SFRs: TMR2L (low byte) and TMR2H (high by te). T imer 2 may operate in 16-bit a uto-reload mode, (sp lit) 8-bit auto-reload mode, USB S tart-of-Frame (SOF) ca pture mode, or Low-Frequency Os cillator (LFO) Falling Edge capture mode.
C8051F340/1/2/3/4/5/6/7 252 Rev. 0.5 21.2.2. 8-bit Timers with Auto-Reload When T2SPLIT = ‘ 1’ and T2CE = ‘0’, T imer 2 operates as two 8-bit timers ( TMR2H and TMR2L) . Both 8-bit timers operate in auto-reload mode as shown in Figur e 21.5 . TMR2RLL holds the reload value for TMR2 L; TMR2RLH holds the re load value for TMR2H.
Rev. 0.5 253 C8051F340/1/2/3/4/5/6/7 21.2.3. Timer 2 Capture Modes: USB S t art-of-Fra me or LFO Falling Edge When T2CE = ‘1’, T imer 2 will operate in one of two special capture modes. The capture event can be selected between a USB S tart-of-Frame (SOF) capture, and a Low- Frequency Oscillator (LFO) Falling Edge capture, using the T2CSS bit.
C8051F340/1/2/3/4/5/6/7 254 Rev. 0.5 When T2SPLIT = ‘1’, the T imer 2 registers (TMR2H and TMR2L) act as two 8-bit counte rs. Each counter counts up indepe ndently and overflows fro m 0xFF to 0x00.
Rev. 0.5 255 C8051F340/1/2/3/4/5/6/7 SFR Definition 21.8. TMR2CN: Timer 2 Control Bit7: T F2H: T imer 2 High Byte Overflow Flag. Set by hardware when the T imer 2 high byte ov erflows from 0xFF to 0x00. In 16 bit mod e, this will occur when T imer 2 overflows from 0xFF FF to 0x0000.
C8051F340/1/2/3/4/5/6/7 256 Rev. 0.5 SFR Definition 21.9. TMR2RLL: Timer 2 Relo ad Register Low Byte SFR Definition 21.10. TMR2RLH: T imer 2 Relo ad Register High Byte SFR Definition 21.1 1. TMR2L: Timer 2 Low Byte SFR Definition 21.12. TMR2H T imer 2 High Byte Bits 7–0: TMR2RLL: T imer 2 Reload Register Low Byte.
Rev. 0.5 257 C8051F340/1/2/3/4/5/6/7 21.3. Timer 3 T imer 3 is a 16-bit time r formed by two 8-bi t SFRs: TMR3L (low byte) and TMR3H (high by te). T imer 3 may operate in 16-bit a uto-reload mode, (sp lit) 8-bit auto-reload mode, USB S tart-of-Frame (SOF) ca pture mode, or Low-Frequency Os cillator (LFO) Rising Edge capture mode.
C8051F340/1/2/3/4/5/6/7 258 Rev. 0.5 21.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is ‘1’ and T3CE = ‘0’, T imer 3 operates as two 8-bi t timers (TMR3H and TMR3L). Both 8-bit timers operate in auto-reload mode as shown in Figur e 21.5 . TMR3RLL holds the reload value for TMR3 L; TMR3RLH holds the re load value for TMR3H.
Rev. 0.5 259 C8051F340/1/2/3/4/5/6/7 21.3.3. USB St art-of-Frame Capture When T3CE = ‘1’, T imer 3 will operate in one of two special capture modes. The capture event can be selected between a USB S t art-of-Frame (SOF) captur e, and a Low-Fr equency Oscillator (LFO) Rising Edge capture, using the T3CSS bit.
C8051F340/1/2/3/4/5/6/7 260 Rev. 0.5 When T3SPLIT = ‘1’, the T imer 3 registers (TMR3H and TMR3L) act as two 8-bit counte rs. Each counter counts up indepe ndently and overflows fro m 0xFF to 0x00.
Rev. 0.5 261 C8051F340/1/2/3/4/5/6/7 SFR Definition 21.13. TMR3CN: T imer 3 Control Bit7: T F3H: T imer 3 High Byte Overflow Flag. Set by hardware when the T imer 3 high byte ov erflows from 0xFF to 0x00. In 16 bit mod e, this will occur when T imer 3 overflows from 0xFF FF to 0x0000.
C8051F340/1/2/3/4/5/6/7 262 Rev. 0.5 SFR Definiti on 21.14. TMR3RLL: Timer 3 Reload Register Low Byte SFR Definition 21.15. TMR3RLH: T imer 3 Relo ad Register High Byte SFR Definition 21.16. TMR3L: T imer 3 Low Byte SFR Definition 21.17. TMR3H T imer 3 High Byte Bits 7–0: TMR3RLL: T imer 3 Reload Register Low Byte.
Rev. 0.5 263 C8051F340/1/2/3/4/5/6/7 22. Programmable Counter Array (PCA0) The Programmable Cou nter Array (PCA0) provides enh anced timer functionality while req uiring less CPU intervention th an the standard 80 51 counter/timers. Th e PCA co nsists of a dedicat ed 16-bit counter/timer and five 16-bit capt ure/compare module s.
C8051F340/1/2/3/4/5/6/7 264 Rev. 0.5 22.1. PCA Counter/Timer The 16-bit PCA counter/tim er consists o f two 8-bi t SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-b it counter/timer an d PCA0L is the low byte (LSB).
Rev. 0.5 265 C8051F340/1/2/3/4/5/6/7 22.2. Capture/Comp are Modules Each module can b e configured to op erate independen tly in one of six operation modes: Edge-triggered Capture, Soft ware T imer , High S peed Output, Frequency Output, 8-Bit Pulse Wid th Modulator , or 16-Bit Pulse Width Modulat or .
C8051F340/1/2/3/4/5/6/7 266 Rev. 0.5 22.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin ca uses the PCA to capture th e value of the PCA counter/ timer and load it into the corr esponding module' s 16-bit capture/comp are register (PCA0CPL n and PCA0CPHn).
Rev. 0.5 267 C8051F340/1/2/3/4/5/6/7 22.2.2. Software T imer (Comp are) Mode In Sof twa re T imer mode, the PCA counter/timer valu e is comp ared to the module' s 16-bit capture/ comp ar e register (PCA0CPHn and PCA0CPLn) .
C8051F340/1/2/3/4/5/6/7 268 Rev. 0.5 22.2.3. High Speed Output Mode In High S peed Output mode, a module’ s associated CEXn pin is toggled ea ch time a match occu rs between the PCA Co unter and the.
Rev. 0.5 269 C8051F340/1/2/3/4/5/6/7 22.2.4. Frequency Output Mode Frequency Output Mode p roduces a programmable- freq uency squar e wave on the module’ s associated CEXn pin. The ca pture/compare mo dule high byte holds the number of PCA clocks to count before the out - put is toggled.
C8051F340/1/2/3/4/5/6/7 270 Rev. 0.5 22.2.5. 8-Bit Pulse Wid th Modulator Mode Each module can be u sed inde pende ntly to gen erate a pulse wid th mod ulated (PWM ) outp ut on it s associ - ated CEXn pin. The frequency of the output is de pe ndent on the timebase for the PCA counter/timer .
Rev. 0.5 271 C8051F340/1/2/3/4/5/6/7 22.2.6. 16-Bit Pulse Wid th Modulator Mode A PCA module may also be o perate d in 16-Bit PWM mod e. In th is m ode , the 16- bit captu re/comp are mod - ule defines the numbe r o f PCA clocks for the low tim e of the PWM signal.
C8051F340/1/2/3/4/5/6/7 272 Rev. 0.5 22.3. W atchdog Timer Mode A programmable wa tchdog timer (WDT) function is avai l able throu gh the PCA Module 4. The WDT is used to generate a reset if the time between writes to th e WDT up da te reg ister ( PCA0 CPH4 ) exceed a spe cified limit.
Rev. 0.5 273 C8051F340/1/2/3/4/5/6/7 Equation 22.4. W atchdog Timer Offset in PCA Clocks The WDT reset is gener ated when PCA0L overflo w s while there is a match betwe en PCA0CPH4 and PCA0H. Software may force a WDT reset by wr iting a ‘1’ to the CCF4 flag (PCA0CN.
C8051F340/1/2/3/4/5/6/7 274 Rev. 0.5 22.4. Register Descriptions for PCA Following are deta iled descriptions of the special function regi sters related to the operation of the PCA. SFR Definition 22.1. PCA0CN: PCA Control Bit7: CF: P CA Counter/T imer Overflow Flag.
Rev. 0.5 275 C8051F340/1/2/3/4/5/6/7 SFR Definition 22.2. PCA0MD: PCA Mode Bit7: CID L: PCA Counter/Timer Idle Control. S pecifies PCA behavior wh en CPU is in Idle Mode. 0: PCA continues to function normally while the system controller is in Idle Mode.
C8051F340/1/2/3/4/5/6/7 276 Rev. 0.5 SFR Definition 22.3. PCA0CPMn: PCA Capture/Compare Mode PCA0CPMn Address: PCA0CPM0 = 0xDA (n = 0), PCA0CPM1 = 0xDB (n = 1), PCA0CPM2 = 0xDC (n = 2), PCA0CP M3 = 0xDD (n = 3), PCA0CPM4 = 0xDE (n = 4) Bit7: PWM16n: 16-bit Pulse Width Modulation Ena ble.
Rev. 0.5 277 C8051F340/1/2/3/4/5/6/7 SFR Definition 22.4. PCA0L: PCA Counter/T imer Low Byte SFR Definition 22.5. PCA0H: PCA Counter /Timer High Byte SFR Definition 22.6. PCA0CPLn: PCA Capture Module Low Byte Bits 7–0: PCA0L: PCA Counter/T imer Low Byte.
C8051F340/1/2/3/4/5/6/7 278 Rev. 0.5 SFR Definition 22.7. PCA0CPHn: PCA Captur e Module High Byte PCA0CPHn Address: PCA0CPH0 = 0xFC (n = 0), PCA0CPH1 = 0xEA (n = 1), PCA0CPH2 = 0xEC (n = 2), PCA0CPH3 = 0xEE (n = 3), PCA0CPH4 = 0xFE (n = 4) Bits7–0: PCA0CPHn: PCA Capture Mod ule High Byte.
Rev. 0.5 279 C8051F340/1/2/3/4/5/6/7 23. C2 Interface C8051F340/1/2/3/4/5/6/7 devic es include an on-chip Silicon Labs 2- Wire (C2) debug in terface to allow Flash programming a nd in-system debuggin g with the produ ction p art inst alled in the end application.
C8051F340/1/2/3/4/5/6/7 280 Rev. 0.5 C2 Register Definition 23.3. REVID: C2 Revision ID C2 Register Definition 23.4. FPCTL: C2 Flash Programming Control C2 Register Definition 23.5. FPDA T : C2 Flash Programming Data This read-on ly register r eturns the 8- bit revision ID .
Rev. 0.5 281 C8051F340/1/2/3/4/5/6/7 23.2. C2 Pin Sharing The C2 protocol allows th e C2 pins to be shar ed wi th user functions so that in-system debugging and Flash programming fun ctions may be performed.
C8051F340/1/2/3/4/5/6/7 282 Rev. 0.5 C ONT ACT I NFORMATION Silicon Laborato ries Inc. 4635 Boston Lane Austin, TX 78735 T el: 1+(512) 416-8500 Fax: 1+(512) 416-9669 T oll Free: 1+(87 7) 444-3032 Email: MCUinfo@silabs.com Internet: www .silabs.com Silicon Laboratories and Silicon Labs are trademarks of Silico n Laboratories Inc.
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