Gebruiksaanwijzing /service van het product DAC8555EVM van de fabrikant Texas Instruments
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User's Guide SLAU204 – December 2006 DAC8555EVM User's Guide This user’s guide describes the characteristics, operation and use of the DAC8555 Evaluation Module (EVM). It covers all matters related to proper use and configuration of this EVM along with the devices that it supports.
www.ti.com Contents 1 Overview ............................................................................................. 3 2 PCB Design and Performance .................................................................... 6 3 EVM Operation ........
www.ti.com 1 Overview 1.1 Features 1.2 Power Requirements 1.2.1 Supply Voltage 1.2.2 Reference Voltage Overview This section gives a general overview of the DAC8555EVM and describes some of the factors that must be considered when using this demonstration board.
www.ti.com 1.3 EVM Basic Functions Overview CAUTION When applying an external voltage reference through TP2 or J4-20, make sure that it does not exceed +5V maximum. External voltage references in excess of +5V can permanently damage the DAC8555 being tested (U1).
www.ti.com JMP1 1 JMP12 JMP13 JMP14 External Reference Module +5V A V DD +3.3V A (J2A) (J2B) DACModule (J4A) (J4B) 8CH (J1) (J5) (J3A) (J3B) 4CH JMP15 JMP16 JMP9 JMP10 DACOut V SS V H REF TP4 TP3 V CC GND V SS GND V DD +5V A +3.
www.ti.com 1.3.1 Related Documentation from Texas Instruments 2 PCB Design and Performance 2.1 PCB Layout PCB Design and Performance The following documents provide information regarding Texas Instrument integrated circuits used in the assembly of the DAC8555EVM.
www.ti.com PCB Design and Performance Figure 2. DAC8555EVM PCB—Top Silkscreen Image Figure 3. DAC8555EVM PCB—Layer 1 (Top Signal Layer) SLAU204 – December 2006 DAC8555EVM User's Guide 7 Sub.
www.ti.com PCB Design and Performance Figure 4. DAC8555EVM PCB—Layer 2 (Ground Plane) Figure 5. DAC8555EVM PCB—Layer 3 (Power Plane) 8 DAC8555EVM User's Guide SLAU204 – December 2006 Submit.
www.ti.com PCB Design and Performance Figure 6. DAC8555EVM PCB—Layer 4 (Bottom Signal Layer) Figure 7. DAC8555EVM PCB—Bottom Silkscreen Image SLAU204 – December 2006 DAC8555EVM User's Guide.
www.ti.com 2.2 EVM Performance PCB Design and Performance Figure 8. DAC8555EVM—Drill Drawing The EVM performance test is executed using a high-density DAC bench test board, an Agilent 3458A digital multimeter and a PC running LabVIEW™ software. The EVM board is tested for linearity for all codes between 485 and 64741.
www.ti.com PCB Design and Performance Figure 9. INL and DNL Characterization Graph of DAC A SLAU204 – December 2006 DAC8555EVM User's Guide 11 Submit Documentation Feedback.
www.ti.com PCB Design and Performance Figure 10. INL and DNL Characterization Graph of DAC B 12 DAC8555EVM User's Guide SLAU204 – December 2006 Submit Documentation Feedback.
www.ti.com PCB Design and Performance Figure 11. INL and DNL Characterization Graph of DAC C SLAU204 – December 2006 DAC8555EVM User's Guide 13 Submit Documentation Feedback.
www.ti.com PCB Design and Performance Figure 12. INL and DNL Characterization Graph of DAC D DAC8555EVM User's Guide 14 SLAU204 – December 2006 Submit Documentation Feedback.
www.ti.com 2.3 Bill of Materials PCB Design and Performance The parts list, showing the components used in the assembly of the DAC8555EVM, is given in Table 1 .
www.ti.com 3 EVM Operation 3.1 Default Settings 3.2 Host Processor Interface 3.3 EVM Stacking EVM Operation This section covers the operation of the EVM in detail, in order to provide guidance to the user in evaluating the onboard DAC as well as how to interface the EVM to a specific host processor.
www.ti.com 3.4 Output Op Amp EVM Operation Table 3. DAC Output Channel Mapping Reference Jumper Position Function 1-2 DAC output A (V OUT A) is routed to J4-2. JMP11 2-3 DAC output A (V OUT A) is routed to J4-10. 1-2 DAC output B (V OUT B) is routed to J4-4.
www.ti.com 3.4.1 Unity Gain Output 3.4.2 Output Gain of 2 EVM Operation The buffered output configuration can be used to prevent loading of the DAC8555, though it may add some slight distortion because of the feedback resistor and capacitor.
www.ti.com 3.4.3 Capacitive Load Drive 3.5 Optional Signal Conditioning Op-Amp (U4B) 3.6 Jumper Settings EVM Operation It may be required to drive a wide range of capacitive loads. However, under certain conditions, all op amps may become unstable, depending on the op amp configuration, gain, and load value.
www.ti.com 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 EVM Operation Table 7. Jumper Settings and Functions (continued) Reference Jumper Setting (1) Function RST pin is set high through pull-up resistor R4. RST can be driven by GPIO5, J2-19. JMP4 RST pin is set low.
www.ti.com 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 EVM Operation Table 7. Jumper Settings and Functions (continued) Reference Jumper Setting (1) Function Routes V OUT B to J4-4. JMP12 Routes V OUT B to J4-12. Routes V OUT C to J4-6. JMP13 Routes V OUT C to J4-14.
www.ti.com 4 Schematic Schematic 22 DAC8555EVM User's Guide SLAU204 – December 2006 Submit Documentation Feedback.
A B C D D C B A ti 6730 SOUTH TUCSON BLVD., TUCSON, AZ 85706 USA TITLE SHEET OF FILE SIZE DATE REV DRAW N BY ENGINEER REVISION HISTORY REV ENGINEERING CHANG E NUM BER APPROVED B DATA A CQUISITION PRODUCTS HIGH-PERFORMANCE ANALOG DIVISION SEMICONDUCTOR GROUP DOCUMENT CONTROL NO.
FCC Warning This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general customer use.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
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