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SM320F2812-HT Digital Signal Processor Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Contents 1 Features ........................................................................................................................... 11 1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS .
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 4 Peripherals ....................................................................................................................... 52 4.1 32-Bit CPU-Timers 0/1/2 ...............
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.20 SPI Slave Mode Timing ................................................................................................. 113 6.21 External Interface (XINTF) Timing ............
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 List of Figures 2-1 SM320F2812 Die Layout ........................................................................................................ 15 2-2 SM320F2812 172-Pin HFG CQFP (Top View) .
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6-23 General-Purpose Input Timing ................................................................................................ 109 6-24 SPI Master Mode External Timing (Clock Phase = 0) .
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 List of Tables 2-1 Hardware Features ............................................................................................................... 14 2-2 Bare Die Information ...
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6-16 External ADC Start-of-Conversion – EVB – Switching Characteristics ................................................. 106 6-17 Interrupt Switching Characteristics .........
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6-64 Minimum Required Wait-States at Different Frequencies .....................
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 10 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Digital Signal Processor Check for Samples: SM320F2812-HT 1 Features 12 • High-Performance Static CMOS Technology • 128 Bit Security Key/Lock – 150 MHz (6.67 ns Cycle Time) – Protects Flash/ROM/OTP and L0/L1 SARAM – Low Power (1.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com xxx 1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS • Controlled Baseline • One Assembly/Test Site • One Fabrication Site •.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 2 Introduction This section provides a summary of the device features, lists the pin assignments, and describes the function of each pin.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 2.2 Device Summary Table 2-1 provides a summary of the device features. Table 2-1. Hardware Features FEATURE F2812 Instruction Cycle (at 150 MHz) 6.67 ns Single-Access RAM (SARAM) (16 bit word) 18K 3.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 2.3 Die Layout The SM320F2812 die layout is shown in Figure 2-1 . See Table 2-3 for a description of each pad's function.
V DDAIO 1 130 172 ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7 ADCREFM ADCREFP A VSSREFBG A VDDREFBG V DDA1 V SSA1 ADCRESEXT MC XMP/ XA[0] MDRA XD[0] MDXA V DD XD[1] MCLKRA MFSXA XD.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 2.5 Signal Descriptions Table 2-3 specifies the signals on the F2812 device. All digital inputs are TTL-compatible. All outputs are 3.3 V with CMOS levels. Inputs are not 5 V tolerant.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 2-3. Signal Descriptions (1) (continued) PIN NO. DIE PAD DIE PAD DIE PAD NAME X-CENTER Y-CENTER I/O/Z (2) PU/PD (3) DESCRIPTION 172-PIN NO. ( m m) ( m m) HFG Microprocessor/Microcomputer Mode Select.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 2-3. Signal Descriptions (1) (continued) PIN NO. DIE PAD DIE PAD DIE PAD NAME X-CENTER Y-CENTER I/O/Z (2) PU/PD (3) DESCRIPTION 172-PIN NO. ( m m) ( m m) HFG JTAG AND MISCELLANEOUS SIGNALS Oscillator Input – input to the internal oscillator.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 2-3. Signal Descriptions (1) (continued) PIN NO. DIE PAD DIE PAD DIE PAD NAME X-CENTER Y-CENTER I/O/Z (2) PU/PD (3) DESCRIPTION 172-PIN NO. ( m m) ( m m) HFG JTAG test reset with internal pulldown.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 2-3. Signal Descriptions (1) (continued) PIN NO. DIE PAD DIE PAD DIE PAD NAME X-CENTER Y-CENTER I/O/Z (2) PU/PD (3) DESCRIPTION 172-PIN NO. ( m m) ( m m) HFG ADC ANALOG INPUT SIGNALS ADCINA7 163 186 42.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 2-3. Signal Descriptions (1) (continued) PIN NO. DIE PAD DIE PAD DIE PAD NAME X-CENTER Y-CENTER I/O/Z (2) PU/PD (3) DESCRIPTION 172-PIN NO. ( m m) ( m m) HFG POWER SIGNALS V DD 22 29 2927.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Signal Descriptions (Continued) (1) PIN NO. PERIPHERAL DIE PAD DIE PAD GPIO DIE PAD NO. I/O/Z (2) PU/PD (3) DESCRIPTION 172-PIN SIGNAL X-CENTER Y-CENTER HFG GPIO OR PERIPHERAL SIGNALS GPIOA OR EVA SIGNALS GPIO or PWM GPIOA0 PWM1 (O) 90 104 4908.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Signal Descriptions (Continued) (1) (continued) PIN NO. PERIPHERAL DIE PAD DIE PAD GPIO DIE PAD NO. I/O/Z (2) PU/PD (3) DESCRIPTION 172-PIN SIGNAL X-CENTER Y-CENTER HFG GPIO or Capture GPIOB8 CAP4_QEP3 (I) 56 64 5361.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Signal Descriptions (Continued) (1) (continued) PIN NO. PERIPHERAL DIE PAD DIE PAD GPIO DIE PAD NO. I/O/Z (2) PU/PD (3) DESCRIPTION 172-PIN SIGNAL X-CENTER Y-CENTER HFG GPIOF OR CAN SIGNALS GPIO or eCAN GPIOF6 CANTXA (O) 85 99 5361.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Signal Descriptions (Continued) (1) (continued) PIN NO. PERIPHERAL DIE PAD DIE PAD GPIO DIE PAD NO. I/O/Z (2) PU/PD (3) DESCRIPTION 172-PIN SIGNAL X-CENTER Y-CENTER HFG GPIOG OR SCI-B SIGNALS GPIO or SCI GPIOG4 SCITXDB (O) 88 102 5098.
M0 SARAM 1K x 16 CPU-T imer 0 CPU-T imer 1 INT[12:1] CLKIN Real-T ime JT A G CPU-T imer 2 Peripheral Bus C28x CPU H0 SARAM 8K ⋅ 16 INT14 NMI INT13 Memory Bus M1 SARAM 1K x 16 Flash 128K x 16 Boot RO.
Block Start Address Low 64K (24x/240x Equivalent Data Space) 0x00 0000 M0 V ector − RAM (32 × 32) (Enabled if VMAP = 0) Data Space Prog Space M0 SARAM (1K × 16) M1 SARAM (1K × 16) Peripheral Fram.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 3-1. Addresses of Flash Sectors in F2812 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3D 8000 Sector J, 8K × 16 0x3D 9FFF 0x3D A.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 3.2 Brief Descriptions 3.2.1 C28x CPU The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is source code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant software investment.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com single step through non-time critical code while enabling time-critical interrupts to be serviced without interference. The F2812 implements the real-time mode in hardware within the CPU.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 3-3. Boot Mode Selection GPIOF4 GPIOF12 GPIOF3 GPIOF2 BOOT MODE SELECTED (1) (SCITXDA) (MDXA) (SPISTEA) (SPICLK) (2) GPIO P.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 HALT: Turn off oscillator. This mode basically shuts down the device and places it in the lowest possible power consumption mode. Only a reset or XNMI wakes the device from this mode.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 3.2.20 Serial Port Peripherals The F2812 supports the following serial communication peripherals: eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping of messages, and is CAN 2.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 3-4. Peripheral Frame 0 Registers (1) NAME ADDRESS RANGE SIZE (×16) ACCESS TYPE (2) 0x00 0880 Device Emulation Registers 3.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 3-6. Peripheral Frame 2 Registers (1) NAME ADDRESS RANGE SIZE (×16) ACCESS TYPE 0x00 7000 reserved 16 0x00 700F 0x00 7010 .
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 3.4 Device Emulation Registers These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 3-7 .
XD(15:0) XA(18:0) XZCS6 XZCS7 XZCS6AND7 XZCS2 XWE XR/W XREADY XMP/MC XHOLD XHOLDA XCLKOUT XRD XINTF Zone 0 (8K × 16) XINTF Zone 1 (8K × 16) XINTF Zone 6 (512K × 16) XINTF Zone 7 (16K × 16) (mapped.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 The operation and timing of the external interface, can be controlled by the registers listed in Table 3-8 .
C28x CPU PIE TIMER 2 (for RT OS) TIMER 0 W atchdog Peripherals (SPI, SCI, McBSP , CAN, EV , ADC) (41 Interrupts) 96 Interrupts † TINT0 Interrupt Control XNMICR(15:0) XINT1 Interrupt Control XINT1CR(.
INT12 MUX INT1 1 INT2 INT1 CPU (Enable) (Flag) INTx INTx.8 PIEIERx(8:1) PIEIFRx(8:1) MUX INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 From Peripherals or External Interrupts (Enable) (Flag) IER(12:1) IFR(12:1) Global Enable INTM 1 0 PIEACKx (Enable/Flag) SM320F2812-HT www.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 3-11. PIE Configuration and Control Registers (1) NAME ADDRESS SIZE (×16) DESCRIPTION PIECTRL 0x0000-0CE0 1 PIE, Control R.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 3.6.1 External Interrupts Table 3-12. External Interrupts Registers NAME ADDRESS SIZE (×16) DESCRIPTION XINT1CR 0x00 7070 1 XINT.
SeeNote A SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 3.7 System Control This section describes the F2812 oscillator, PLL and clocking mechanisms, the watchdog function and the low power modes. Figure 3-6 shows the various clock and reset domains in the F2812 device that are discussed.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 The PLL, clocking, watchdog, and low-power modes are controlled by the registers listed in Table 3-13 .
X2 X1/XCLKIN On-Chip Oscillator (OSC) PLL Bypass /2 XF_XPLLDIS OSCCLK (PLL Disabled) Latch XPLLDIS XRS PLL 4-Bit PLL Select SYSCLKOUT 1 0 CLKIN CPU 4-Bit PLL Select XCLKIN PLL Block SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 3.
External Clock Signal (T oggling 0 −V D D ) C b1 (see Note A) X2 X1/XCLKIN X1/XCLKIN X2 Crystal C b2 (see Note A) (a) (b) NC SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 3.
/512 OSCCLK WDCR (WDPS(2:0)) WDCLK WDCNTR(7:0) WDKEY(7:0) Bad Key Good Key 101 WDCR (WDCHK(2:0)) Bad WDCHK Key WDCR (WDDIS) Clear Counter SCSR (WDENINT) W atchdog Prescaler Generate Output Pulse (512 .
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 3.12 Low-Power Modes Block The low-power modes on the F2812 are similar to the 240x devices.
Borrow Reset T imer Reload SYSCLKOUT TCR.4 (T imer Start Status) TINT 16-Bit T imer Divide-Down TDDRH:TDDR 32-Bit T imer Period PRDH:PRD 32-Bit Counter TIMH:TIM 16-Bit Prescale Counter PSCH:PSC Borrow SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.
INT1 to INT12 INT14 C28x TINT2 TINT0 PIE CPU-TIMER 0 CPU-TIMER 2 (Reserved for TI system functions) INT13 TINT1 CPU-TIMER 1 (Reserved for TI system functions) XINT13 SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 In the F2812 device, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4-2 .
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers NAME ADDRESS SIZE (×16) DESCRIPTION TIMER0TIM 0x00 0C00 1 CPU-.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 4.2 Event Manager Modules (EVA, EVB) The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 4-3. EVA Registers (1) NAME ADDRESS SIZE (×16) DESCRIPTION GPTCONA 0x00 7400 1 GP Timer Control Register A T1CNT 0x00 7401.
GPTCONA(12:4), CAPCONA(8), EXTCONA[0] EV A T O ADC (Internal) T imer 1 Compare Output Logic T1PWM_T1CMP GPTCONA(1,0) T1CON(1) GP T imer 1 TCLKINA Prescaler HSPCLK T1CON(10:8) T1CON(5,4) clock Full Com.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 4.2.1 General-Purpose (GP) Timers There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes: • .
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 4.2.6 PWM Characteristics Characteristics of the PWMs are as follows: • 16-bit registers • Wide range of programmable deadban.
Input Ana log Voltag e ADCLO 4096 , 3 - ´ SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 4.3 Enhanced Analog-to-Digital Converter (ADC) Module A simplified functional block diagram of the ADC module is shown in Figure 4-4. The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S / H) circuit.
Result Registers EVB S/W ADCSOC EV A S/W Sequencer 2 Sequencer 1 SOC SOC ADC Control Registers 70B7h 70B0h 70AFh 70A8h Result Reg 15 Result Reg 8 Result Reg 7 Result Reg 1 Result Reg 0 Module ADC 12-Bit Analog MUX ADCINA0 ADCINA7 ADCINB0 ADCINB7 System Control Block High-Speed Prescaler HSPCLK ADCENCLK C28x SYSCLKOUT S/H S/H SM320F2812-HT www.
ADCINA[7:0] ADCINB[7:0] ADCLO ADCBGREFIN † ADC External Current Bias Resistor ADCRESEXT ADCREFP V DD A1 V DD A2 V SSA1 V SSA2 A VDDREFBG A VSSREFBG V DD AIO V SSAIO V DD 1 V SS1 T est Pin ADC Refere.
ADCINA[7:0] ADCINB[7:0] ADCLO ADCBGREFIN ADC External Current Bias Resistor ADCRESEXT ADCREFP V DD A1 V DD A2 V SSA1 V SSA2 A VDDREFBG A VSSREFBG V DD AIO V SSAIO V DD 1 V SS1 T est Pin ADC Reference .
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-4 .
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 4.4 Enhanced Controller Area Network (eCAN) Module The CAN module has the following features: • Fully compliant with CAN protocol, version 2.
Mailbox RAM (512 Bytes) 32-Message Mailbox of 4 × 32-Bit W ords Memory Management Unit CPU Interface, Receive Control Unit, T imer Management Unit eCAN Memory (512 Bytes) Registers and Message Object.
Mailbox Enable − CANME Mailbox Direction − CANMD T ransmission Request Set − CANTRS T ransmission Request Reset − CANTRR T ransmission Acknowledge − CANT A Abort Acknowledge − CANAA Receiv.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com The CAN registers listed in Table 4-6 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations.
CLKSRG McBSP clock rat e CLKG , 1 CLKGDIV = = + SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 4.5 Multichannel Buffered Serial Port (McBSP) Module The McBSP module has the fol.
McBSP Receive Interrupt Select Logic DX DR Expand Logic DRR1 Receive Buffer RX FIFO Interrupt DRR2 Receive Buffer RX FIFO Registers RBR1 Register RBR2 Register McBSP Registers and Control Logic CLKX F.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 4-7 provides a summary of the McBSP registers. Table 4-7. McBSP Register Summary ADDRESS TYPE RESET VALUE NAME DESCRIPTION .
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 4-7. McBSP Register Summary (continued) ADDRESS TYPE RESET VALUE NAME DESCRIPTION 0x00 78xxh (R/W) (HEX) FIFO MODE REGISTER.
LSPCLK , (BRR 1 ) 8 + · LSPCLK , 16 6 150 MHz Max b it rate 9.375 10 b / s 2 8 = = ´ ´ SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 4.6 Serial Communications Interface (SCI) Module The F2812 device include two serial communications interface (SCI) modules.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com NOTE All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros.
TX FIFO _0 LSPCLK WUT Frame Format and Mode Even/Odd Enable Parity SCI RX Interrupt select logic BRKDT RXRDY SCIRXST .6 SCICTL1.3 8 SCICTL2.1 RX/BK INT ENA SCIRXD SCIRXST .1 TXENA SCI TX Interrupt select logic TX EMPTY TXRDY SCICTL2.0 TX INT ENA SCITXD RXENA SCIRXD RXW AKE SCICTL1.
LSPCLK , (SPIBRR 1 ) + L S P C L K , 4 SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 4.7 Serial Peripheral Interface (SPI) Module The F2812 device includes the four-pin serial peripheral interface (SPI) module.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Enhanced feature: • 16-level transmit/receive FIFO • Delayed transmit control The SPI port operation is configured and controlled by the registers listed in Table 4-10 . Table 4-10.
S SPICTL.0 SPI INT FLAG SPI INT E N A SPISTS.6 S Clock Polarity T alk LSPCLK 4 5 6 1 2 3 0 0 1 2 3 SPI Bit Rate State Control SPIRXBUF Buffer Register Clock Phase Receiver Overrun Flag SPICTL.4 Overrun INT ENA SPICCR.3 − 0 SPIBRR.6 − 0 SPICCR.6 SPICTL.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 4.8 GPIO MUX The GPIO Mux registers are used to select the operation of shared pins on the F2812 device. The pins can be individually selected to operate as Digital I/O or connected to Peripheral I/O signals (via the GPxMUX registers).
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 4-12. GPIO Data Registers (1) (2) NAME ADDRESS SIZE (×16) REGISTER DESCRIPTION GPADAT 0x00 70E0 1 GPIO A Data Register GPA.
Peripheral I/O MUX 0 1 MUX 1 0 PIN Internal (Pullup or Pulldown) Digital I/O XRS High-Impedance Enable (1) High- Impedance Control GPxDIR Register Bit GPxMUX Register Bit GPxQUAL Register GPxDA T/SET/CLEAR/T OGGLE Register Bit(s) Input Qualification SYSCLKOUT SM320F2812-HT www.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 5 Development Support Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSPs, in.
PREFIX SM 320 F 2812 HFG TMX = experimental de vice TMP = prototype dev ice TMS = qualified de vice SM = commercial processing SMJ = M IL-PRF-38535 (QML) DEVICE F AMIL Y 320 = TMS320 DSP Family TECHNOLOGY PACKAGETYPE † HFG = 172-pin CQFP KGD = Die DEVICE 2810 TEMPERA TURE RANGE M S = -55°C to 220°C F = Flash EEPROM (1.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com TMS320x281x, 280x Enhanced Controller Area Network (eCAN) Reference Guide (literature number SPRU074) describes the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Updated information on the TMS320™ DSP controllers can be found on the worldwide web at: http://www.ti.com . To send comments regarding this TMS320F281x/TMS320C281x data manual (literature number SPRS174), use the commentsatbooks.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.2 Recommended Operating Conditions See (1) MIN NOM MAX UNIT V DDIO Device supply voltage, I/O 3.14 3.3 3.47 V 1.8 V (135 MHz) 1.71 1.8 1.89 V DD , V DD1 Device supply voltage, CPU V 1.
1.00E+06 1.00E+05 1.00E+04 1.00E+03 1.00E+02 70 150 200 220 Die Junction T emperature (°C) Hours SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Figure 6-1. SM320F2812-HT Life Expectancy Curve Notes: 1. See data sheet for absolute maximum and minimum recommended operating conditions.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.4 Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During Low-Power Modes at 150-MHz SYSCLKOUT T .
0 50 100 150 200 250 0 20 40 60 80 100 120 140 160 SYSCLKOUT (MHz) IDD IDDIO IDD3VFL IDDA T otal 3.3−V current Current (mA) 0 100 200 300 400 500 600 700 0 20 40 60 80 100 120 140 160 SYSCLKOUT (MHz) TOT AL POWER Power (mW) SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.6 Reducing Current Consumption 28x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current consumption can be achieved by turning off the clock to any peripheral module which is not used in a given application.
SeeFigure6-8, SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-2. Recommended Low-Dropout Regulators SUPPLIER PART NUMBER Texas Instruments TPS767D301 NOTE The GPIO pins are undefined until V DD = 1 V and V DDIO = 2.
0.4 V (V OL ) 20% 2.4 V (V OH ) 80% 0.8 V (V IL ) 10% 2.0 V (V IH ) 90% SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Figure 6-5.
T ransmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (see note) T ester Pin Electronics Data Sheet T iming Reference Point Output Under T est NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line ef fects must be taken into account.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.12 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock options available on the F2812 DSP. Table 6-3 lists the cycle times of various clocks.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-5. XCLKIN Timing Requirements – PLL Bypassed or Enabled (1) NO. MIN MAX UNIT C8 t c(CI) Cycle time, XCLKIN 6.
SeeNote A SeeNoteB SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 6-8 is intended to illustrate the timing parameters only and may differ based on configuration.
t w(RSL 1) t h(XPL LD IS) t h(XM P/MC) t h(b oot-m ode) (See Note D) V DD IO , V DD3VF L V DD An , V DDA IO (3.3 V) (See Note B) XCLKIN 2.5 V 0.3 V X1 XRS XF/XPLLDIS XMP/MC Boot-Mode Pins V DD , V DD 1 (1.
t w(RSL ) t h(XPL LD IS) t h(XM P/MC) t OSCST V DD IO , V DD3VF L V DD An , V DDA IO (3.3 V) XCLKIN X1 XRS XF/XPLLDIS XMP/MC V DD , V DD 1 (1.8 V (or 1.
XCLKIN/8 (XCLKIN * 5) t h(XPL LD IS) t h(XM P/MC) t h(b oot-m ode) (see Note A) t w(RSL 2) XCLKIN X1 XRS XF/XPLLDIS XMP/MC Boot-Mode Pins XCLKOUT I/O Pins Address/Data/ Control Boot-ROM Execution Star.
W AKE INT (see Note B) XCLKOUT (see Note A) A0−A15 t d(W A KE− IDLE) t w(W AK E− INT) SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.15 Low-Power Mode Wakeup Timing Table 6-10 is also the IDLE Mode Wake-Up Timing Requirements table.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-11 is also the STANDBY Mode Wake-Up Timing Requirements table. Table 6-11.
t w(W AK E-INT) t d(W A KE-ST BY) t d(IDL E−XC OH) 32 SYSCLKOUT Cycles W ake−up Signal X1/XCLKIN XCLKOUT † ST ANDBY Normal Execution ST ANDBY Flushing Pipeline A B C D E F Device Status NOTES: A. IDLE instruction is executed to put the device into ST ANDBY mode.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-12. HALT Mode Switching Characteristics (1) PARAMETER MIN TYP MAX UNIT Delay time, IDLE instruction executed to XCLKOUT t.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com A. IDLE instruction is executed to put the device into HALT mode. B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the CLKIN to the core is stopped.
t w(PWM ) t d(PW M)XC O PWMx XCLKOUT (see Note A) XCLKOUT (see Note A) t w(TD IR) TDIRx SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-13.
XCLKOUT t d(XC OH-EV ASOCL ) EV ASOC t w(EV A SOCL ) XCLKOUT t d(XC OH-EVB SOCL ) EVBSOC t w(EVBSOC L) SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.
PWM (see Note C) TxCTRIP , CxTRIP , PDPINTx (see Note B) XCLKOUT (see Note A) t w(PDP) , t w(C xTR IP) , t w(TxCT RIP) t d(PD P-PWM )HZ , t d(TR IP-PWM)H Z XNMI, XINT1, XINT2 t w(INT) Interrupt V ector t d(INT ) A0−A15 SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-18.
t d(XC OH-GPO) GPIO XCLKOUT t r(GPO) t f(GPO) GPIO Signal 1 Sampling Window QUALPRD Output From Qualifier 1 1 111111111 0000000 000 SYSCLKOUT QUALPRD = 1 (2 x SYSCLKOUT cycles) x 5 NOTES: A. This glitch is ignored by the input qualifier . The QUALPRD bit field specifies the qualification sampling period.
t c(SPC) + SPI clock cycle time + LSPCL K 4 or L SPCLK (SPIB RR ) 1) + t c(LCO) + L SPCLK cycle tim e GPIOxn XCLKOUT t w(GPI) (2) SM320F2812-HT www.ti.
9 4 SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be V alid Master Out Data Is V alid 8 5 3 2 1 SPISTE (see Note A) SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.
t c(SPC) + SPI clock cycle time + LSPCL K 4 or L SPCLK (SPIB RR ) 1) + t c(LCO) + L SPCLK cycle tim e (2) SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-22. SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) SPI WHEN (SPIBRR + 1) SPI WHEN (SPIBRR + 1) IS EVEN OR IS ODD AND NO.
Data V alid 1 1 SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be V alid Master Out Data Is V alid 1 7 6 10 3 2 SPISTE (see Note A) SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com A. In the master mode, SPISTE goes active 0.
t c(SPC) + SPI clock cycle time + LSPCL K 4 or L SPCLK (SPIB RR ) 1) + t c(LCO) + L SPCLK cycle tim e 20 15 SPISIMO SPISOMI SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO Data Must Be V alid SPISOMI Data Is V alid 19 16 14 13 12 SPISTE (see Note A) (2) SM320F2812-HT www.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 114 Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Fold.
t c(SPC) + SPI clock cycle time + LSPCL K 4 or L SPCLK (SPIB RR ) 1) + t c(LCO) + L SPCLK cycle tim e Data V alid 22 SPISIMO SPISOMI SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO Data Must Be V alid SPISOMI Data Is V alid 21 12 18 17 14 13 SPISTE (see Note A) (2) SM320F2812-HT www.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 116 Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Fold.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.21 External Interface (XINTF) Timing Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail wait states in the XTIMING registers.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com NOTE Restriction does not include external hardware wait states These requirements result in the following XTIMING register configuration restrictions: Table 6-28.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 or Table 6-31. XTIMING Register Configuration Restrictions (1) (2) XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING ≥ 2 ≥ 1 0 ≥ 2 ≥ 1 0 0, 1 (1) Not production tested.
XTIMING0 XTIMING1 XTIMING2 XTIMING6 XTIMING7 XBANK LEAD/ACTIVE/TRAIL 1 † 0 XCLKOUT /2 XTIMCLK 1 † 0 /2 C28x CPU XINTCNF2 (CLKMODE) XINTCNF2 (XTIMCLK) † Default V alue after reset SYSCLKOUT XINTCNF2 (CLKOFF) 1 0 0 SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.22 XINTF Signal Alignment to XCLKOUT For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock XTIMCLK. Strobes such as XRD, XWE, and zone chip-select (XZCS) change state in relationship to the rising edge of XTIMCLK.
Lead Active T rail DIN t d(XC OHL -XRDL ) t d(XC OH-XA ) t d(XC OH-XZ CSL) t d(XC OHL -XRDH ) t h(XD )XRD t d(XC OHL -XZCSH ) XCLKOUT=XTIMCLK XCLKOUT= 1/2 XTIMCLK XZCS0AND1 , XZCS2 , XZCS6AND7 XA[0:18] XRD XWE XR/W XD[0:15] NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT .
Lead Active T rail t d(XC OH-XZ CSL) t d(XC OH-XA ) t d(XC OHL -XWEL) t d(XCOH L-XW EH) t d(XC OHL -XZCSH ) t en(XD )XWEL t h (XD)XW EH t dis(XD)XR NW XCLKOUT=XTIMCLK XCLKOUT= 1/2 XTIMCLK XZCS0AND1 , XZCS2 , XZCS6AND7 XA[0:18] XRD XWE XR/W XD[0:15] NOTES: A.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com XTIMING register parameters used for this example: XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYM.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.25 External Interface Ready-on-Read Timing With One External Wait State Table 6-37.
Lead Active T rail DIN t d(XC OH-XZ CSL) t d(XC OH-XA ) t d(XC OHL -XRDL ) t d(XC OHL -XZCSH ) t d(XC OHL -XRDH ) WS (Synch) XCLKOUT=XTIMCLK XCLKOUT= 1/2 XTIMCLK XZCS0AND1 , XZCS2 , XZCS6AND7 XA[0:18] XRD XWE XR/W XD[0:15] XREADY(Synch) NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT .
t su(XD )XRD Lead Active T rail DIN t d(XC OH-XZ CSL) t d(XC OH-XA ) t d(XC OHL -XRDL ) t d(XC OHL -XZCSH ) t d(XC OHL -XRDH ) WS (Asynch) XCLKOUT=XTIMCLK XCLKOUT= 1/2 XTIMCLK XZCS0AND1 , XZCS2 , XZCS6AND7 XA[0:18] XRD XWE XR/W XD[0:15] XREADY(Asynch) NOTES: A.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.26 External Interface Ready-on-Write Timing With One External Wait State Table 6-41.
Lead 1 Active T rail XCLKOUT = XTIMCLK XCLKOUT = 1/2 XTIMCLK XA[0:18] XD[0:15] XREADY(Synch) t d(XCO HL-XWE L) t d(XCO HL-XW EH) t d(XCO HL-XZCSH) t d(XCO H-XA) WS (Synch) XZCS0AND1 , XZCS2 , XZCS6AND7 XRD XWE XR/W t d(XCO H-XZCSL) NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT .
Lead 1 Active T rail XCLKOUT = XTIMCLK XCLKOUT = 1/2 XTIMCLK XA[0:18] XD[0:15] t d(XCO HL-XWE H) t d(XCO HL-XZCSH) t d(XCO H-XA) WS (Asynch) XZCS0AND1 , XZCS2 , XZCS6AND7 XRD XWE XR/W t d(XCO H-XZCSL) NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT .
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.27 XHOLD and XHOLDA f the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of high-impedance mode.
XCLKOUT (/1 Mode) XHOLD XR/W , XZCS0AND1 , XZCS2 , XZCS6AND7 XD[15:0] V alid XHOLDA t d(H L-Hiz) t d(H H-HA H) High-Impedance XA[18:0] V alid V alid High-Impedance t d(H H-BV ) t d(H L-HA L) See Note A See Note B SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.
SeeNote A SeeNoteB SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-45. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) (1) (2) (3) (4) MIN MAX UNIT t d.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.29 On-Chip Analog-to-Digital Converter 6.29.1 ADC Absolute Maximum Ratings VALUE (1) UNIT V SSA1 /V SSA2 to V DDA1 /V DDA2 /AV DDREFBG –0.3 to 4.6 V Supply voltage range V SS1 to V DD1 – 0.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions Table 6-46. DC Specifications (1) (2) T A = –55°C to 220°C PARAMETER UNIT MIN TYP MAX Resolution 12 Bits ADC clock (3) 1 kHz 25 MHz ACCURACY INL (Integral nonlinearity) (4) 1–18.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 6-47. AC Specifications (1) (2) T A = –55°C to 125°C T A = 220°C PARAMETER UNIT MIN TYP MAX MIN TYP MAX SINAD Signal-t.
ac R s ADCIN0 C p 10 pF R on 1 k Ω 1.25 pF C h Switch T ypical V alues of the Input Circuit Components: Switch Resistance (R on ): 1 k Ω Sampling Capacitor (C h ): 1.
Analog Input on Channel Ax or Bx ADC Clock Sample and Hold SH Pulse SMODE Bit t dsch x_n t dsch x_n+1 Sample n Sample n+1 Sample n+2 t SH ADC Event T rigger from EV or Other Sources t d(SH ) SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-50. Sequential Sampling Mode Timing (1) AT 25–MHz ADC SAMPLE n SAMPLE n + 1 CLOCK, REMARKS t c(ADCCLK) = 40 ns Delay time from event trigger to t d(SH) 2.
Analog Input on Channel Ax Analog Input on Channel Bv ADC Clock Sample and Hold SH Pulse t SH t dsch A0_n t dsch B0_n t dsch B0_n +1 Sample n Sample n+1 Sample n+2 t dsch A0_n +1 t d(SH ) ADC Event T rigger from EV or Other Sources SMODE Bit SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.
(SINAD 1. 76) N 6.02 - = SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-51. Simultaneous Sampling Mode Timing (1) (continued) AT 25-MHz ADC SAMPLE n SAMPLE n + 1 CLOCK, REMARKS t c(ADCCLK) = 40 ns Delay time for successive (3 + Acqps) × t d(schB0_n+1) results to appear in Result 120 ns t c(ADCCLK) register 6.
CLKG + CL KSRG (1 ) CLKGDV ) (2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.30 Multichannel Buffered Serial Port (McBSP) Timing 6.30.1 McBSP Transmit and Receive Timing Table 6-52.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-53. McBSP Switching Characteristics (1) (2) (3) NO. PARAMETER MIN MAX UNIT M1 t c(CKRX) Cycle time, CLKR/X CLKR/X int 2P .
(n−2) Bit (n−1) (n−3) (n−2) Bit (n−1) (n−4) (n−3) (n−2) Bit (n−1) M18 M17 M18 M17 M17 M18 M16 M15 M4 M4 M14 M13 M3, M12 M1, M1 1 M2, M12 (RDA TDL Y= 10b) DR (RDA TDL Y= 01b) DR (RDA .
Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX M30 M31 DR M28 M24 M29 M25 LSB MSB M32 M33 SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.30.2 McBSP as SPI Master or Slave Timing Table 6-54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1) MASTER SLAVE NO.
Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX DR M35 M37 M40 M39 M38 M34 LSB MSB M41 M42 SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 6-56. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1) MASTER SLAVE NO.
M51 M50 M47 Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX DR M44 M48 M49 M43 LSB MSB M52 SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-58. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1) MASTER SLAVE NO.
Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX DR M54 M58 M56 M53 M55 M59 M57 LSB MSB M60 M61 SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 6-60. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1) MASTER SLAVE NO.
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.31 Flash Timing 6.31.1 Recommended Operating Conditions (4) MIN NOM MAX UNIT N f Flash endurance for the array (Write/erase cyc.
SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 6-64. Minimum Required Wait-States at Different Frequencies (1) (continued) SYSCLKOUT (MHz) SYSCLKOUT (ns) PAGE WAIT-STATE .
SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 7 Mechanical Data The following mechanical package diagram(s) reflect the most current released mechanical data available for the designated device(s).
PACKAGE OPTION ADDENDUM www.ti.com 28-May-2010 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak T.
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