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TMS320C6457 DSP Host Port Interface (HPI) User's Guide Literature Number: SPRUGK7A March 2009 – Revised July 2010.
2 SPRUGK7A – March 2009 – Revised July 2010 Copyright © 2009–2010, Texas Instruments Incorporated.
Preface ....................................................................................................................................... 6 1 Introduction to the HPI ...............................................................................
www.ti.com List of Figures 1 HPI Position in the Host-DSP System ................................................................................... 7 2 Example of Host-DSP Signal Connections When Using the HAS Signal in the 32-Bit Multiplexed Mode ..
www.ti.com List of Tables 1 Summary of HPI Registers ................................................................................................ 9 2 HPI Signals .....................................................................................
Preface SPRUGK7A – March 2009 – Revised July 2010 Read This First About This Manual This guide describes the host port interface (HPI) on the TMS320C6457 digital signal processors (DSPs).
HPID R/W FIFOs HPIA Increment HPIC Access type HD[31:0]/HD[15:0] HDS1 , HDS2 HR/W HAS HCNTL0 HCNTL1 (optional) HINT HRDY HPI Host Data Address ALE R/W IRQ Ready HCS Chip select DSP HPI DMA logic HHWIL.
Introduction to the HPI www.ti.com The HPI uses multiplexed operation, meaning the data bus carries both address and data. When the host drives an address on the bus, the address is stored in the address register (HPIA) in the HPI, so that the bus can then be used for data.
www.ti.com Introduction to the HPI Table 1. Summary of HPI Registers Host Access CPU Access Read/Write Access Requirements Read/Write Offset Register Description Permissions Permissions Address PWREMU.
Introduction to the HPI www.ti.com Table 2. HPI Signals (continued) Signal State (1) Host Connection Description HCNTL[1:0] I Address or control pins The HPI latches the logic levels of these pins on the falling edge of HAS or internal HSTRB (for details about internal HSTRB, see Section 3.
www.ti.com Using the Address Registers 2 Using the Address Registers The HPI contains two 32-bit address registers: one for read operations (HPIAR) and one for write operations (HPIAW). These roles are unchanging from the position of the HPI DMA logic.
Address or I/O Read/W rite Chip select Data strobe A Data/address Interrupt Ready HCNTL[1:0] HR/W HCS HDS1 HDS2 HD[31:0] HINT HRDY HPI Host Address latch enable HAS No connect HHWIL Logic high 2 32 DSP HPI Operation www.
Address or I/O Read/W rite Chip select Data strobe A Data/address Interrupt Ready HCNTL[1:0] HR/W HCS HDS1 HDS2 HD[31:0] HINT HRDY HPI Host Logic high HAS No connect HHWIL Logic high 2 32 DSP Read/W r.
Read/W rite Chip select Data strobe A Data Interrupt Ready HCNTL[1:0] HR/W HCS HDS1 HDS2 HD[15:0] HINT HRDY HPI DSP Host HAS HHWIL Logic high Logic high Address or I/O HD[31:16] No connect 2 16 16 HPI Operation www.
HDS1 HDS2 HCS HRDY Internal HSTRB Internal HRDY www.ti.com HPI Operation If the host wants to read data from the DSP internal/external memory, the HPI DMA logic reads the memory address from HPIAR and retrieves the data from the addressed memory location.
HPI Operation www.ti.com 3.4 HCNTL[1:0] and HR/W: Indicating the Cycle Type The cycle type consists of: • The access type selected by the host by driving the appropriate levels on the HCNTL[1:0] pins of the HPI. Table 4 describes the four available access types.
www.ti.com HPI Operation 3.5 HHWIL: Identifying the First and Second Halfwords in 16-Bit Multiplexed Mode In the 16-bit multiplexed mode, each host cycle consists of two consecutive halfword transfers.
Data 2 Data 1 HCS HAS HSTRB HR/W HCNTL[1:0] HD[15:0] HRDY A HHWIL Internal HPI latches control information Host latches data HPI latches control information Host latches data HPI Operation www.
HCS HAS HSTRB HR/W HCNTL[1:0] HRDY A HHWIL Data 1 Data 2 HD[15:0] Internal HPI latches control information HPI latches data HPI latches control information HPI latches data www.
Data 2 Data 1 HCS HSTRB HR/W HCNTL[1:0] HD[15:0] HRDY A HHWIL Internal HPI latches control information Host latches data HPI latches control information Host latches data HPI Operation www.
HCS HSTRB HRDY A HR/W HCNTL[1:0] HHWIL Data 1 Data 2 HD[15:0] Internal HPI latches control information HPI latches data HPI latches control information HPI latches data www.
Data 1 HCS HSTRB HR/W HCNTL[1:0] HD[15:0] HRDY HHWIL Internal V alid 00 V alid HPI Operation www.ti.com 3.8 Single-Halfword HPIC Cycle in the 16-Bit Multiplexed Mode In 16-bit multiplexed mode, the lower 16 bits of the HPIC registers are duplicated on the upper 16 bits during HPIC host accesses.
1st halfword 00 or 10 00 or 10 2nd halfword Internal HD[15:0] HRDY HHWIL HR/W HCNTL[1:0] HCS HSTRB HCS HCNTL[1:0] HR/W HHWIL Internal HSTRB HD[15:0] HRDY 1st halfword 2nd halfword 1st halfword 2nd hal.
1st halfword 2nd halfword 00 00 Internal HD[15:0] HRDY HHWIL HR/W HCNTL[1:0] HCS HSTRB 10 10 1 1 11 1st halfword 2nd halfword 2nd halfword 1st halfword Internal HSTRB HD[15:0] HRDY HHWIL HR/W HCNTL[1:.
10 10 01 01 01 1st halfword 2nd halfword 1st halfword 2nd halfword 1st halfword Internal HSTRB HD[15:0] HRDY HHWIL HR/W HCNTL[1:0] HCS HPIA write HPID+ writes 00 or 10 HCNTL[1:0] HD[31:0] HRDY HR/W Internal HSTRB HCS www.ti.com HPI Operation Figure 18.
1 1 10 HPIA W rite HPID Read HCNTL[1:0] HD[31:0] HRDY HR/W Internal HSTRB HCS 10 01 01 01 HPIA W rite HPID+ Reads HD[31:0] HRDY HCS A HCNTL[1:0] HR/W Internal HSTRB HPI Operation www.
00 HCNTL[1:0] HD[31:0] HRDY HR/W Internal HSTRB HCS 10 1 1 HPIA W rite HPID W rite HRDY HR/W Internal HSTRB HCS HCNTL[1:0] HD[31:0] www.ti.com HPI Operation Figure 22.
10 01 01 01 HPIA W rite HPID+ W rites HCNTL[1:0] HD[31:0] HRDY HR/W Internal HSTRB HCS A 10 01 01 01 HPIA W rite HPID+ W rites HD[31:0] HRDY Internal HSTRB HCS A HCNTL[1:0] HR/W HPI Operation www.
www.ti.com Software Handshaking Using the HPI Ready (HRDY) Bit 4 Software Handshaking Using the HPI Ready (HRDY) Bit In addition to the HRDY output signal, the HPI contains an HRDY bit in the control register (HPIC). This bit is useful for software polling when the host does not have an input pin to connect to the HRDY pin.
DSPINT=0 DSPINT=1 CPU writes 1 to DSPINT bit Interrupt pending Host writes 0 to DSPINT bit No interrupt/ interrupt cleared Host writes 0 or 1 to DSPINT bit CPU writes 0 to DSPINT bit CPU writes 0 or 1 to DSPINT bit Host writes 1 to DSPINT bit (interrupt generated to CPU) (A) Interrupts Between the Host and the CPU www.
HINT bit=0 HINT signal is high is low HINT signal HINT bit=1 CPU writes 1 to HINT bit Host writes 1 to HINT bit Interrupt active CPU writes 0 to HINT bit No interrupt/ interrupt cleared Host writes 0 or 1 to HINT bit CPU writes 0 or 1 to HINT bit Host writes 0 to HINT bit www.
W rite FIFO control logic Host write pointer HPI DMA read pointer W rite FIFO Host writes Read FIFO reads Host control logic Read FIFO Host read pointer HPI DMA write pointer HPI DMA logic Switched central Burst writes reads Burst resource DSP internal/ external memory FIFOs and Bursting www.
www.ti.com FIFOs and Bursting If the host initiates an HPID read cycle with autoincrementing, the HPI DMA logic performs two 4-word burst operations to fill the read FIFO. The host is initially held off by the deassertion of the HRDY signal until data is available to be read from the read FIFO.
FIFOs and Bursting www.ti.com 6.3 FIFO Flush Conditions When specific conditions occur within the HPI, the read or write FIFO must be flushed to prevent the reading of stale data from the FIFOs. When a read FIFO flush condition occurs, all current host accesses and direct memory accesses (DMAs) to the read FIFO are allowed to complete.
www.ti.com Emulation and Reset Considerations 7 Emulation and Reset Considerations 7.1 Emulation Modes The FREE and SOFT bits of the power and emulation management register (PWREMU_MGMT) determine the response of the HPI to an emulation suspend condition.
HPI Registers www.ti.com 8 HPI Registers 8.1 Introduction Table 6 lists the memory-mapped registers for the Host Port Interface (HPI). See the device-specific data manual for the memory address of these registers.
www.ti.com HPI Registers 8.2 Power and Emulation Management Register (PWREMU_MGMT) The power management and emulation register is shown in Figure 29 and described in Table 7 .
HPI Registers www.ti.com 8.3 Host Port Interface Control Register (HPIC) The HPIC register stores control and status bits used to configure and operate the HPI peripheral. The bit positions of the HPIC register and their functions are illustrated in Table 8 .
www.ti.com HPI Registers Table 8. Host Port Interface Control Register (HPIC) Field Descriptions (continued) Bit Field Value Description 9 DUALHPIA Dual-HPIA mode bit (configured by the host). 0 Single-HPIA mode. From the host's perspective, there is one 32-bit HPIA register.
HPI Registers www.ti.com 8.4 Host Port Interface Address Registers (HPIAW and HPIAR) There are two 32-bit HPIA registers: HPIAW for write operations and HPIAR for read operations.
www.ti.com HPI Registers 8.5 Data Register (HPID) The 32-bit register HPID provides the data path between the host and the HPI DMA logic. During a host write cycle, the host fills HPID with 32 bits, and then the HPI DMA logic transfers the 32-bit value to the internal memory of the DSP.
www.ti.com Appendix A Revision History This revision history highlights the technical changes made to the document in this revision. Table 11. TMS320C6457 HPI Revision History See Additions/Modificati.
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