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TMS320C645x Serial Rapid IO (SRIO) User's Guide Literature Number: SPRU976 March 2006.
2 SPRU976 – March 2006 Submit Documentation Feedback.
Contents Preface .............................................................................................................................. 13 1 Overview .............................................................................................
5.25 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) .................. 126 5.26 DOORBELL n Interrupt Condition Routing Register (DOORBELL n _ICRR) .............................. 127 5.27 DOORBELL n Interrupt Condition Routing Register 2 (DOORBELL n _ICRR2) .
5.72 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) ................................... 174 5.73 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) ..................................... 175 5.74 Base Device ID CSR (BASE_ID) ......
List of Figures 1 RapidIO Architectural Hierarchy .......................................................................................... 15 2 RapidIO Interconnect Architecture .......................................................................
52 Load/Store Module Interrupt Condition Routing Registers ............................................................ 82 53 Error, Reset, and Special Event Interrupt Condition Routing Registers ............................................ 83 54 Sharing of ISDR Bits .
105 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUE n _TXDMA_HDP) .......................... 150 106 Queue Transmit DMA Completion Pointer Registers (QUEUE n _TXDMA_CP) .................................. 151 107 Queue Receive DMA Head Descriptor Pointer Registers (QUEUE n _RXDMA_HDP) .
158 Port Error Rate Threshold CSR n (SP n _ERR_THRESH) ........................................................... 206 159 Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) .............................................. 207 160 Port IP Mode CSR (SP_IP_MODE) .
List of Tables 1 RapidIO Documents and Links ........................................................................................... 18 2 Packet Type .................................................................................................
50 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) Field Descriptions ......................................... 121 51 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) Field Descriptions .......................................... 122 52 LSU Status Interrupt Register (LSU_ICSR) Field Descriptions .
99 Source Operations CAR (SRC_OP) Field Descriptions ............................................................. 171 100 Destination Operations CAR (DEST_OP) Field Descriptions ....................................................... 172 101 Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions .
Preface SPRU976 – March 2006 Read This First About This Manual This document describes the Serial Rapid IO (SRIO) on the TMS320C645x devices. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h.
1 Overview 1.1 General RapidIO System User's Guide SPRU976 – March 2006 Serial RapidIO (SRIO) The RapidIO peripheral used in the TMS320C645x is called a serial RapidIO (SRIO).
www.ti.com Globally shared memory spec logical Future Message passing system I/O Logical specification Information necessary for the end point to process the transaction (i.
www.ti.com Host Subsystem I/O Control Subsystem DSP Farm TDM,GMII, Utopia Communications Subsystem PCI Subsystem InfiniBand HCA ™ T o System Area Network Memory Memory Memory Memory RapidIO RapidIO .
www.ti.com Serial RapidIO 1x Device to 1x Device Interface Diagram Serial RapidIO 4x Device to 4x Device Interface Diagram 1x Device TD[0] TD[0] RD[0] RD[0] TD[0] TD[0] 1x Device RD[0] RD[0] RD[0-3] RD[0-3] 4x Device TD[0-3] RD[0-3] RD[0-3] TD[0-3] 4x Device TD[0-3] TD[0-3] 1.
www.ti.com 1.3 Standards 1.4 External Devices Requirements Overview Features Not Supported: • Compliance with the Global Shared Memory specification (GSM) • 8/16 LP-LVDS compatible • Destination.
www.ti.com 2 SRIO Functional Description 2.1 Overview SRIO Functional Description 2.1.1 Peripheral Data Flow This peripheral is designed to be an external slave module that is capable of mastering the internal DMA.
www.ti.com 1.25-3.125 Gbps differential data Rx Clock recovery S2P 10b Clk 8b/10b decode 8b Clock recovery Rx 8b 8b/10b decode 10b Clk S2P Clock recovery Rx 8b 8b/10b decode 10b Clk S2P Clock recovery.
www.ti.com Initiator Request Packet Issued Operation Completed for Master Acknowledge Symbol Acknowledge Symbol Response Packet Forwarded Request Packet Forwarded Acknowledge Symbol Acknowledge Symbol.
www.ti.com double-word n-1 acklD rsv prio tt ftype destID sourcelD address rsrv xamsbs double-word 0 double-word 1 ... double-word n-2 CRC PHY LOG TRA LOG TRA PHY 5 3 2 2 4 8 8 29 1 2 64 64 (n-4)*64 6.
www.ti.com SRIO Functional Description The type of received packet determines how the packet routing is handled. Reserved or undefined packet types are destroyed before being processed by the logical layer functional blocks. This prevents erroneous allocation of resources to them.
www.ti.com 2.2 SRIO Pins 2.3 Functional Operation SRIO Functional Description The SRIO device pins are high-speed differential signals based on Current-Mode Logic (CML) switching levels. The transmit and receive buffers are self-contained within the clock recovery blocks.
www.ti.com Port 0 8 x 276 TX 8 x 276 RX 8 x 276 RX 8 x 276 TX Port 1 8 x 276 TX 8 x 276 RX Port 2 8 x 276 RX 8 x 276 TX Port 3 Physical layer buffers SERDES 0 SERDES 1 SERDES 2 SERDES 3 SERDES differe.
www.ti.com SRIO Functional Description 2.3.2 SERDES and its Configurations SRIO offers many benefits to customers by allowing a scalable non-proprietary interface. With the use of TI’s SERDES macros, the peripheral is very adaptable and bandwidth scalable.
www.ti.com SRIO Functional Description Table 4. Bits of SERDES_CFG n _CNTL Register (0x120 - 0x12c) (continued) Bit Name Value Description 5:1 MPY PLL multiply. Select PLL multiply factors between 4 and 60. Multiply modes shown below. 0000 4x 0001 5x 0010 6x 0011 Reserved 0100 8x 0101 10x 0110 12x 0111 12.
www.ti.com SRIO Functional Description Here is the frequency range versus MPY: Table 7. Frequency Range versus MPY MPY RIOCLK and RIOCLK Line Rate Range (Gbps) Range (MHz) Full Half Quarter 4x 250 - 425 2 - 3.4 1 - 1.7 0.5 - 0.85 5x 200 - 425 2 - 4.25 1 - 2.
www.ti.com SRIO Functional Description Table 8. Bits of SERDES_CFGRX n _CNTL Registers (continued) Bit Field Value Description 15:14 LOS Loss of signal. Enables loss of signal detection with 2 selectable thresholds. 00 Disabled. Loss of signal detection disabled.
www.ti.com SRIO Functional Description Table 9. EQ Bits CFGRX[22:19] Low Freq Gain Zero Freq (at e 28 (min)) 0000 Maximum - 0001 Adaptive Adaptive 001x Reserved 01xx Reserved 1000 Adaptive 1084MHz 1001 805MHz 1010 573MHz 1011 402MHz 1100 304MHz 1101 216MHz 1110 156MHz 1111 135MHz 2.
www.ti.com SRIO Functional Description Table 10. Bits of SERDES_CFGTX n _CNTL Registers (continued) Bit Field Value Description 4:2 BUS- Bus width. Selects the width of the parallel interface (10 or 8 bit). WIDTH 000 10-bit operation. Data is input on TD n [9:0].
www.ti.com Configuration/Status Register and T ables (32-bit) Output Buffers (64-bit) RapidIO Endpoint IT Generator ASIC Device RapidIO Endpoint L2 CPU Step 2. IT to CPU for end transfer completion Step 1. ASIC writes through RapidIO to L2 SRIO Functional Description 2.
www.ti.com LSU_Reg0 RapidIO Address MSB Control 31 RapidIO Address LSB/Config_offset Control 31 0 LSU_Reg1 DSP Address Control 31 0 LSU_Reg2 RSV Control 31 0 LSU_Reg3 12 1 1 Byte_count OutPortID Contr.
www.ti.com SRIO Functional Description Table 13. Control/Command Register Field Mapping (continued) Control/Command Register RapidIO Packet Header Field Field Packet Type 4 msb = 4b ftype field for all packets and 4 lsb = 4b trans field for packet types 2,5,8.
www.ti.com LSU_Reg1 T0 T1 T2 T3 T4 T5 Tn V alid LSU_Reg2 V alid LSU_Reg3 V alid LSU_Reg4 V alid LSU_Reg5 V alid Rdy/BSY Completion V alid V alid After T ransaction Completes SRIO Functional Description Figure 11. LSU Registers Timing The following code illustrates an LSU registers programming example.
www.ti.com Source Address DMA Read Destination Address Count Byte Count DSP Address RSV Interrupt Req 0 0 1 7 23 8 DestID 25 24 ID Size 27 26 xambs 29 28 Priority OutPortID 31 30 Hop Count Drbll 31 16.
www.ti.com LSU2 LSU4 LSU3 LSU1 MMR command UDI interface Load/store module RapidIO transport and physical layers Port x transmission FIFO queues TX FIFO RX FIFO Peripheral boundary Config bus access W.
www.ti.com SRIO Functional Description For posted WRITE operations, which do not require a RapidIO response packet, a core may submit multiple outstanding requests. For instance, a single core may have many streaming write packets buffered at any given time, given outgoing resources.
www.ti.com SRIO Functional Description Segmentation: The LSU handles two types of segmentation of outbound requests. The first type is when the Byte_Count of Read/Write requests exceeds 256 bytes (up to 4KB). The second type is when Read/Write request RapidIO address is non-64b aligned.
www.ti.com SRIO Functional Description So the general flow is as follows: • Previously, the control/command registers were written and the request packet was sent • Response Packet Type13, Trans !.
www.ti.com Mailbox 1...64 from RapidIO Packet Header - Received on any input port Mailbox Mapper Q15 Q2 Q1 Q0 Queue assignable to any core Packet Sequence Message n A Packet Manager n+1 B n+2 B n + 3 .
www.ti.com msglen msgseg/ xmbox mbox letter 4 4 2 2 Single Segment Mailbox 0 ... 63 Multi-Segment Mailbox 0 ... 4 SOURCEID = SourceID allowed access if secure queue Mailbox = Allowed mailbox for this mapping register (Mask-able) 0b000000 - Mailbox 0 0b000001 - Mailbox 1 0b000010 - Mailbox 2 .
www.ti.com SRIO Functional Description Figure 17. Queue Mapping Register RXU_MAP_L n 31 30 29 24 23 22 21 16 Letter Mask Mailbox Mask Letter Mailbox R/W-11 R/W-111111 R/W-0 R/W-000000 15 0 SOURCEID R/W-0x0000 LEGEND: R = Read, W = Write, n = value at reset Figure 18.
www.ti.com 31 0 1 2 15 23 7 27 1 1 19 3 29 O W N E R S H I P T E A R D O W N E O P E O Q S O P 3 RESERVED cc Message Length 13 21 5 25 9 17 1 30 14 22 6 26 10 18 2 28 12 20 4 24 8 16 0 Bit Fields Next.
www.ti.com SRIO Functional Description Table 17. RX Buffer Descriptor Field Descriptions Field Description next_descriptor_pointer Next Descriptor Pointer: The 32-bit word aligned memory address of the next buffer descriptor in the RX queue. This references the next buffer descriptor from the current buffer descriptor.
www.ti.com SRIO Functional Description Table 17. RX Buffer Descriptor Field Descriptions (continued) Field Description mailbox Destination Mailbox: Specifies the mailbox to which the message was sent. 000000b: Mailbox 0 000001b: Mailbox 1 ... 000100b: Mailbox 4 .
www.ti.com Switch Switch Endpoint Endpoint C0 C0 B0 B0 B2 B2 A1 A1 B1 B1 A0 A0 Open Open Open Open Open Open Open Full Open Open Full Full Retry Retry Retry Retry Retry Retry Accept Retry Retry Retry .
www.ti.com CPPI block CPU DMA Config bus access L2 memory Bu ffe r de sc ri pto r du al -p ort SR AM (N x2 0B ) Da ta b uff er Peripheral boundary 32 32 32 128 C P P I c o nt r o l r e g i s t e r s S.
www.ti.com 31 0 1 2 15 23 7 27 1 1 19 3 29 O W N E R S H I P T E A R D O W N E O P E O Q S O P 3 Reserved Retry_count cc Message Length 13 21 5 25 9 17 1 30 14 22 6 26 10 18 2 28 12 20 4 24 8 16 0 Bit Fields Next Descriptor Pointer Buffer Pointer Dest_ID PRI tt SSIZE Mailbox Port_ID Word Offset SRIO Functional Description 2.
www.ti.com SRIO Functional Description Table 20. TX Buffer Descriptor Field Definitions (continued) Field Description ownership Ownership: Indicates ownership of the message and is valid only on sop. This bit is set by the host and cleared by the port when the message has been transmitted.
www.ti.com SRIO Functional Description Table 20. TX Buffer Descriptor Field Definitions (continued) Field Description tt RapidIO tt field specifying 8- or 16-bit DeviceIDs 00: 8b deviceIDs 01: 16b deviceIDs 10: reserved 11: reserved PortID Port number for routing outgoing packet.
www.ti.com SRIO Functional Description Figure 23. Weighted Round Robin Programming Registers (Address Offset 0x7E0 – 0x7EC) TX_QUEUE_CNTL0- Address Offset (0x7E0) 31 24 23 16 TX_Queue_Map3 TX_Queue_.
www.ti.com SRIO Functional Description Table 21. Weighted Round Robin Programming Registers (Address Offset 0x7E0 – 0x7EC) (continued) Name Bit Access Reset Value Description TX_Queue_Map10 [23:16] .
www.ti.com SRIO Functional Description Essentially, instead of the 24-bit value representing the period of the response timer, the period is now defined as P = (2^24 x 16)/F. This means the countdown timer frequency needs to be 44.7 – 89.5Mhz for a 6 – 3 second response timeout.
www.ti.com SRIO Functional Description The CPPI module can be powered down if the message passing protocol is not being supported in the application. For example, if the direct I/O protocol is being used for data transfers, powering down the CPPI module will save power.
www.ti.com SRIO Functional Description • This value is compared against the port written value in the TX DMA State CP register, if equal, the interrupt is deasserted.
www.ti.com Descriptor Descriptor Buffer Buffer Port Rx DMA State Rx Queue Head Descriptor Pointer SRIO Functional Description Figure 24. RX Buffer Descriptor TX Buffer Descriptor TX_DESCP0_0->TXDES.
www.ti.com Descriptor Descriptor Buffer Buffer Port Tx DMA State Tx Queue Head Descriptor Pointer SRIO Functional Description Figure 25. TX Buffer Descriptor Start Message Passing SRIO_REGS->Queue0_RXDMA_HDP = (int )RX_DESCP0_0 ; SRIO_REGS->Queue0_TxDMA_HDP = (int )TX_DESCP0_0 ; 2.
www.ti.com acklD rsv prio tt 1010 destID sourcelD Reserved srcTID Reserved Doorbell Reg # rsv Doorbell bit CRC PHY LOG TRA LOG TRA PHY 5 3 2 2 4 8 8 8 8 9 2 1 4 16 16 32 16 4 2 10 info (msb) 8 info (lsb) 8 SRIO Functional Description 2.
www.ti.com SRIO Functional Description 2.3.7 Congestion Control The RapidIO Flow Control specification is referenced in Table 1 . This section describes the requirements and implementation of congestion control within the peripheral. The peripheral is notified of switch fabric congestion through type 7 RapidIO packets.
www.ti.com Reserved RIO_FLOW_CNTL0 31 R, all zeros tt 17 R/W , 0b01 Flow_Cntl_ID0 15 R/W , 0x0000 Reserved RIO_FLOW_CNTL1 31 R, all zeros tt 17 R/W , 0b01 Flow_Cntl_ID1 15 R/W , 0x0000 Reserved RIO_FL.
www.ti.com Reserved RIO_LSUn_FLOW_MASKS (Address Offsets: 0x041C, 0x043C, 0x045C, 0x047C) 31-16 R, 0x0000 LSU n Flow Mask 15-0 R/W , 0xFFFF TX Queue1 Flow Mask RIO_TX_CPPI_FLOW_MASKS0 (Address Offsets.
www.ti.com A0 A0 A2 A2 A1 A1 A3 A3 L2 offset 0x0 DSP defined MMR offset 0x1000 Byte lane 0 31 Byte lane 3 DMA 32b 0 SRIO Functional Description 2.3.8 Endianness RapidIO is based on big endian. This is discussed in detail in section 2.4 of the RapidIO Interconnect specification.
www.ti.com DMA Example The desired operation is to send a T ype 8 maintenance request to an external device. The goal is to read 16B of RapidIO MMR from an external device, starting offset 0x0000. This operation involves the LSU block and utilizes the DMA for transferring the response packet payload.
www.ti.com SRIO Functional Description 2.3.9.1 Reset Summary After reset, the state of the peripheral depends on the default register values and the BLK n _EN_INIT tieoff values. You can also perform a hard reset using the software of each logical block within the peripheral via the GBL_EN and BLK n _EN bits.
www.ti.com SRIO Functional Description Figure 34. BLK0_EN_STAT (Address 0x003C) 31 1 0 Reserved EN_STAT R-0 R-1 LEGEND: R = Read, W = Write, n = value at reset Figure 35. BLK1_EN (Address 0x0040) 31 1 0 Reserved EN R-0 R/W-1 LEGEND: R = Read, W = Write, n = value at reset Figure 36.
www.ti.com SRIO Functional Description Table 24. Enable and Enable Status Bit Field Descriptions (continued) Name Bit Access Description BLK1_EN 0 R/W Controls reset to logical block 1, which is the LSU.
www.ti.com SRIO Functional Description Table 24. Enable and Enable Status Bit Field Descriptions (continued) Name Bit Access Description BLK8_EN_STAT 0 R Indicates state of BLK8_EN reset signal. 0 = Logical block 8 in reset and clock is off 1 = Logical block 8 enabled and clocking The GBL_EN register is implemented with a single ENABLE bit.
www.ti.com SRIO Functional Description Table 25. Emulation Control Signals Name Bit Access Reset Value Description Free 0 R/W 1b FREE = 0, SOFT Bit takes effect FREE = 1, Free run mode (default mode) - Peripheral ignores the EMUSUSP signal and functions normally.
www.ti.com SRIO Functional Description 2.3.11.2 PLL, Ports, Device ID and Data Rate Initializations For example, Enable pll, 333MHz, 4p1x, x20. 3.125 Gbps, full rate, ½ rate, ¼ rate: if (srio4p1x_mo.
www.ti.com SRIO Functional Description } else{ SRIO_REGS->SP_IP_MODE = 0x04000000; // Jadis mltc/rst/pw enable, clear } SRIO_REGS->IP_PRESCAL = 0x00000021; // srv_clk prescalar=0x21 (333MHz) SRI.
www.ti.com Boot Program Host Controller Optional I2C EEPROM DSP ROM 1x RapidIO SRIO Functional Description 2.3.12 Bootload Capability 2.3.12.1 Configuration It is assumed that an external device will initiate the bootload data transfer and master the DMA interface.
www.ti.com 3 Logical/Transport Error Handling and Logging Logical/Transport Error Handling and Logging Error management registers allow detection and logging of logical/transport layer errors.
www.ti.com 4 Interrupt Conditions 4.1 CPU Interrupts 4.2 General Description acklD rsv prio tt 1010 destID sourcelD Reserved srcTID Reserved Doorbell Reg # rsv Doorbell bit CRC PHY LOG TRA LOG TRA PHY.
www.ti.com 4.3 Interrupt Condition Control Registers Interrupt Conditions The DOORBELL packet’s 16-bit INFO field indicates which DOORBELL register interrupt bit to set. There are four DOORBELL registers, each currently with 16 bits, allowing 64 interrupt sources or circular buffers.
www.ti.com Interrupt Conditions Table 26. Interrupt Source Configuration Options Field Access Reset Value Value Function ICSx R 0 0b Condition not present 1b Condition present ICCx W 0 0b No effect 1b Condition status cleared Figure 43.
www.ti.com Interrupt Conditions Where ICS0 - Doorbell1, bit 0, through ICS15 - Doorbell1, bit 15. Figure 45. DOORBELL2 Interrupt Registers for Direct I/O Transfers DOORBELL2 Interrupt Condition Status.
www.ti.com Interrupt Conditions Figure 47. RX_CPPI Interrupts Using Messaging Mode Data Transfers RX_CPPI Interrupt Condition Status Registers (ICSR) (Address Offset 0x0240) 31 16 Reserved R-0 15 14 1.
www.ti.com Interrupt Conditions Where ICS0 - TX CPPI interrupt, buffer descriptor queue 0, through ICS15 - TX CPPI interrupt, buffer descriptor queue 15. Clearing of any ICSR bit is dependent on the CPU writing to the TX DMA State CP. The CPU acknowledges the interrupt after reclaiming all available buffer descriptors by writing the CP value.
www.ti.com Interrupt Conditions • Bit 21- Transaction was not sent due to DMA data transfer error, LSU3 • Bit 22- Retry Doorbell response received or Atomic Test-and-swap was not allowed (semaphor.
www.ti.com Interrupt Conditions The interrupt conditions are programmable to select the interrupt output that will be driven. Each condition is independently programmable to use any of the interrupt destinations supported by the device.
www.ti.com Interrupt Conditions Figure 52. Load/Store Module Interrupt Condition Routing Registers LSU_ICRR0 (Address Offset 0x02E0) 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R/W-0000 R/W-0000 R/W-0.
www.ti.com 4.4 Interrupt Status Decode Registers Interrupt Conditions Figure 53. Error, Reset, and Special Event Interrupt Condition Routing Registers ERR_RST_EVNT_ICRR (Address Offset 0x02F0) 31 12 1.
www.ti.com 31 30 29 28 27 26 25 24 23 22 21 20 19 16 18 17 LSU Error , reset and special event Tx CPPI [15:0] Rx CPPI [15:0] ISDR bits: 15 ISDR bits: 14 13 12 1 1 6 8 10 9 7 5 4 3 2 0 1 Doorbell 0 [15.
www.ti.com 4.5 Interrupt Generation 4.6 Interrupt Pacing Interrupt Conditions LSU bits within the ICSR are logically grouped for a given core and ORd together into a single bit of the decode register. Similarly, the Error/Reset/Special event bits within the ICSR are ORd together into a single bit of the decode register.
www.ti.com 4.7 Interrupt Handling Interrupt Conditions Figure 57. INTDST n _RATE_CNTL Interrupt Rate Control Register 31 0 32-bit Count Down Value R/W-0 LEGEND: R = Read, W = Write, n = value at reset.
www.ti.com Interrupt Conditions interruptStatus[11] = SRIO_REGS->ERR_RST_EVNT_ICSR; interruptStatus[12] = SRIO_REGS->ERR_RST_EVNT_ICCR; SRIO_REGS->DOORBELL0_ICCR=0xFFFFFFFF; SRIO_REGS->DOO.
www.ti.com 5 SRIO Registers 5.1 Introduction SRIO Registers Table 28 lists the memory-mapped registers for the Serial Rapid IO (SRIO). See the device-specific data manual for the memory address of these registers.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x0110 SERDES_CFGTX0_ SERDES Transmit Channel Configuration Register 0 Section 5.14 CNTL 0x0114 SERDES_CFGTX1_ SERDES Transmit Channel Configuration Register 1 Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x02EC LSU_ICRR3 LSU Interrupt Condition Routing Register 3 Section 5.35 0x02F0 ERR_RST_EVNT_IC Error, Reset, and Special Event Interrupt Condition Routing Register Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x0444 LSU3_REG1 LSU3 Control Register 1 Section 5.42 0x0448 LSU3_REG2 LSU3 Control Register 2 Section 5.43 0x044C LSU3_REG3 LSU3 Control Register 3 Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x0584 QUEUE1_TXDMA_C Queue Transmit DMA Completion Pointer Register 1 Section 5.50 P 0x0588 QUEUE2_TXDMA_C Queue Transmit DMA Completion Pointer Register 2 Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x0630 QUEUE12_RXDMA_ Queue Receive DMA Head Descriptor Pointer Register 12 Section 5.51 HDP 0x0634 QUEUE13_RXDMA_ Queue Receive DMA Head Descriptor Pointer Register 13 Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x071C TX_CPPI_FLOW_MA Transmit CPPI Supported Flow Mask Register 6 Section 5.54 SKS6 0x0720 TX_CPPI_FLOW_MA Transmit CPPI Supported Flow Mask Register 7 Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x0890 RXU_MAP_L18 MailBox-to-Queue Mapping Register L18 Section 5.61 0x0894 RXU_MAP_H18 MailBox-to-Queue Mapping Register H18 Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x1008 ASBLY_ID Assembly Identity CAR Section 5.66 0x100C ASBLY_INFO Assembly Information CAR Section 5.67 0x1010 PE_FEAT Processing Element Features CAR Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x2048 SP0_ERR_ATTR_CA Port 0 Attributes Error Capture CSR 0 Section 5.96 PT_DBG0 0x204C SP0_ERR_CAPT_DB Port 0 Packet/Control Symbol Error Capture CSR 1 Section 5.
www.ti.com SRIO Registers Table 28. Serial Rapid IO (SRIO) Registers (continued) Offset Acronym Register Description Section 0x2128 SP3_ERR_RATE Port 3 Error Rate CSR Section 5.101 0x212C SP3_ERR_THRESH Port 3 Error Rate Threshold CSR Section 5.102 0x12000 SP_IP_DISCOVERY Port IP Discovery Timer in 4x mode Section 5.
www.ti.com 5.2 Peripheral Identification Register (PID) SRIO Registers The peripheral identification register (PID) is a constant register that contains the ID and ID revision number for that peripheral. The PID stores version information used to identify the peripheral.
www.ti.com 5.3 Peripheral Control Register (PCR) SRIO Registers The peripheral control register (PCR) contains a bit that enables or disables the entire peripheral and one bit for every module within the peripheral where this level of control is desired.
www.ti.com 5.4 Peripheral Settings Control Register (PER_SET_CNTL) SRIO Registers Figure 60. Peripheral Settings Control Register (PER_SET_CNTL) 31-27 26 25 24 23-21 20-18 17-16 Reserved SW_M LOOP BOO.
www.ti.com SRIO Registers Table 31. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued) Bit Field Value Description 17-15 TX_PRI1_WM Transmit credit threshold. Sets the required number of logical layer TX buffers needed to send priority 1 packets across the UDI interface.
www.ti.com SRIO Registers Table 31. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued) Bit Field Value Description 2 ENPLL3 Drives SERDES Macro 3 PLL Enable signal 0b D.
www.ti.com 5.5 Peripheral Global Enable Register (GBL_EN) SRIO Registers Figure 61. Peripheral Global Enable Register (GBL_EN) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-1 0 Reserved EN R-0x00 RW- 0x00 LEGEND: R = Read only; - n = value after reset Table 32.
www.ti.com 5.6 Peripheral Global Enable Status Register (GBL_EN_STAT) SRIO Registers Figure 62. Peripheral Global Enable Status Register (GBL_EN_STAT) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15 1 0 Reserved GBL_ EN_S TAT R-0x00 R- Undefi ned LEGEND: R = Read only; - n = value after reset Table 33.
www.ti.com 5.7 Block n Enable Register (BLK n_EN) SRIO Registers There are nine of these registers, one for each of nine logical blocks in the peripheral.
www.ti.com 5.8 Block n Enable Status Register (BLK n_EN_STAT) SRIO Registers There are nine of these registers, one for each of nine logical blocks in the peripheral.
www.ti.com 5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1) SRIO Registers Figure 65. RapidIO DEVICEID1 Register (DEVICEID_REG1) 31-24 23-16 Reserved 8BNODEID R-0x0000 RW-0x00FF LEGEND: R = Read only; - n = value after reset 15-0 16BNODEID RW-0xFFFF LEGEND: R = Read only; - n = value after reset Table 36.
www.ti.com 5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2) SRIO Registers Figure 66. RapidIO DEVICEID2 Register (DEVICEID_REG2) 31-24 23-16 Reserved 8BNODEID R-0x0000 RW-0x00FF LEGEND: R = Read only; - n = value after reset 15-0 16BNODEID RW-0xFFFF LEGEND: R = Read only; - n = value after reset Table 37.
www.ti.com 5.11 Packet Forwarding Register n for 16b DeviceIDs (PF_16B_CNTL n) SRIO Registers There are four of these registers, to support four ports.
www.ti.com 5.12 Packet Forwarding Register n for 8b DeviceIDs (PF_8B_CNTL n) SRIO Registers There are four of these registers, to support four ports. Figure 68.
www.ti.com 5.13 SERDES Receive Channel Configuration Registers n (SERDES_CFGRX n_CNTL) SRIO Registers There are four of these registers, to support four ports.
www.ti.com SRIO Registers Table 40. SERDES Receive Channel Configuration Registers n (SERDES_CFGRX n _CNTL) Field Descriptions (continued) Bit Field Value Description 11 Reserved Reserved. 10:8 TERM Termination. Selects input termination options suitable for a variety of AC or DC coupled scenarios.
www.ti.com 5.14 SERDES Transmit Channel Configuration Registers n (SERDES_CFGTX n_CNTL) SRIO Registers There are four of these registers, to support four ports.
www.ti.com SRIO Registers Table 43. SWING Bits CFGTX[11:9] Amplitude (mV dfpp ) 000 125 001 250 010 500 011 625 100 750 101 1000 110 1125 111 1250 Table 44. DE Bits CFGTX[15:12] Amplitude Reduction % dB 0000 0 0 0001 4.76 -0.42 0010 9.52 -0.87 0011 14.
www.ti.com 5.15 SERDES Macro Configuration Register n (SERDES_CFG n_CNTL) SRIO Registers There are four of these registers, to support four ports. Figure 71.
www.ti.com 5.16 DOORBELL n Interrupt Status Register (DOORBELL n_ICSR) SRIO Registers Each of the four doorbells is supported by a register of this type.
www.ti.com 5.17 DOORBELL n Interrupt Clear Register (DOORBELL n_ICCR) SRIO Registers Each of the four doorbells is supported by a register of this type.
www.ti.com 5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) SRIO Registers Figure 74. RX CPPI Interrupt Status Register (RX_CPPI_ICSR) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ICS (0-15) R-0x00 LEGEND: R = Read only; - n = value after reset Table 48.
www.ti.com 5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) SRIO Registers Figure 75. RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ICC (0-15) W-0x00 LEGEND: R = Read only; - n = value after reset Table 49.
www.ti.com 5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) SRIO Registers Figure 76. TX CPPI Interrupt Status Register (TX_CPPI_ICSR) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ICS (0-15) R-0x00 LEGEND: R = Read only; - n = value after reset Table 50.
www.ti.com 5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) SRIO Registers Figure 77. TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ICC (0-15) W-0x00 LEGEND: R = Read only; - n = value after reset Table 51.
www.ti.com 5.22 LSU Status Interrupt Register (LSU_ICSR) SRIO Registers Figure 78. LSU Status Interrupt Register (LSU_ICSR) 31-16 ICS(31-16) R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ICS(15-0) R-0x00 LEGEND: R = Read only; - n = value after reset Table 52.
www.ti.com 5.23 LSU Clear Interrupt Register (LSU _ICCR) SRIO Registers Figure 79. LSU Clear Interrupt Register (LSU _ICCR) 31-16 ICC(31-16) W-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ICC(15-0) W-0x00 LEGEND: R = Read only; - n = value after reset Table 53.
www.ti.com 5.24 Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) SRIO Registers Figure 80. Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) 31.
www.ti.com 5.25 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) SRIO Registers Figure 81. Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) 31-1.
www.ti.com 5.26 DOORBELL n Interrupt Condition Routing Register (DOORBELL n_ICRR) SRIO Registers Each of the four doorbells is supported by a register of this type.
www.ti.com 5.27 DOORBELL n Interrupt Condition Routing Register 2 (DOORBELL n_ICRR2) SRIO Registers Each of the four doorbells is supported by a register of this type.
www.ti.com 5.28 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) SRIO Registers Figure 84. RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) 31 28 27 24 23 20 19 16 ICR7 ICR6 IC.
www.ti.com 5.29 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) SRIO Registers Figure 85. RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) 31 28 27 24 23 20 19 16 ICR15 ICR1.
www.ti.com 5.30 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) SRIO Registers Figure 86. TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) 31 28 27 24 23 20 19 16 ICR7 ICR6 IC.
www.ti.com 5.31 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) SRIO Registers Figure 87. TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) 31 28 27 24 23 20 19 16 ICR15 ICR1.
www.ti.com 5.32 LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) SRIO Registers Figure 88. LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) 31 28 27 24 23 20 19 16 ICR7 ICR6 .
www.ti.com 5.33 LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) SRIO Registers Figure 89. LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) 31 28 27 24 23 20 19 16 ICR15 ICR1.
www.ti.com 5.34 LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) SRIO Registers Figure 90. LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) 31 28 27 24 23 20 19 16 ICR23 ICR2.
www.ti.com 5.35 LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) SRIO Registers Figure 91. LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) 31 28 27 24 23 20 19 16 ICR31 ICR3.
www.ti.com 5.36 Error, Reset, and Special Event Interrupt Condition Routing Register SRIO Registers (ERR_RST_EVNT_ICRR) Figure 92. Error, Reset, and Special Event Interrupt Condition Routing Register .
www.ti.com 5.37 Error, Reset, and Special Event Interrupt Condition Routing Register 2 SRIO Registers (ERR_RST_EVNT_ICRR2) Figure 93. Error, Reset, and Special Event Interrupt Condition Routing Regist.
www.ti.com 5.38 Error, Reset, and Special Event Interrupt Condition Routing Register 3 SRIO Registers (ERR_RST_EVNT_ICRR3) Figure 94. Error, Reset, and Special Event Interrupt Condition Routing Regist.
www.ti.com 5.39 INTDST n Interrupt Status Decode Registers (INTDST n_DECODE) SRIO Registers There are eight of these registers. Figure 95. INTDST n Interrupt Status Decode Registers (INTDST n _DECODE).
www.ti.com 5.40 INTDST n Interrupt Rate Control Registers (INTDST n_RATE_CNTL) SRIO Registers There are eight of these registers. Figure 96. INTDST n Interrupt Rate Control Registers (INTDST n _RATE_C.
www.ti.com 5.41 LSU n Control Register 0 (LSU n_REG0) SRIO Registers There are four of these registers, one for each LSU. Figure 97. LSU n Control Register 0 (LSU n _REG0) 31-16 ADDRESS_MSB RW-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ADDRESS_MSB RW-0x00 LEGEND: R = Read only; - n = value after reset Table 71.
www.ti.com 5.42 LSU n Control Register 1 (LSU n_REG1) SRIO Registers There are four of these registers, one for each LSU. Figure 98. LSU n Control Register 1 (LSU n _REG1) 31-16 ADDRESS_LSB_CONFIG_OFF.
www.ti.com 5.43 LSU n Control Register 2 (LSU n_REG2) SRIO Registers There are four of these registers, one for each LSU. Figure 99. LSU n Control Register 2 (LSU n _REG2) 31-16 DSP_ADDRESS RW-0x00 LEGEND: R = Read only; - n = value after reset 15-0 DSP_ADDRESS RW-0x00 LEGEND: R = Read only; - n = value after reset Table 73.
www.ti.com 5.44 LSU n Control Register 3 (LSU n_REG3) SRIO Registers There are four of these registers, one for each LSU. Figure 100. LSU n Control Register 3 (LSU n _REG3) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-12 11-0 Reserved BYTE_COUNT R-0x00 RW-0x00 LEGEND: R = Read only; - n = value after reset Table 74.
www.ti.com 5.45 LSU n Control Register 4 (LSU n_REG4) SRIO Registers There are four of these registers, one for each LSU. Figure 101. LSU n Control Register 4 (LSU n _REG4) 31-30 29-28 27-26 25-24 23-.
www.ti.com 5.46 LSU n Control Register 5 (LSU n_REG5) SRIO Registers There are four of these registers, one for each LSU. Figure 102. LSU n Control Register 5 (LSU n _REG5) 31-16 DRBLL_INFO RW-0x00 LEGEND: R = Read only; - n = value after reset 15-8 7-0 HOP_COUNT PACKET_TYPE RW-0x00 RW-0x00 LEGEND: R = Read only; - n = value after reset Table 76.
www.ti.com 5.47 LSU n Control Register 6 (LSU n_REG6) SRIO Registers There are four of these registers, one for each LSU. Figure 103. LSU n Control Register 6 (LSU n _REG6) 31-16 Reserved R-0x00 LEGEN.
www.ti.com 5.48 LSU Congestion Control Flow Mask n (LSU_FLOW_MASKS n) SRIO Registers Figure 104. LSU Congestion Control Flow Mask n (LSU_FLOW_MASKS n ) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 FLOW_MASK (0-15) RW-0x01 LEGEND: R = Read only; - n = value after reset Table 78.
www.ti.com 5.49 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUE n_TXDMA_HDP) SRIO Registers There are sixteen of these registers. Figure 105.
www.ti.com 5.50 Queue Transmit DMA Completion Pointer Registers (QUEUE n_TXDMA_CP) SRIO Registers There are sixteen of these registers. Figure 106. Queue Transmit DMA Completion Pointer Registers (QUE.
www.ti.com 5.51 Queue Receive DMA Head Descriptor Pointer Registers (QUEUE n_RXDMA_HDP) SRIO Registers There are sixteen of these registers. Figure 107.
www.ti.com 5.52 Queue Receive DMA Completion Pointer Registers (QUEUE n_RXDMA_CP) SRIO Registers There are sixteen of these registers. Figure 108. Queue Receive DMA Completion Pointer Registers (QUEUE.
www.ti.com 5.53 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) SRIO Registers Figure 109. Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n .
www.ti.com 5.54 Transmit CPPI Supported Flow Mask Registers n (TX_CPPI_FLOW_MASKS n) SRIO Registers There are eight registers of this type. See Figure 28 for more information on this register.
www.ti.com SRIO Registers Transmit CPPI Supported Flow Mask Register 7 (TX_CPPI_FLOW_MASKS7) 31-16 15-0 QUEUE15_FLOW_MASK QUEUE14_FLOW_MASK RW-0x01 RW-0x01 LEGEND: R = Read only; - n = value after reset Table 84.
www.ti.com 5.55 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) SRIO Registers Figure 111. Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = .
www.ti.com 5.56 Receive CPPI Control Register (RX_CPPI_CNTL) SRIO Registers Figure 112. Receive CPPI Control Register (RX_CPPI_CNTL) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after rese.
www.ti.com 5.57 Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) SRIO Registers Figure 113. Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) 31-28 27-24 23-.
www.ti.com 5.58 Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) SRIO Registers Figure 114. Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) 31-28 27-24 23-.
www.ti.com 5.59 Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) SRIO Registers Figure 115. Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) 31-28 27-24 23-.
www.ti.com 5.60 Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) SRIO Registers Figure 116. Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) 31-28 27-24 23-.
www.ti.com 5.61 Mailbox-to-Queue Mapping Register L n (RXU_MAP_L n) SRIO Registers Figure 117. Mailbox-to-Queue Mapping Register L n (RXU_MAP_L n ) 31-30 29-24 23-22 21-16 LETTER_MAS MAILBOX_MASK LETT.
www.ti.com 5.62 Mailbox-to-Queue Mapping Register H n (RXU_MAP_H n) SRIO Registers Figure 118. Mailbox-to-Queue Mapping Register H n (RXU_MAP_H n ) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = v.
www.ti.com 5.63 Flow Control Table Entry Registers (FLOW_CNTL n) SRIO Registers There are sixteen of these registers. Figure 119. Flow Control Table Entry Registers (FLOW_CNTL n ) 31-18 17-16 Reserved TT R-0x00 RW-0x01 LEGEND: R = Read only; - n = value after reset 15-0 FLOW_CNTL_ID RW-0x00 LEGEND: R = Read only; - n = value after reset Table 93.
www.ti.com 5.64 Device Identity CAR (DEV_ID) SRIO Registers Figure 120. Device Identity CAR (DEV_ID) 31-16 DEVICEIDENTITY R-0x0000 LEGEND: R = Read only; - n = value after reset 15-0 DEVICE_VENDORIDENTITY R-0x0030 LEGEND: R = Read only; - n = value after reset Table 94.
www.ti.com 5.65 Device Information CAR (DEV_INFO) SRIO Registers Figure 121. Device Information CAR (DEV_INFO) 31-16 DEVICEREV R-0x0000 LEGEND: R = Read only; - n = value after reset 15-0 DEVICEREV R-0x0000 LEGEND: R = Read only; - n = value after reset Table 95.
www.ti.com 5.66 Assembly Identity CAR (ASBLY_ID) SRIO Registers Figure 122. Assembly Identity CAR (ASBLY_ID) 31-16 ASSY_IDENTITY R-0x0000 LEGEND: R = Read only; - n = value after reset 15-0 ASSY_VENDORIDENTITY R-0x0030 LEGEND: R = Read only; - n = value after reset Table 96.
www.ti.com 5.67 Assembly Information CAR (ASBLY_INFO) SRIO Registers Figure 123. Assembly Information CAR (ASBLY_INFO) 31-16 ASSYREV R-0x0000 LEGEND: R = Read only; - n = value after reset 15-0 EXTENDEDFEATURESPTR R-0x0100 LEGEND: R = Read only; - n = value after reset Table 97.
www.ti.com 5.68 Processing Element Features CAR (PE_FEAT) SRIO Registers Figure 124. Processing Element Features CAR (PE_FEAT) 31 30 29 28 27-16 BRIDG MEMO PROC SWIT Reserved E RY ESSO CH R R- R- R- R.
www.ti.com 5.69 Source Operations CAR (SRC_OP) SRIO Registers Figure 125. Source Operations CAR (SRC_OP) 31-18 17-16 Reserved IMPLMNT_DEF INED_2 R-0x00 R-0x00 LEGEND: R = Read only; - n = value after .
www.ti.com 5.70 Destination Operations CAR (DEST_OP) SRIO Registers Figure 126. Destination Operations CAR (DEST_OP) 31-18 17-16 Reserved IMPLMNT_DEF INED_2 R-0x00 R-0x00 LEGEND: R = Read only; - n = .
www.ti.com 5.71 Processing Element Logical Layer Control CSR (PE_LL_CTL) SRIO Registers Figure 127. Processing Element Logical Layer Control CSR (PE_LL_CTL) 31-16 Reserved R-0x0000 LEGEND: R = Read on.
www.ti.com 5.72 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) SRIO Registers Figure 128. Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) 31 30-16 Reserv LCSBA ed R- R-0x00 0x00 LEGEND: R = Read only; - n = value after reset 15-0 LCSBA R-0x00 LEGEND: R = Read only; - n = value after reset Table 102.
www.ti.com 5.73 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) SRIO Registers Figure 129. Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) 31-16 LCSBA R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 LCSBA R-0x00 LEGEND: R = Read only; - n = value after reset Table 103.
www.ti.com 5.74 Base Device ID CSR (BASE_ID) SRIO Registers Figure 130. Base Device ID CSR (BASE_ID) 31-24 23-16 Reserved BASE_DEVICEID R-0x00 RW-0x00FF LEGEND: R = Read only; - n = value after reset 15-0 LARGE_BASE_DEVICEID RW-0xFFFF LEGEND: R = Read only; - n = value after reset Table 104.
www.ti.com 5.75 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) SRIO Registers See Section 2.4.2 of the RapidIO Specification for description of this register.
www.ti.com 5.76 Component Tag CSR (COMP_TAG) SRIO Registers Figure 132. Component Tag CSR (COMP_TAG) 31-16 COMPONENT_TAG RW-0x00 LEGEND: R = Read only; - n = value after reset 15-0 COMPONENT_TAG RW-0x00 LEGEND: R = Read only; - n = value after reset Table 106.
www.ti.com 5.77 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) SRIO Registers Figure 133. 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) 31-16 EF_PTR R-0x1000 LEGEND: R = Read only; - n = value after reset 15-0 EF_ID R-0x0001 LEGEND: R = Read only; - n = value after reset Table 107.
www.ti.com 5.78 Port Link Time-Out Control CSR (SP_LT_CTL) SRIO Registers Figure 134. Port Link Time-Out Control CSR (SP_LT_CTL) 31-16 TIMEOUT_VALUE RW-0xFFFFFF LEGEND: R = Read only; - n = value after reset 15-8 7-0 TIMEOUT_VALUE Reserved RW-0xFFFFFF R-0x00 LEGEND: R = Read only; - n = value after reset Table 108.
www.ti.com 5.79 Port Response Time-Out Control CSR (SP_RT_CTL) SRIO Registers Figure 135. Port Response Time-Out Control CSR (SP_RT_CTL) 31-16 TIMEOUT_VALUE RW-0xFFFFFF LEGEND: R = Read only; - n = value after reset 15-8 7-0 TIMEOUT_VALUE Reserved RW-0xFFFFFF R-0x00 LEGEND: R = Read only; - n = value after reset Table 109.
www.ti.com 5.80 Port General Control CSR (SP_GEN_CTL) SRIO Registers Figure 136. Port General Control CSR (SP_GEN_CTL) 31 30 29 28-16 HOST MAST DISCO Reserved ER_E VERE NABL D E RW- RW- RW- R-0x00 0x00 0x00 0x00 LEGEND: R = Read only; - n = value after reset 15-0 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset Table 110.
www.ti.com 5.81 Port Link Maintenance Request CSR n (SP n_LM_REQ) SRIO Registers Each of the four ports is supported by a register of this type. Figure 137.
www.ti.com 5.82 Port Link Maintenance Response CSR n (SP n_LM_RESP) SRIO Registers Each of the four ports is supported by a register of this type. Figure 138.
www.ti.com 5.83 Port Local AckID Status CSR n (SP n_ACKID_STAT) SRIO Registers Each of the four ports is supported by a register of this type. Figure 139.
www.ti.com 5.84 Port Error and Status CSR n (SP n_ERR_STAT) SRIO Registers Each of the four ports is supported by a register of this type. Figure 140. Port Error and Status CSR n (SP n _ERR_STAT) 31-2.
www.ti.com SRIO Registers Table 114. Port Error and Status CSR n (SP n _ERR_STAT) Field Descriptions (continued) Bit Field Value Description 1 PORT_OK The input and output ports are initialized and the port is exchanging error-free control symbols with the attached device (read-only).
www.ti.com 5.85 Port Control CSR n (SP n_CTL) SRIO Registers Each of the four ports is supported by a register of this type. Figure 141. Port Control CSR n (SP n _CTL) 31-30 29-27 26-24 23 22 21 20 19.
www.ti.com SRIO Registers Table 115. Port Control CSR n (SP n _CTL) Field Descriptions (continued) Bit Field Value Description 21 INPUT_PORT_E Input port receive enable NABLE 0b Port is stopped and only enabled to route or respond I/O logical MAINTENANCE packets, depending upon the functionality of the processing element.
www.ti.com 5.86 Error Reporting Block Header (ERR_RPT_BH) SRIO Registers Figure 142. Error Reporting Block Header (ERR_RPT_BH) 31-16 EF_PTR R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 EF_ID R-0x0007 LEGEND: R = Read only; - n = value after reset Table 116.
www.ti.com 5.87 Logical/Transport Layer Error Detect CSR (ERR_DET) SRIO Registers Figure 143. Logical/Transport Layer Error Detect CSR (ERR_DET) 31 30 29 28 27 26 25 24 23 22 21-16 IO_ER MSG_ GSM_ ERR.
www.ti.com 5.88 Logical/Transport Layer Error Enable CSR (ERR_EN) SRIO Registers Figure 144. Logical/Transport Layer Error Enable CSR (ERR_EN) 31 30 29 28 27 26 25 24 23 22 21-16 IO_ERR_ MSG_E GSM_E E.
www.ti.com 5.89 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) SRIO Registers Figure 145. Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) 31-16 ADDRESS_63_32 R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 ADDRESS_63_32 R-0x00 LEGEND: R = Read only; - n = value after reset Table 119.
www.ti.com 5.90 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) SRIO Registers Figure 146. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) 31-16 ADDRESS_31_3 R-0x00 LEGEND: R = Read only; - n = value after reset 15-3 2 1-0 ADDRESS_31_3 Reserv XAMSBS ed R-0x00 R- R-0x00 0x00 LEGEND: R = Read only; - n = value after reset Table 120.
www.ti.com 5.91 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) SRIO Registers Figure 147. Logical/Transport Layer Device ID Capture CSR (ID_CAPT) 31-24 23-16 MSB_DESTID DESTID R-0x00 R-0x00 LEGEND: R = Read only; - n = value after reset 15-8 7-0 MSB_SOURCEID SOURCEID R-0x00 R-0x00 LEGEND: R = Read only; - n = value after reset Table 121.
www.ti.com 5.92 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) SRIO Registers Figure 148. Logical/Transport Layer Control Capture CSR (CTRL_CAPT) 31-28 27-24 23-16 FTYPE TTYPE MSGINFO R-0x00 R-0x00 R-0x00 LEGEND: R = Read only; - n = value after reset 15-0 IMP_SPECIFIC R-0x00 LEGEND: R = Read only; - n = value after reset Table 122.
www.ti.com 5.93 Port-Write Target Device ID CSR (PW_TGT_ID) SRIO Registers Figure 149. Port-Write Target Device ID CSR (PW_TGT_ID) 31-24 23-16 DEVICEID_MSB DEVICEID RW-0x00 RW-0x00 LEGEND: R = Read only; - n = value after reset 15-0 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset Table 123.
www.ti.com 5.94 Port Error Detect CSR n (SP n_ERR_DET) SRIO Registers Each of the four ports is supported by a register of this type. Figure 150. Port Error Detect CSR n (SP n _ERR_DET) 31 30-24 23 22.
www.ti.com 5.95 Port Error Rate Enable CSR n (SP n_RATE_EN) SRIO Registers Each of the four ports is supported by a register of this type. Figure 151. Port Error Rate Enable CSR n (SP n _RATE_EN) 31 3.
www.ti.com 5.96 Port n Attributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) SRIO Registers Each of the four ports is supported by a register of this type.
www.ti.com 5.97 Port n Packet/Control Symbol Error Capture CSR 1 (SP n_ERR_CAPT_DBG1) SRIO Registers Each of the four ports is supported by a register of this type.
www.ti.com 5.98 Port n Packet/Control Symbol Error Capture CSR 2 (SP n_ERR_CAPT_DBG2) SRIO Registers Each of the four ports is supported by a register of this type.
www.ti.com 5.99 Port n Packet/Control Symbol Error Capture CSR 3 (SP n_ERR_CAPT_DBG3) SRIO Registers Each of the four ports is supported by a register of this type.
www.ti.com 5.100 Port n Packet/Control Symbol Error Capture CSR 4 (SP n_ERR_CAPT_DBG4) SRIO Registers Each of the four ports is supported by a register of this type.
www.ti.com 5.101 Port Error Rate CSR n (SP n_ERR_RATE) SRIO Registers Each of the four ports is supported by a register of this type. Figure 157. Port Error Rate CSR n (SP n _ERR_RATE) 31-24 23-18 17-.
www.ti.com 5.102 Port Error Rate Threshold CSR n (SP n_ERR_THRESH) SRIO Registers Each of the four ports is supported by a register of this type. Figure 158.
www.ti.com 5.103 Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) SRIO Registers Figure 159. Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) 31-28 27-24 23-20 19-16 DISCOVERY_TIME.
www.ti.com 5.104 Port IP Mode CSR (SP_IP_MODE) SRIO Registers Figure 160. Port IP Mode CSR (SP_IP_MODE) 31-30 29 28 27 26 25 24-16 SP_MODE IDLE_ TX_FI PW_DI TGT_I SELF_ Reserved ERR_ FO_B S D_DIS RST .
www.ti.com SRIO Registers Table 134. Port IP Mode CSR (SP_IP_MODE) Field Descriptions (continued) Bit Field Value Description 3 RST_EN Reset Interrupt Enable. If enabled, the interrupt signal is High when the 4 reset control symbols are received in a sequence 0b Reset interrupt disable 1b Reset interrupt enable 2 RST_CS Reset received status bit.
www.ti.com 5.105 Serial Port IP Prescalar (IP_PRESCAL) SRIO Registers Figure 161. Serial Port IP Prescalar (IP_PRESCAL) 31-16 Reserved R-0x00 LEGEND: R = Read only; - n = value after reset 15-8 7-0 Reserved PRESCALE R-0x00 RW-0x0F LEGEND: R = Read only; - n = value after reset Table 135.
www.ti.com 5.106 Port-Write-In Capture CSR n (SP_IP_PW_IN_CAPT n) SRIO Registers Each of the four ports is supported by a register of this type. Figure 162.
www.ti.com 5.107 Port Reset Option CSR n (SP n_RST_OPT) SRIO Registers Each of the four ports is supported by a register of this type. Figure 163. Port Reset Option CSR n (SP n _RST_OPT) 31-16 Reserve.
www.ti.com 5.108 Port Control Independent Register n (SP n_CTL_INDEP) SRIO Registers Each of the four ports is supported by a register of this type. Figure 164.
www.ti.com SRIO Registers Table 138. Port Control Independent Register n (SP n _CTL_INDEP) Field Descriptions (continued) Bit Field Value Description 17 MAX_RETRY_EN Max_retry_error report enable. If enabled, the Port-Write and interrupt are reported as errors.
www.ti.com 5.109 Port Silence Timer n (SP n_SILENCE_TIMER) SRIO Registers Each of the four ports is supported by a register of this type. Figure 165. Port Silence Timer n (SP n _SILENCE_TIMER) 31-28 2.
www.ti.com 5.110 Port Multicast-Event Control Symbol Request Register n (SP n_MULT_EVNT_CS) SRIO Registers Each of the four ports is supported by a register of this type.
www.ti.com 5.111 Port Control Symbol Transmit n (SP n_CS_TX) SRIO Registers Each of the four ports is supported by a register of this type. Figure 167.
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